From 75325abce32fa076c74cf385bcd2d3b7705b147a Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Thu, 14 Mar 2024 19:38:31 -0700 Subject: [PATCH] OpcodeDispatcher: Implement rdpid Missed this instruction when implementing rdtscp. Returns the same ID result in a register just like rdtscp, but without the cycle counter results. Doesn't touch any flags just like rdtscp. --- FEXCore/Source/Interface/Core/CPUID.cpp | 2 +- .../Interface/Core/OpcodeDispatcher.cpp | 6 +++ .../Source/Interface/Core/OpcodeDispatcher.h | 1 + .../Core/X86Tables/SecondaryGroupTables.cpp | 2 +- unittests/ASM/Disabled_Tests_Simulator | 3 ++ unittests/ASM/Secondary/09_F3_07.asm | 17 +++++++ .../InstructionCountCI/SecondaryGroup.json | 46 +++++++++++++++++++ 7 files changed, 75 insertions(+), 2 deletions(-) create mode 100644 unittests/ASM/Secondary/09_F3_07.asm diff --git a/FEXCore/Source/Interface/Core/CPUID.cpp b/FEXCore/Source/Interface/Core/CPUID.cpp index 5be7b107f6..50315f1cdb 100644 --- a/FEXCore/Source/Interface/Core/CPUID.cpp +++ b/FEXCore/Source/Interface/Core/CPUID.cpp @@ -694,7 +694,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) const { (0 << 19) | // MPX MAWAU (0 << 20) | // MPX MAWAU (0 << 21) | // MPX MAWAU - (0 << 22) | // RDPID Read Processor ID + (1 << 22) | // RDPID Read Processor ID (0 << 23) | // Reserved (0 << 24) | // Reserved (0 << 25) | // CLDEMOTE diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 43603bdab7..d7733d3a4f 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5426,6 +5426,10 @@ void OpDispatchBuilder::RDTSCPOp(OpcodeArgs) { StoreGPRRegister(X86State::REG_RDX, Counter.CounterHigh); } +void OpDispatchBuilder::RDPIDOp(OpcodeArgs) { + StoreResult(GPRClass, Op, _ProcessorID(), -1); +} + void OpDispatchBuilder::CRC32(OpcodeArgs) { const uint8_t GPRSize = CTX->GetGPRSize(); @@ -6573,6 +6577,8 @@ constexpr uint16_t PF_F2 = 3; {OPD(FEXCore::X86Tables::TYPE_GROUP_9, PF_66, 1), 1, &OpDispatchBuilder::CMPXCHGPairOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_9, PF_F2, 1), 1, &OpDispatchBuilder::CMPXCHGPairOp}, + {OPD(FEXCore::X86Tables::TYPE_GROUP_9, PF_F3, 7), 1, &OpDispatchBuilder::RDPIDOp}, + // GROUP 12 {OPD(FEXCore::X86Tables::TYPE_GROUP_12, PF_NONE, 2), 1, &OpDispatchBuilder::PSRLI<2>}, {OPD(FEXCore::X86Tables::TYPE_GROUP_12, PF_NONE, 4), 1, &OpDispatchBuilder::PSRAIOp<2>}, diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index c6be701f6f..674cbb3b70 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -867,6 +867,7 @@ friend class FEXCore::IR::PassManager; void StoreFenceOrCLFlush(OpcodeArgs); void CLZeroOp(OpcodeArgs); void RDTSCPOp(OpcodeArgs); + void RDPIDOp(OpcodeArgs); void PSADBW(OpcodeArgs); diff --git a/FEXCore/Source/Interface/Core/X86Tables/SecondaryGroupTables.cpp b/FEXCore/Source/Interface/Core/X86Tables/SecondaryGroupTables.cpp index 4965b81d3d..ff92b372e5 100644 --- a/FEXCore/Source/Interface/Core/X86Tables/SecondaryGroupTables.cpp +++ b/FEXCore/Source/Interface/Core/X86Tables/SecondaryGroupTables.cpp @@ -162,7 +162,7 @@ std::array SecondInstGroupOps = [ {OPD(TYPE_GROUP_9, PF_F3, 4), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}}, {OPD(TYPE_GROUP_9, PF_F3, 5), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}}, {OPD(TYPE_GROUP_9, PF_F3, 6), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}}, - {OPD(TYPE_GROUP_9, PF_F3, 7), 1, X86InstInfo{"RDPID", TYPE_INVALID, FLAGS_NONE, 0, nullptr}}, + {OPD(TYPE_GROUP_9, PF_F3, 7), 1, X86InstInfo{"RDPID", TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_MOD_REG_ONLY, 0, nullptr}}, {OPD(TYPE_GROUP_9, PF_66, 0), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}}, {OPD(TYPE_GROUP_9, PF_66, 1), 1, X86InstInfo{"CMPXCHG8B/16B", TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_MOD_MEM_ONLY, 0, nullptr}}, diff --git a/unittests/ASM/Disabled_Tests_Simulator b/unittests/ASM/Disabled_Tests_Simulator index 7320481074..710d0df501 100644 --- a/unittests/ASM/Disabled_Tests_Simulator +++ b/unittests/ASM/Disabled_Tests_Simulator @@ -86,3 +86,6 @@ Test_VEX/vroundss.asm # Simulator doesn't support cycle counter reading Test_TwoByte/0F_31.asm + +# Simulator doesn't support executing a syscall +Test_Secondary/09_F3_07.asm diff --git a/unittests/ASM/Secondary/09_F3_07.asm b/unittests/ASM/Secondary/09_F3_07.asm new file mode 100644 index 0000000000..7ba0c40a44 --- /dev/null +++ b/unittests/ASM/Secondary/09_F3_07.asm @@ -0,0 +1,17 @@ +%ifdef CONFIG +{ + "RegData": { + "RAX": "1" + } +} +%endif + +mov rax, 0 +mov rbx, 0x4142434445464748 +mov rcx, 0x4142434445464748 +rdpid ebx + +cmp rbx, rcx +setne al + +hlt diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json index c911bee932..5539adb7d1 100644 --- a/unittests/InstructionCountCI/SecondaryGroup.json +++ b/unittests/InstructionCountCI/SecondaryGroup.json @@ -921,6 +921,52 @@ "msr nzcv, x20" ] }, + "rdpid eax": { + "ExpectedInstructionCount": 17, + "Comment": "GROUP9 0xF3 0x0F 0xC7 /7", + "ExpectedArm64ASM": [ + "mrs x0, nzcv", + "str w0, [x28, #728]", + "str x8, [x28, #40]", + "mov w0, #0x100", + "str x0, [x28, #1056]", + "sub sp, sp, #0x10 (16)", + "mov w8, #0xa8", + "mov x0, sp", + "add x1, sp, #0x4 (4)", + "svc #0x0", + "ldp w0, w1, [sp]", + "sub sp, sp, #0x10 (16)", + "ldr w8, [x28, #728]", + "msr nzcv, x8", + "ldr x8, [x28, #40]", + "str xzr, [x28, #1056]", + "orr x5, x0, x1, lsl #12" + ] + }, + "rdpid rax": { + "ExpectedInstructionCount": 17, + "Comment": "GROUP9 0xF3 0x0F 0xC7 /7", + "ExpectedArm64ASM": [ + "mrs x0, nzcv", + "str w0, [x28, #728]", + "str x8, [x28, #40]", + "mov w0, #0x100", + "str x0, [x28, #1056]", + "sub sp, sp, #0x10 (16)", + "mov w8, #0xa8", + "mov x0, sp", + "add x1, sp, #0x4 (4)", + "svc #0x0", + "ldp w0, w1, [sp]", + "sub sp, sp, #0x10 (16)", + "ldr w8, [x28, #728]", + "msr nzcv, x8", + "ldr x8, [x28, #40]", + "str xzr, [x28, #1056]", + "orr x5, x0, x1, lsl #12" + ] + }, "psrlw mm0, 0": { "ExpectedInstructionCount": 0, "Type": "MMX",