diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp
index d0d7df6561..f715751b0f 100644
--- a/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp
+++ b/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp
@@ -37,9 +37,10 @@ DEF_OP(CASPair) {
     Bind(&LoopTop);
 
     ldaxp(EmitSize, TMP2, TMP3, MemSrc);
-    cmp(EmitSize, TMP2, Expected.first);
-    ccmp(EmitSize, TMP3, Expected.second, ARMEmitter::StatusFlags::None, ARMEmitter::Condition::CC_EQ);
-    b(ARMEmitter::Condition::CC_NE, &LoopNotExpected);
+    eor(EmitSize, TMP1, TMP2, Expected.first);
+    eor(EmitSize, TMP4, TMP3, Expected.second);
+    orr(EmitSize, TMP1, TMP1, TMP4);
+    cbnz(EmitSize, TMP1, &LoopNotExpected);
     stlxp(EmitSize, TMP2, Desired.first, Desired.second, MemSrc);
     cbnz(EmitSize, TMP2, &LoopTop);
     mov(EmitSize, Dst.first, Expected.first);
diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json
index 16bacee115..f3e8f640fe 100644
--- a/FEXCore/Source/Interface/IR/IR.json
+++ b/FEXCore/Source/Interface/IR/IR.json
@@ -642,7 +642,6 @@
                 ],
         "HasDest": true,
         "DestSize": "Size",
-        "ImplicitFlagClobber": true,
         "NumElements": "2",
         "EmitValidation": [
           "Size == FEXCore::IR::OpSize::i64Bit || Size == FEXCore::IR::OpSize::i128Bit"