Chisel 6 migration

[kayvan61]

We rely on an out of date chisel. Moving to the new chisel requires rewriting some of the testing code, and checking which if any interfaces changed

[kayvan61]

Chisel 6 is currently bugged, initing memories doesn't work. See chipsalliance/chisel#4340

Regardless, forking from tywaves to maintain our only simulator which uses 'final' instead of 'initial' for the simulation body still results in the core halting unexpectedly so we need to track that down. Won't fix until the mainline chiselSim has the ability to dump VCDs, and init RAMs.