From 864fcfc78733297055fea032dfb5f7c8d594dfd8 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 6 Oct 2024 11:47:30 -0700 Subject: [PATCH] [RISCV] Combine RVBUnary and RVKUnary into classes that are more similar to ALU(W)_r(r/i). NFC (#111279) Create Unary_r and UnaryW_r that use OP_IMM and OP_IMM_32. --- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 10 ++++++ llvm/lib/Target/RISCV/RISCVInstrInfoZb.td | 40 ++++++++++------------- llvm/lib/Target/RISCV/RISCVInstrInfoZk.td | 26 +++++++-------- 3 files changed, 38 insertions(+), 38 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 01ecd06e288bca..0f16b2a9739dd3 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -606,6 +606,16 @@ class Priv_rr funct7> let rd = 0; } +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class Unary_r imm12, bits<3> funct3, string opcodestr> + : RVInstIUnary; + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class UnaryW_r imm12, bits<3> funct3, string opcodestr> + : RVInstIUnary; + //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td index 3dcab2def0c0ef..39eff7dcead6e3 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td @@ -232,12 +232,6 @@ class RVBUnaryR funct7, bits<3> funct3, let rs2 = 0; } -let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in -class RVBUnary imm12, bits<3> funct3, - RISCVOpcode opcode, string opcodestr> - : RVInstIUnary; - let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class RVBShift_ri imm11_7, bits<3> funct3, RISCVOpcode opcode, string opcodestr> @@ -333,27 +327,27 @@ def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">, } // Predicates = [HasStdExtZbkx] let Predicates = [HasStdExtZbb], IsSignExtendingOpW = 1 in { -def CLZ : RVBUnary<0b011000000000, 0b001, OPC_OP_IMM, "clz">, +def CLZ : Unary_r<0b011000000000, 0b001, "clz">, Sched<[WriteCLZ, ReadCLZ]>; -def CTZ : RVBUnary<0b011000000001, 0b001, OPC_OP_IMM, "ctz">, +def CTZ : Unary_r<0b011000000001, 0b001, "ctz">, Sched<[WriteCTZ, ReadCTZ]>; -def CPOP : RVBUnary<0b011000000010, 0b001, OPC_OP_IMM, "cpop">, +def CPOP : Unary_r<0b011000000010, 0b001, "cpop">, Sched<[WriteCPOP, ReadCPOP]>; } // Predicates = [HasStdExtZbb] let Predicates = [HasStdExtZbb, IsRV64], IsSignExtendingOpW = 1 in { -def CLZW : RVBUnary<0b011000000000, 0b001, OPC_OP_IMM_32, "clzw">, - Sched<[WriteCLZ32, ReadCLZ32]>; -def CTZW : RVBUnary<0b011000000001, 0b001, OPC_OP_IMM_32, "ctzw">, - Sched<[WriteCTZ32, ReadCTZ32]>; -def CPOPW : RVBUnary<0b011000000010, 0b001, OPC_OP_IMM_32, "cpopw">, - Sched<[WriteCPOP32, ReadCPOP32]>; +def CLZW : UnaryW_r<0b011000000000, 0b001, "clzw">, + Sched<[WriteCLZ32, ReadCLZ32]>; +def CTZW : UnaryW_r<0b011000000001, 0b001, "ctzw">, + Sched<[WriteCTZ32, ReadCTZ32]>; +def CPOPW : UnaryW_r<0b011000000010, 0b001, "cpopw">, + Sched<[WriteCPOP32, ReadCPOP32]>; } // Predicates = [HasStdExtZbb, IsRV64] let Predicates = [HasStdExtZbb], IsSignExtendingOpW = 1 in { -def SEXT_B : RVBUnary<0b011000000100, 0b001, OPC_OP_IMM, "sext.b">, +def SEXT_B : Unary_r<0b011000000100, 0b001, "sext.b">, Sched<[WriteIALU, ReadIALU]>; -def SEXT_H : RVBUnary<0b011000000101, 0b001, OPC_OP_IMM, "sext.h">, +def SEXT_H : Unary_r<0b011000000101, 0b001, "sext.h">, Sched<[WriteIALU, ReadIALU]>; } // Predicates = [HasStdExtZbb] @@ -403,28 +397,28 @@ def ZEXT_H_RV64 : RVBUnaryR<0b0000100, 0b100, OPC_OP_32, "zext.h">, } // Predicates = [HasStdExtZbb, IsRV64] let Predicates = [HasStdExtZbbOrZbkb, IsRV32] in { -def REV8_RV32 : RVBUnary<0b011010011000, 0b101, OPC_OP_IMM, "rev8">, +def REV8_RV32 : Unary_r<0b011010011000, 0b101, "rev8">, Sched<[WriteREV8, ReadREV8]>; } // Predicates = [HasStdExtZbbOrZbkb, IsRV32] let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in { -def REV8_RV64 : RVBUnary<0b011010111000, 0b101, OPC_OP_IMM, "rev8">, +def REV8_RV64 : Unary_r<0b011010111000, 0b101, "rev8">, Sched<[WriteREV8, ReadREV8]>; } // Predicates = [HasStdExtZbbOrZbkb, IsRV64] let Predicates = [HasStdExtZbb] in { -def ORC_B : RVBUnary<0b001010000111, 0b101, OPC_OP_IMM, "orc.b">, +def ORC_B : Unary_r<0b001010000111, 0b101, "orc.b">, Sched<[WriteORCB, ReadORCB]>; } // Predicates = [HasStdExtZbb] let Predicates = [HasStdExtZbkb] in -def BREV8 : RVBUnary<0b011010000111, 0b101, OPC_OP_IMM, "brev8">, +def BREV8 : Unary_r<0b011010000111, 0b101, "brev8">, Sched<[WriteBREV8, ReadBREV8]>; let Predicates = [HasStdExtZbkb, IsRV32] in { -def ZIP_RV32 : RVBUnary<0b000010001111, 0b001, OPC_OP_IMM, "zip">, +def ZIP_RV32 : Unary_r<0b000010001111, 0b001, "zip">, Sched<[WriteZIP, ReadZIP]>; -def UNZIP_RV32 : RVBUnary<0b000010001111, 0b101, OPC_OP_IMM, "unzip">, +def UNZIP_RV32 : Unary_r<0b000010001111, 0b101, "unzip">, Sched<[WriteZIP, ReadZIP]>; } // Predicates = [HasStdExtZbkb, IsRV32] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td index 3ec63b1b6adb33..34f8b006b9c047 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZk.td @@ -52,10 +52,6 @@ def byteselect : RISCVOp, TImmLeaf(Imm);}]> { //===----------------------------------------------------------------------===// // Instruction class templates //===----------------------------------------------------------------------===// -let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in -class RVKUnary imm12, bits<3> funct3, string opcodestr> - : RVInstIUnary; let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class RVKByteSelect funct5, string opcodestr> @@ -88,7 +84,7 @@ let Predicates = [HasStdExtZknd, IsRV64] in { def AES64DS : ALU_rr<0b0011101, 0b000, "aes64ds">; def AES64DSM : ALU_rr<0b0011111, 0b000, "aes64dsm">; -def AES64IM : RVKUnary<0b001100000000, 0b001, "aes64im">; +def AES64IM : Unary_r<0b001100000000, 0b001, "aes64im">; } // Predicates = [HasStdExtZknd, IsRV64] let Predicates = [HasStdExtZkndOrZkne, IsRV64] in { @@ -108,10 +104,10 @@ def AES64ESM : ALU_rr<0b0011011, 0b000, "aes64esm">; } // Predicates = [HasStdExtZkne, IsRV64] let Predicates = [HasStdExtZknh], IsSignExtendingOpW = 1 in { -def SHA256SIG0 : RVKUnary<0b000100000010, 0b001, "sha256sig0">; -def SHA256SIG1 : RVKUnary<0b000100000011, 0b001, "sha256sig1">; -def SHA256SUM0 : RVKUnary<0b000100000000, 0b001, "sha256sum0">; -def SHA256SUM1 : RVKUnary<0b000100000001, 0b001, "sha256sum1">; +def SHA256SIG0 : Unary_r<0b000100000010, 0b001, "sha256sig0">; +def SHA256SIG1 : Unary_r<0b000100000011, 0b001, "sha256sig1">; +def SHA256SUM0 : Unary_r<0b000100000000, 0b001, "sha256sum0">; +def SHA256SUM1 : Unary_r<0b000100000001, 0b001, "sha256sum1">; } // Predicates = [HasStdExtZknh] let Predicates = [HasStdExtZknh, IsRV32] in { @@ -124,10 +120,10 @@ def SHA512SUM1R : ALU_rr<0b0101001, 0b000, "sha512sum1r">; } // [HasStdExtZknh, IsRV32] let Predicates = [HasStdExtZknh, IsRV64] in { -def SHA512SIG0 : RVKUnary<0b000100000110, 0b001, "sha512sig0">; -def SHA512SIG1 : RVKUnary<0b000100000111, 0b001, "sha512sig1">; -def SHA512SUM0 : RVKUnary<0b000100000100, 0b001, "sha512sum0">; -def SHA512SUM1 : RVKUnary<0b000100000101, 0b001, "sha512sum1">; +def SHA512SIG0 : Unary_r<0b000100000110, 0b001, "sha512sig0">; +def SHA512SIG1 : Unary_r<0b000100000111, 0b001, "sha512sig1">; +def SHA512SUM0 : Unary_r<0b000100000100, 0b001, "sha512sum0">; +def SHA512SUM1 : Unary_r<0b000100000101, 0b001, "sha512sum1">; } // Predicates = [HasStdExtZknh, IsRV64] let Predicates = [HasStdExtZksed], IsSignExtendingOpW = 1 in { @@ -136,8 +132,8 @@ def SM4KS : RVKByteSelect<0b11010, "sm4ks">; } // Predicates = [HasStdExtZksed] let Predicates = [HasStdExtZksh], IsSignExtendingOpW = 1 in { -def SM3P0 : RVKUnary<0b000100001000, 0b001, "sm3p0">; -def SM3P1 : RVKUnary<0b000100001001, 0b001, "sm3p1">; +def SM3P0 : Unary_r<0b000100001000, 0b001, "sm3p0">; +def SM3P1 : Unary_r<0b000100001001, 0b001, "sm3p1">; } // Predicates = [HasStdExtZksh] //===----------------------------------------------------------------------===//