From 64148944c56f50a50383c79d5b6d074d8608f2a4 Mon Sep 17 00:00:00 2001 From: SpencerAbson Date: Mon, 28 Oct 2024 10:41:07 +0000 Subject: [PATCH] [AArch64] Add assembly/disassembly for zeroing SVE2 integer instructions (#113473) This patch adds assembly/disassembly for the following SVE2.2 instructions - SQABS (zeroing) - SQNEG (zeroing) - URECPE (zeroing) - USQRTE (zeroing) - Refactor the existing merging forms to remove the now redundant bit 17 argument. - In accordance with: https://developer.arm.com/documentation/ddi0602/latest/ --- .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 14 +++-- llvm/lib/Target/AArch64/SVEInstrFormats.td | 52 ++++++++++++++----- llvm/test/MC/AArch64/SVE2/sqabs-diagnostics.s | 2 +- llvm/test/MC/AArch64/SVE2/sqneg-diagnostics.s | 2 +- .../test/MC/AArch64/SVE2/urecpe-diagnostics.s | 2 +- .../MC/AArch64/SVE2/ursqrte-diagnostics.s | 2 +- .../MC/AArch64/SVE2p2/sqabs_z-diagnostics.s | 37 +++++++++++++ llvm/test/MC/AArch64/SVE2p2/sqabs_z.s | 39 ++++++++++++++ .../MC/AArch64/SVE2p2/sqneg_z-diagnostics.s | 37 +++++++++++++ llvm/test/MC/AArch64/SVE2p2/sqneg_z.s | 39 ++++++++++++++ .../MC/AArch64/SVE2p2/urecpe_z-diagnostics.s | 47 +++++++++++++++++ llvm/test/MC/AArch64/SVE2p2/urecpe_z.s | 33 ++++++++++++ .../MC/AArch64/SVE2p2/ursqrte_z-diagnostics.s | 47 +++++++++++++++++ llvm/test/MC/AArch64/SVE2p2/ursqrte_z.s | 33 ++++++++++++ 14 files changed, 366 insertions(+), 20 deletions(-) create mode 100644 llvm/test/MC/AArch64/SVE2p2/sqabs_z-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE2p2/sqabs_z.s create mode 100644 llvm/test/MC/AArch64/SVE2p2/sqneg_z-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE2p2/sqneg_z.s create mode 100644 llvm/test/MC/AArch64/SVE2p2/urecpe_z-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE2p2/urecpe_z.s create mode 100644 llvm/test/MC/AArch64/SVE2p2/ursqrte_z-diagnostics.s create mode 100644 llvm/test/MC/AArch64/SVE2p2/ursqrte_z.s diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index bf6e25438633c7..dc96b249c4e40c 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -3586,10 +3586,10 @@ let Predicates = [HasSVE2orSME] in { defm UMINP_ZPmZ : sve2_int_arith_pred<0b101111, "uminp", int_aarch64_sve_uminp>; // SVE2 integer unary operations (predicated) - defm URECPE_ZPmZ : sve2_int_un_pred_arit_s<0b000, "urecpe", int_aarch64_sve_urecpe>; - defm URSQRTE_ZPmZ : sve2_int_un_pred_arit_s<0b001, "ursqrte", int_aarch64_sve_ursqrte>; - defm SQABS_ZPmZ : sve2_int_un_pred_arit<0b100, "sqabs", int_aarch64_sve_sqabs>; - defm SQNEG_ZPmZ : sve2_int_un_pred_arit<0b101, "sqneg", int_aarch64_sve_sqneg>; + defm URECPE_ZPmZ : sve2_int_un_pred_arit_s<0b00, "urecpe", int_aarch64_sve_urecpe>; + defm URSQRTE_ZPmZ : sve2_int_un_pred_arit_s<0b01, "ursqrte", int_aarch64_sve_ursqrte>; + defm SQABS_ZPmZ : sve2_int_un_pred_arit< 0b10, "sqabs", int_aarch64_sve_sqabs>; + defm SQNEG_ZPmZ : sve2_int_un_pred_arit< 0b11, "sqneg", int_aarch64_sve_sqneg>; // SVE2 saturating add/subtract defm SQADD_ZPmZ : sve2_int_arith_pred<0b110000, "sqadd", int_aarch64_sve_sqadd>; @@ -4236,6 +4236,12 @@ let Predicates = [HasSVE2p2orSME2p2] in { // Signed integer base 2 logarithm of fp value, zeroing predicate defm FLOGB_ZPzZ : sve_fp_z2op_p_zd_d_flogb<"flogb">; + // SVE2 integer unary operations, zeroing predicate + def URECPE_ZPzZ : sve2_int_un_pred_arit_z<0b10, 0b00, "urecpe", ZPR32>; + def URSQRTE_ZPzZ : sve2_int_un_pred_arit_z<0b10, 0b01, "ursqrte", ZPR32>; + defm SQABS_ZPzZ : sve2_int_un_pred_arit_z<0b10, "sqabs">; + defm SQNEG_ZPzZ : sve2_int_un_pred_arit_z<0b11, "sqneg">; + // Floating point round to integral fp value in integer size range // Merging defm FRINT32Z_ZPmZ : sve_fp_2op_p_zd_frint<0b00, "frint32z">; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index af5c96eb5c8c56..02ee0fe9244572 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -3964,7 +3964,7 @@ multiclass sve2_int_sadd_long_accum_pairwise(NAME # _D)>; } -class sve2_int_un_pred_arit sz, bit Q, bits<2> opc, +class sve2_int_un_pred_arit sz, bits<2> opc, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn), asm, "\t$Zd, $Pg/m, $Zn", @@ -3976,23 +3976,44 @@ class sve2_int_un_pred_arit sz, bit Q, bits<2> opc, let Inst{31-24} = 0b01000100; let Inst{23-22} = sz; let Inst{21-20} = 0b00; - let Inst{19} = Q; - let Inst{18} = 0b0; - let Inst{17-16} = opc; + let Inst{19} = opc{1}; + let Inst{18-17} = 0b00; + let Inst{16} = opc{0}; let Inst{15-13} = 0b101; let Inst{12-10} = Pg; let Inst{9-5} = Zn; let Inst{4-0} = Zd; - let Constraints = "$Zd = $_Zd"; let DestructiveInstType = DestructiveUnaryPassthru; let ElementSize = zprty.ElementSize; let hasSideEffects = 0; } -multiclass sve2_int_un_pred_arit_s opc, string asm, +class sve2_int_un_pred_arit_z sz, bits<2> opc, + string asm, ZPRRegOp zprty> +: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn), + asm, "\t$Zd, $Pg/z, $Zn", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Zd; + bits<5> Zn; + let Inst{31-24} = 0b01000100; + let Inst{23-22} = sz; + let Inst{21-20} = 0b00; + let Inst{19} = opc{1}; + let Inst{18-17} = 0b01; + let Inst{16} = opc{0}; + let Inst{15-13} = 0b101; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; + let hasSideEffects = 0; +} + +multiclass sve2_int_un_pred_arit_s opc, string asm, SDPatternOperator op> { - def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>, + def _S : sve2_int_un_pred_arit<0b10, opc, asm, ZPR32>, SVEPseudo2Instr; def : SVE_3_Op_Pat(NAME # _S)>; @@ -4002,14 +4023,14 @@ multiclass sve2_int_un_pred_arit_s opc, string asm, defm : SVE_3_Op_Undef_Pat(NAME # _S_UNDEF)>; } -multiclass sve2_int_un_pred_arit opc, string asm, SDPatternOperator op> { - def _B : sve2_int_un_pred_arit<0b00, opc{2}, opc{1-0}, asm, ZPR8>, +multiclass sve2_int_un_pred_arit opc, string asm, SDPatternOperator op> { + def _B : sve2_int_un_pred_arit<0b00, opc, asm, ZPR8>, SVEPseudo2Instr; - def _H : sve2_int_un_pred_arit<0b01, opc{2}, opc{1-0}, asm, ZPR16>, + def _H : sve2_int_un_pred_arit<0b01, opc, asm, ZPR16>, SVEPseudo2Instr; - def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>, + def _S : sve2_int_un_pred_arit<0b10, opc, asm, ZPR32>, SVEPseudo2Instr; - def _D : sve2_int_un_pred_arit<0b11, opc{2}, opc{1-0}, asm, ZPR64>, + def _D : sve2_int_un_pred_arit<0b11, opc, asm, ZPR64>, SVEPseudo2Instr; def : SVE_3_Op_Pat(NAME # _B)>; @@ -4028,6 +4049,13 @@ multiclass sve2_int_un_pred_arit opc, string asm, SDPatternOperator op> defm : SVE_3_Op_Undef_Pat(NAME # _D_UNDEF)>; } +multiclass sve2_int_un_pred_arit_z opc, string asm> { + def _B : sve2_int_un_pred_arit_z<0b00, opc, asm, ZPR8>; + def _H : sve2_int_un_pred_arit_z<0b01, opc, asm, ZPR16>; + def _S : sve2_int_un_pred_arit_z<0b10, opc, asm, ZPR32>; + def _D : sve2_int_un_pred_arit_z<0b11, opc, asm, ZPR64>; +} + //===----------------------------------------------------------------------===// // SVE2 Widening Integer Arithmetic Group //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/AArch64/SVE2/sqabs-diagnostics.s b/llvm/test/MC/AArch64/SVE2/sqabs-diagnostics.s index 8b3a136a7d7429..7dd268dd7cddd1 100644 --- a/llvm/test/MC/AArch64/SVE2/sqabs-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2/sqabs-diagnostics.s @@ -4,7 +4,7 @@ // Invalid predicate sqabs z0.s, p0/z, z1.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2 // CHECK-NEXT: sqabs z0.s, p0/z, z1.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/sqneg-diagnostics.s b/llvm/test/MC/AArch64/SVE2/sqneg-diagnostics.s index 7b0f5722b94a3f..372adad0427c09 100644 --- a/llvm/test/MC/AArch64/SVE2/sqneg-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2/sqneg-diagnostics.s @@ -4,7 +4,7 @@ // Invalid predicate sqneg z0.s, p0/z, z1.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2 // CHECK-NEXT: sqneg z0.s, p0/z, z1.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/urecpe-diagnostics.s b/llvm/test/MC/AArch64/SVE2/urecpe-diagnostics.s index f04538494cd6f0..73bb6cecffa5a4 100644 --- a/llvm/test/MC/AArch64/SVE2/urecpe-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2/urecpe-diagnostics.s @@ -4,7 +4,7 @@ // Invalid predicate urecpe z0.s, p0/z, z1.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2 // CHECK-NEXT: urecpe z0.s, p0/z, z1.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/ursqrte-diagnostics.s b/llvm/test/MC/AArch64/SVE2/ursqrte-diagnostics.s index 2190ff1ebd82ba..0c6746a4a7c1fe 100644 --- a/llvm/test/MC/AArch64/SVE2/ursqrte-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2/ursqrte-diagnostics.s @@ -4,7 +4,7 @@ // Invalid predicate ursqrte z0.s, p0/z, z1.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2 // CHECK-NEXT: ursqrte z0.s, p0/z, z1.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p2/sqabs_z-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/sqabs_z-diagnostics.s new file mode 100644 index 00000000000000..8c00a74c69c8c6 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/sqabs_z-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqabs z31.b, p7/z, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqabs z31.b, p7/z, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqabs z31.d, p7/z, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqabs z31.d, p7/z, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid predicate + +sqabs z31.b, p8/z, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: sqabs z31.b, p8/z, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/z, z7.h +sqabs z0.h, p0/z, z3.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqabs z0.h, p0/z, z3.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +sqabs z0.h, p0/z, z3.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqabs z0.h, p0/z, z3.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2p2/sqabs_z.s b/llvm/test/MC/AArch64/SVE2p2/sqabs_z.s new file mode 100644 index 00000000000000..c583423fac6eba --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/sqabs_z.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +sqabs z0.b, p0/z, z0.b // 01000100-00001010-10100000-00000000 +// CHECK-INST: sqabs z0.b, p0/z, z0.b +// CHECK-ENCODING: [0x00,0xa0,0x0a,0x44] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 440aa000 + +sqabs z21.h, p5/z, z10.h // 01000100-01001010-10110101-01010101 +// CHECK-INST: sqabs z21.h, p5/z, z10.h +// CHECK-ENCODING: [0x55,0xb5,0x4a,0x44] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 444ab555 + +sqabs z23.s, p3/z, z13.s // 01000100-10001010-10101101-10110111 +// CHECK-INST: sqabs z23.s, p3/z, z13.s +// CHECK-ENCODING: [0xb7,0xad,0x8a,0x44] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 448aadb7 + +sqabs z31.d, p7/z, z31.d // 01000100-11001010-10111111-11111111 +// CHECK-INST: sqabs z31.d, p7/z, z31.d +// CHECK-ENCODING: [0xff,0xbf,0xca,0x44] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 44cabfff \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2p2/sqneg_z-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/sqneg_z-diagnostics.s new file mode 100644 index 00000000000000..576633c0ab1b64 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/sqneg_z-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqneg z31.b, p7/z, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqneg z31.b, p7/z, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqneg z31.d, p7/z, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqneg z31.d, p7/z, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid predicate + +sqneg z31.b, p8/z, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: sqneg z31.b, p8/z, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.h, p0/z, z7.h +sqneg z0.h, p0/z, z3.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqneg z0.h, p0/z, z3.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +sqneg z0.h, p0/z, z3.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqneg z0.h, p0/z, z3.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2p2/sqneg_z.s b/llvm/test/MC/AArch64/SVE2p2/sqneg_z.s new file mode 100644 index 00000000000000..287211fd3ff5dd --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/sqneg_z.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +sqneg z0.b, p0/z, z0.b // 01000100-00001011-10100000-00000000 +// CHECK-INST: sqneg z0.b, p0/z, z0.b +// CHECK-ENCODING: [0x00,0xa0,0x0b,0x44] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 440ba000 + +sqneg z23.h, p3/z, z13.h // 01000100-01001011-10101101-10110111 +// CHECK-INST: sqneg z23.h, p3/z, z13.h +// CHECK-ENCODING: [0xb7,0xad,0x4b,0x44] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 444badb7 + +sqneg z21.s, p5/z, z10.s // 01000100-10001011-10110101-01010101 +// CHECK-INST: sqneg z21.s, p5/z, z10.s +// CHECK-ENCODING: [0x55,0xb5,0x8b,0x44] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 448bb555 + +sqneg z31.d, p7/z, z31.d // 01000100-11001011-10111111-11111111 +// CHECK-INST: sqneg z31.d, p7/z, z31.d +// CHECK-ENCODING: [0xff,0xbf,0xcb,0x44] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 44cbbfff \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2p2/urecpe_z-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/urecpe_z-diagnostics.s new file mode 100644 index 00000000000000..9da2a7e096f3af --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/urecpe_z-diagnostics.s @@ -0,0 +1,47 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid element width + +urecpe z31.b, p7/z, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urecpe z31.b, p7/z, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urecpe z31.h, p7/z, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urecpe z31.h, p7/z, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urecpe z31.s, p7/z, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urecpe z31.s, p7/z, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urecpe z31.d, p7/z, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urecpe z31.d, p7/z, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid predicate + +urecpe z0.s, p8/z, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: urecpe z0.s, p8/z, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +urecpe z0.s, p0/z, z3.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: urecpe z0.s, p0/z, z3.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +urecpe z0.s, p0/z, z3.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: urecpe z0.s, p0/z, z3.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2p2/urecpe_z.s b/llvm/test/MC/AArch64/SVE2p2/urecpe_z.s new file mode 100644 index 00000000000000..6b3ec79c988690 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/urecpe_z.s @@ -0,0 +1,33 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +urecpe z0.s, p0/z, z0.s // 01000100-10000010-10100000-00000000 +// CHECK-INST: urecpe z0.s, p0/z, z0.s +// CHECK-ENCODING: [0x00,0xa0,0x82,0x44] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 4482a000 + +urecpe z23.s, p3/z, z13.s // 01000100-10000010-10101101-10110111 +// CHECK-INST: urecpe z23.s, p3/z, z13.s +// CHECK-ENCODING: [0xb7,0xad,0x82,0x44] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 4482adb7 + +urecpe z31.s, p7/z, z31.s // 01000100-10000010-10111111-11111111 +// CHECK-INST: urecpe z31.s, p7/z, z31.s +// CHECK-ENCODING: [0xff,0xbf,0x82,0x44] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 4482bfff \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2p2/ursqrte_z-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/ursqrte_z-diagnostics.s new file mode 100644 index 00000000000000..1b6cf8d78e655e --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/ursqrte_z-diagnostics.s @@ -0,0 +1,47 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid element width + +ursqrte z31.b, p7/z, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ursqrte z31.b, p7/z, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ursqrte z31.h, p7/z, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ursqrte z31.h, p7/z, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ursqrte z31.s, p7/z, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ursqrte z31.s, p7/z, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ursqrte z31.d, p7/z, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ursqrte z31.d, p7/z, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid predicate + +ursqrte z0.s, p8/z, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: ursqrte z0.s, p8/z, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +ursqrte z0.s, p0/z, z3.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ursqrte z0.s, p0/z, z3.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ursqrte z0.s, p0/z, z3.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ursqrte z0.s, p0/z, z3.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2p2/ursqrte_z.s b/llvm/test/MC/AArch64/SVE2p2/ursqrte_z.s new file mode 100644 index 00000000000000..097d82bebd430b --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/ursqrte_z.s @@ -0,0 +1,33 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +ursqrte z0.s, p0/z, z0.s // 01000100-10000011-10100000-00000000 +// CHECK-INST: ursqrte z0.s, p0/z, z0.s +// CHECK-ENCODING: [0x00,0xa0,0x83,0x44] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 4483a000 + +ursqrte z21.s, p5/z, z10.s // 01000100-10000011-10110101-01010101 +// CHECK-INST: ursqrte z21.s, p5/z, z10.s +// CHECK-ENCODING: [0x55,0xb5,0x83,0x44] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 4483b555 + +ursqrte z31.s, p7/z, z31.s // 01000100-10000011-10111111-11111111 +// CHECK-INST: ursqrte z31.s, p7/z, z31.s +// CHECK-ENCODING: [0xff,0xbf,0x83,0x44] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 4483bfff \ No newline at end of file