diff --git a/Firmware/.settings/language.settings.xml b/Firmware/.settings/language.settings.xml index 6499965..d511d5b 100644 --- a/Firmware/.settings/language.settings.xml +++ b/Firmware/.settings/language.settings.xml @@ -5,7 +5,7 @@ - + @@ -16,7 +16,7 @@ - + diff --git a/Firmware/Core/Src/main.c b/Firmware/Core/Src/main.c index bd2cf12..c7b36f5 100644 --- a/Firmware/Core/Src/main.c +++ b/Firmware/Core/Src/main.c @@ -60,216 +60,157 @@ static void MX_USART2_UART_Init(void); static void MX_CRC_Init(void); /* USER CODE BEGIN PFP */ +void SetStandbyXOSC(); +void SetPacketTypeLora(); +void SetPacketTypeFSK(); +uint32_t ComputeRfFreq(double frequencyMhz); +void SetRfFreq(uint32_t rfFreq); +void SetPaLowPower(); +void SetPa22dB(); +void SetTxPower(int8_t powerdBm); +void SetContinuousWave(); +void SetTxInfinitePreamble(); +void SetTx(uint32_t timeout); +void SetRx(uint32_t timeout); +void SetModulationParamsLora(const uint8_t params[4]); +void SetModulationParamsFSK(uint32_t bitrate, uint8_t pulseshape, uint8_t bandwidth, uint32_t freq_dev); +void SetPacketParamsLora(uint16_t preamble_length, bool header_fixed, uint8_t payload_length, bool crc_enabled, bool invert_iq); +void FSKBeep(int8_t powerdBm, uint32_t toneHz, uint32_t lengthMs); +void CWBeep(int8_t powerdBm, uint32_t lengthMs); + /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ -void SetStandbyXOSC() { - uint8_t txbuf[2] = {0x80, 0x01}; - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); -} - -void SetPacketTypeLora() { - uint8_t txbuf[2] = {0x8A, 0x01}; - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); -} - -void SetPacketTypeFSK() { - uint8_t txbuf[2] = {0x8A, 0x00}; - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); -} - -uint32_t ComputeRfFreq(double frequencyMhz) { - return (uint32_t)(frequencyMhz * 1048576L); //2^25/(32e6) -} - -void SetRfFreq(uint32_t rfFreq) { - uint8_t txbuf[5] = {0x86, (rfFreq & 0xFF000000) >> 24, (rfFreq & 0x00FF0000) >> 16, (rfFreq & 0x0000FF00) >> 8, rfFreq & 0x000000FF}; - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); -} - -void SetPaLowPower() { - // set Pa to 14 dB. - uint8_t txbuf[5] = {0x95, 0x02, 0x02, 0x00, 0x01}; - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); -} - -void SetPa22dB() { - // set Pa to the highest 22 dBm - uint8_t txbuf[5] = {0x95, 0x04, 0x07, 0x00, 0x01}; - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); -} - -void SetTxPower(int8_t powerdBm) { - // Between -9 and 22 - uint8_t txbuf[3] = {0x8E, (uint8_t) powerdBm, 0x02}; - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); -} - -void SetContinuousWave() { - uint8_t txbuf[1] = {0xD1}; - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf, 0); -} - -void SetTxInfinitePreamble() { - uint8_t txbuf[1] = {0xD2}; - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf, 0); -} - -void SetTx(uint32_t timeout) { - // Timeout * 15.625 µs - uint8_t txbuf[4] = {0x83, (timeout & 0x00FF0000) >> 16, (timeout & 0x0000FF00) >> 8, timeout & 0x000000FF}; - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); -} - -void SetRx(uint32_t timeout) { - // Timeout * 15.625 µs - // 0x000000 No timeout. Rx Single mode - // 0xFFFFFF Rx Continuous mode. The device remains in RX mode until the host sends a command to change the operation mode - uint8_t txbuf[4] = {0x82, (timeout & 0x00FF0000) >> 16, (timeout & 0x0000FF00) >> 8, timeout & 0x000000FF}; - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); -} - -void SetModulationParamsLora(const uint8_t params[4]) { - uint8_t txbuf[5] = {0x8B, params[0], params[1], params[2], params[3]}; - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); -} - -void SetModulationParamsFSK(uint32_t bitrate, uint8_t pulseshape, uint8_t bandwidth, uint32_t freq_dev) { - uint32_t BR = 32 * 32e6 / bitrate; - uint32_t fdev = (uint32_t) (freq_dev * 1.048576L); // 2^25/32e6 = 1.048576 - uint8_t txbuf[9] = {0x8B, (BR & 0x00FF0000) >> 16, (BR & 0x0000FF00) >> 8, BR & 0x000000FF, pulseshape, bandwidth, (fdev & 0x00FF0000) >> 16, (fdev & 0x0000FF00) >> 8, fdev & 0x000000FF}; - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); -} - -void SetPacketParamsLora(uint16_t preamble_length, bool header_fixed, uint8_t payload_length, bool crc_enabled, bool invert_iq) { - uint8_t txbuf[7] = {0x8C, (uint8_t)((preamble_length >> 8) & 0xFF), (uint8_t)(preamble_length & 0xFF), - (uint8_t) header_fixed, payload_length, (uint8_t) crc_enabled, (uint8_t) invert_iq}; - - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); -} - +// standard frequencies. Note: zero indexed. +const double LPD433[69] = { + 433.075, 433.100, 433.125, 433.150, 433.175, 433.200, 433.225, 433.250, 433.275, 433.300, // 1-10 + 433.325, 433.350, 433.375, 433.400, 433.425, 433.450, 433.475, 433.500, 433.525, 433.550, // 11-20 + 433.575, 433.600, 433.625, 433.650, 433.675, 433.700, 433.725, 433.750, 433.775, 433.800, // 21-30 + 433.825, 433.850, 433.875, 433.900, 433.925, 433.950, 433.975, 434.000, 434.025, 434.050, // 31-40 + 434.075, 434.100, 434.125, 434.150, 434.175, 434.200, 434.225, 434.250, 434.275, 434.300, // 41-50 + 434.325, 434.350, 434.375, 434.400, 434.425, 434.450, 434.475, 434.500, 434.525, 434.550, // 51-60 + 434.575, 434.600, 434.625, 434.650, 434.675, 434.700, 434.725, 434.750, 434.775 // 61-69 +}; -void FSKBeep(int8_t powerdBm, uint32_t toneHz, uint32_t lengthMs) { - // assume in standbyXOSC already. - HAL_Delay(1); - SetTxPower(powerdBm); - SetModulationParamsFSK(toneHz*2, 0x09, 0x1E, 2500); - HAL_Delay(5); - SetTxInfinitePreamble(); - HAL_Delay(lengthMs); - SetStandbyXOSC(); - HAL_Delay(5); -} +const double PMR446[16] = { + 446.00625, 446.01875, 446.03125, 446.04375, 446.05625, // 1-5 + 446.06875, 446.08125, 446.09375, 446.10625, 446.11875, // 6-10 + 446.13125, 446.14375, 446.15625, 446.16875, 446.18125, // 11-15 + 446.19375 // 16 +}; -void CWBeep(int8_t powerdBm, uint32_t lengthMs) { - HAL_Delay(1); - SetTxPower(powerdBm); - HAL_Delay(5); - SetContinuousWave(); - HAL_Delay(lengthMs); - SetStandbyXOSC(); - HAL_Delay(5); -} +const double FRS[22] = { + 462.5625, 462.5875, 462.6125, 462.6375, 462.6625, 462.6875, 462.7125, 467.5625, 467.5875, 467.6125, // 1-10 + 467.6375, 467.6625, 467.6875, 467.7125, 462.5500, 462.5750, 462.6000, 462.6250, 462.6500, 462.6750, // 11-20 + 462.7000, 462.7250 // 21-22 +}; // letter to morse based on ASCII characters. // right-terminated by a "1". 1 is dah, 0 is dit. const uint8_t morse_chars[] = { - 0b11111111, // Special code for SPACE - 0b10000000, // N/A - 0b10000000, // N/A - 0b10000000, // N/A - 0b10000000, // N/A - 0b10000000, // N/A - 0b10000000, // N/A - 0b10000000, // N/A - 0b10000000, // N/A - 0b10000000, // N/A - 0b10000000, // N/A - 0b10000000, // N/A - 0b10000000, // N/A - 0b11100000, // Minus sign (indicated by "M") - 0b10000000, // N/A - 0b10010100, // "/" Slash - 0b11111100, // "0" - 0b01111100, // "1" - 0b00111100, // "2" - 0b00011100, // "3" - 0b00001100, // "4" - 0b00000100, // "5" - 0b10000100, // "6" - 0b11000100, // "7" - 0b11100100, // "8" - 0b11110100, // "9" - 0b10000000, // N/A - 0b10000000, // N/A - 0b10000000, // N/A - 0b10001100, // "=" BT prosign/Equal sign - 0b10000000, // N/A - 0b00110010, // "?" Question mark - 0b10000000, // N/A - 0b01100000, // "A" - 0b10001000, // "B" - 0b10101000, // "C" - 0b10010000, // "D" - 0b01000000, // "E" - 0b00101000, // "F" - 0b11010000, // "G" - 0b00001000, // "H" - 0b00100000, // "I" - 0b01111000, // "J" - 0b10110000, // "K" - 0b01001000, // "L" - 0b11100000, // "M" - 0b10100000, // "N" - 0b11110000, // "O" - 0b01101000, // "P" - 0b11011000, // "Q" - 0b01010000, // "R" - 0b00010000, // "S" - 0b11000000, // "T" - 0b00110000, // "U" - 0b00011000, // "V" - 0b01110000, // "W" - 0b10011000, // "X" - 0b10111000, // "Y" - 0b11001000, // "Z" - 0b10000000, // N/A - 0b10000000, // N/A - 0b10000000, // N/A - 0b10000000, // N/A - 0b10000000, // N/A - 0b10000000, // N/A - 0b01100000, // "a" - 0b10001000, // "b" - 0b10101000, // "c" - 0b10010000, // "d" - 0b01000000, // "e" - 0b00101000, // "f" - 0b11010000, // "g" - 0b00001000, // "h" - 0b00100000, // "i" - 0b01111000, // "j" - 0b10110000, // "k" - 0b01001000, // "l" - 0b11100000, // "m" - 0b10100000, // "n" - 0b11110000, // "o" - 0b01101000, // "p" - 0b11011000, // "q" - 0b01010000, // "r" - 0b00010000, // "s" - 0b11000000, // "t" - 0b00110000, // "u" - 0b00011000, // "v" - 0b01110000, // "w" - 0b10011000, // "x" - 0b10111000, // "y" - 0b11001000 // "z" + 0b11111111, // Special code for SPACE + 0b10000000, // N/A + 0b10000000, // N/A + 0b10000000, // N/A + 0b10000000, // N/A + 0b10000000, // N/A + 0b10000000, // N/A + 0b10000000, // N/A + 0b10000000, // N/A + 0b10000000, // N/A + 0b10000000, // N/A + 0b10000000, // N/A + 0b10000000, // N/A + 0b10000110, // - Hyphen sign + 0b10000000, // N/A + 0b10010100, // "/" Slash + 0b11111100, // "0" + 0b01111100, // "1" + 0b00111100, // "2" + 0b00011100, // "3" + 0b00001100, // "4" + 0b00000100, // "5" + 0b10000100, // "6" + 0b11000100, // "7" + 0b11100100, // "8" + 0b11110100, // "9" + 0b10000000, // N/A + 0b10000000, // N/A + 0b10000000, // N/A + 0b10001100, // "=" BT prosign/Equal sign + 0b10000000, // N/A + 0b00110010, // "?" Question mark + 0b10000000, // N/A + 0b01100000, // "A" + 0b10001000, // "B" + 0b10101000, // "C" + 0b10010000, // "D" + 0b01000000, // "E" + 0b00101000, // "F" + 0b11010000, // "G" + 0b00001000, // "H" + 0b00100000, // "I" + 0b01111000, // "J" + 0b10110000, // "K" + 0b01001000, // "L" + 0b11100000, // "M" + 0b10100000, // "N" + 0b11110000, // "O" + 0b01101000, // "P" + 0b11011000, // "Q" + 0b01010000, // "R" + 0b00010000, // "S" + 0b11000000, // "T" + 0b00110000, // "U" + 0b00011000, // "V" + 0b01110000, // "W" + 0b10011000, // "X" + 0b10111000, // "Y" + 0b11001000, // "Z" + 0b10000000, // N/A + 0b10000000, // N/A + 0b10000000, // N/A + 0b10000000, // N/A + 0b10000000, // N/A + 0b10000000, // N/A + 0b01100000, // "a" + 0b10001000, // "b" + 0b10101000, // "c" + 0b10010000, // "d" + 0b01000000, // "e" + 0b00101000, // "f" + 0b11010000, // "g" + 0b00001000, // "h" + 0b00100000, // "i" + 0b01111000, // "j" + 0b10110000, // "k" + 0b01001000, // "l" + 0b11100000, // "m" + 0b10100000, // "n" + 0b11110000, // "o" + 0b01101000, // "p" + 0b11011000, // "q" + 0b01010000, // "r" + 0b00010000, // "s" + 0b11000000, // "t" + 0b00110000, // "u" + 0b00011000, // "v" + 0b01110000, // "w" + 0b10011000, // "x" + 0b10111000, // "y" + 0b11001000 // "z" }; +void LED_on() { + HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_SET); +} +void LED_off() { + HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET); +} + // https://en.wikipedia.org/wiki/Morse_code#/media/File:International_Morse_Code.svg uint32_t morse_unit_ms = 100; int8_t morse_power = 10; @@ -341,7 +282,6 @@ void play_morse_word(uint8_t* letters, uint8_t len, bool use_cw) { } } - /* USER CODE END 0 */ /** @@ -379,34 +319,47 @@ int main(void) /* USER CODE BEGIN 2 */ //EE_Status ee_status = EE_OK; - - HAL_Delay(1000); // initial start + HAL_Delay(6000); // initial start SetStandbyXOSC(); HAL_Delay(1); SetPacketTypeLora(); HAL_Delay(1); - //SetPaLowPower(); - SetPa22dB(); + + //SetPaLowPower(); // For powers up to 14 dBm + SetPa22dB(); // Uncomment for powers up to 22 dBm HAL_Delay(1); SetTxPower(-9); HAL_Delay(1); SetPacketTypeFSK(); - SetModulationParamsFSK(2000, 0x09, 0x1E, 3000); + SetModulationParamsFSK(2000, 0x09, 0x1E, 2500); - double center_freq = 446.14375; + // Frequency setting in MHz + double center_freq = PMR446[13-1] ;//434.700; + //double center_freq = 223.010; + double freq_correction = 0.99999539941; // Try trimming caps - SetRfFreq(ComputeRfFreq(center_freq)); + SetRfFreq(ComputeRfFreq(center_freq * freq_correction)); /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ + + /* + while (1) { + // Emulate comspec beacon at 40 mW + LED_on(); + CWBeep(16, 50); + LED_off(); + HAL_Delay(1000); + }*/ + while (1) { - HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_SET); + LED_on(); FSKBeep(-9, 500, 200); HAL_Delay(50); @@ -415,16 +368,17 @@ int main(void) HAL_Delay(50); - FSKBeep(10, 1000, 200); + FSKBeep(14, 1000, 200); HAL_Delay(50); - HAL_Delay(1000); - uint8_t callsign[] = "CALLSIGN"; - play_morse_word(callsign, sizeof(callsign)-1, false); + //HAL_Delay(1000); + //uint8_t callsign[] = "HI"; + //play_morse_word(callsign, sizeof(callsign)-1, false); - HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET); - HAL_Delay(3000); + LED_off(); + + HAL_Delay(4000); /* USER CODE END WHILE */ @@ -669,7 +623,113 @@ static void MX_GPIO_Init(void) } /* USER CODE BEGIN 4 */ +void SetStandbyXOSC() { + uint8_t txbuf[2] = {0x80, 0x01}; + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); +} +void SetPacketTypeLora() { + uint8_t txbuf[2] = {0x8A, 0x01}; + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); +} + +void SetPacketTypeFSK() { + uint8_t txbuf[2] = {0x8A, 0x00}; + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); +} + +uint32_t ComputeRfFreq(double frequencyMhz) { + return (uint32_t)(frequencyMhz * 1048576L); //2^25/(32e6) +} + +void SetRfFreq(uint32_t rfFreq) { + uint8_t txbuf[5] = {0x86, (rfFreq & 0xFF000000) >> 24, (rfFreq & 0x00FF0000) >> 16, (rfFreq & 0x0000FF00) >> 8, rfFreq & 0x000000FF}; + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); +} + +void SetPaLowPower() { + // set Pa to 14 dB. + uint8_t txbuf[5] = {0x95, 0x02, 0x02, 0x00, 0x01}; + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); +} + +void SetPa22dB() { + // set Pa to the highest 22 dBm + uint8_t txbuf[5] = {0x95, 0x04, 0x07, 0x00, 0x01}; + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); +} + +void SetTxPower(int8_t powerdBm) { + // Between -9 and 22 + uint8_t txbuf[3] = {0x8E, (uint8_t) powerdBm, 0x02}; + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); +} + +void SetContinuousWave() { + uint8_t txbuf[1] = {0xD1}; + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf, 0); +} + +void SetTxInfinitePreamble() { + uint8_t txbuf[1] = {0xD2}; + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf, 0); +} + +void SetTx(uint32_t timeout) { + // Timeout * 15.625 µs + uint8_t txbuf[4] = {0x83, (timeout & 0x00FF0000) >> 16, (timeout & 0x0000FF00) >> 8, timeout & 0x000000FF}; + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); +} + +void SetRx(uint32_t timeout) { + // Timeout * 15.625 µs + // 0x000000 No timeout. Rx Single mode + // 0xFFFFFF Rx Continuous mode. The device remains in RX mode until the host sends a command to change the operation mode + uint8_t txbuf[4] = {0x82, (timeout & 0x00FF0000) >> 16, (timeout & 0x0000FF00) >> 8, timeout & 0x000000FF}; + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); +} + +void SetModulationParamsLora(const uint8_t params[4]) { + uint8_t txbuf[5] = {0x8B, params[0], params[1], params[2], params[3]}; + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); +} + +void SetModulationParamsFSK(uint32_t bitrate, uint8_t pulseshape, uint8_t bandwidth, uint32_t freq_dev) { + uint32_t BR = 32 * 32e6 / bitrate; + uint32_t fdev = (uint32_t) (freq_dev * 1.048576L); // 2^25/32e6 = 1.048576 + uint8_t txbuf[9] = {0x8B, (BR & 0x00FF0000) >> 16, (BR & 0x0000FF00) >> 8, BR & 0x000000FF, pulseshape, bandwidth, (fdev & 0x00FF0000) >> 16, (fdev & 0x0000FF00) >> 8, fdev & 0x000000FF}; + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); +} + +void SetPacketParamsLora(uint16_t preamble_length, bool header_fixed, uint8_t payload_length, bool crc_enabled, bool invert_iq) { + uint8_t txbuf[7] = {0x8C, (uint8_t)((preamble_length >> 8) & 0xFF), (uint8_t)(preamble_length & 0xFF), + (uint8_t) header_fixed, payload_length, (uint8_t) crc_enabled, (uint8_t) invert_iq}; + + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); +} + + +void FSKBeep(int8_t powerdBm, uint32_t toneHz, uint32_t lengthMs) { + // assume in standbyXOSC already. + HAL_Delay(1); + SetTxPower(powerdBm); + SetModulationParamsFSK(toneHz*2, 0x09, 0x1E, 2500); + HAL_Delay(5); + SetTxInfinitePreamble(); + HAL_Delay(lengthMs); + SetStandbyXOSC(); + HAL_Delay(5); +} + +void CWBeep(int8_t powerdBm, uint32_t lengthMs) { + HAL_Delay(1); + SetTxPower(powerdBm); + HAL_Delay(5); + SetContinuousWave(); + HAL_Delay(lengthMs); + SetStandbyXOSC(); + HAL_Delay(5); +} /* USER CODE END 4 */ /** diff --git a/Firmware/Debug/Core/Src/main.o b/Firmware/Debug/Core/Src/main.o index dd08cc3..231a74c 100644 Binary files a/Firmware/Debug/Core/Src/main.o and b/Firmware/Debug/Core/Src/main.o differ diff --git a/Firmware/Debug/Core/Src/main.su b/Firmware/Debug/Core/Src/main.su index 515c775..eb3f7f7 100644 --- a/Firmware/Debug/Core/Src/main.su +++ b/Firmware/Debug/Core/Src/main.su @@ -1,29 +1,31 @@ ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:999:22:LL_RCC_HSE_EnableDiv2 4 static ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 24 static -../Core/Src/main.c:68:6:SetStandbyXOSC 16 static -../Core/Src/main.c:73:6:SetPacketTypeLora 16 static -../Core/Src/main.c:78:6:SetPacketTypeFSK 16 static -../Core/Src/main.c:83:10:ComputeRfFreq 16 static -../Core/Src/main.c:87:6:SetRfFreq 24 static -../Core/Src/main.c:92:6:SetPaLowPower 16 static -../Core/Src/main.c:98:6:SetPa22dB 16 static -../Core/Src/main.c:104:6:SetTxPower 24 static -../Core/Src/main.c:110:6:SetContinuousWave 16 static -../Core/Src/main.c:115:6:SetTxInfinitePreamble 16 static -../Core/Src/main.c:120:6:SetTx 24 static -../Core/Src/main.c:126:6:SetRx 24 static -../Core/Src/main.c:134:6:SetModulationParamsLora 24 static -../Core/Src/main.c:139:6:SetModulationParamsFSK 48 static -../Core/Src/main.c:146:6:SetPacketParamsLora 32 static -../Core/Src/main.c:154:6:FSKBeep 24 static -../Core/Src/main.c:166:6:CWBeep 16 static -../Core/Src/main.c:277:6:play_morse_char 24 static -../Core/Src/main.c:330:6:play_morse_word 24 static -../Core/Src/main.c:351:5:main 32 static -../Core/Src/main.c:440:6:SystemClock_Config 112 static -../Core/Src/main.c:486:13:MX_ADC_Init 8 static -../Core/Src/main.c:533:13:MX_CRC_Init 8 static -../Core/Src/main.c:564:13:MX_SUBGHZ_Init 8 static -../Core/Src/main.c:590:13:MX_USART2_UART_Init 8 static -../Core/Src/main.c:638:13:MX_GPIO_Init 32 static -../Core/Src/main.c:679:6:Error_Handler 4 static,ignoring_inline_asm +../Core/Src/main.c:207:6:LED_on 8 static +../Core/Src/main.c:210:6:LED_off 8 static +../Core/Src/main.c:218:6:play_morse_char 24 static +../Core/Src/main.c:271:6:play_morse_word 24 static +../Core/Src/main.c:291:5:main 24 static +../Core/Src/main.c:394:6:SystemClock_Config 112 static +../Core/Src/main.c:440:13:MX_ADC_Init 8 static +../Core/Src/main.c:487:13:MX_CRC_Init 8 static +../Core/Src/main.c:518:13:MX_SUBGHZ_Init 8 static +../Core/Src/main.c:544:13:MX_USART2_UART_Init 8 static +../Core/Src/main.c:592:13:MX_GPIO_Init 32 static +../Core/Src/main.c:626:6:SetStandbyXOSC 16 static +../Core/Src/main.c:631:6:SetPacketTypeLora 16 static +../Core/Src/main.c:636:6:SetPacketTypeFSK 16 static +../Core/Src/main.c:641:10:ComputeRfFreq 16 static +../Core/Src/main.c:645:6:SetRfFreq 24 static +../Core/Src/main.c:650:6:SetPaLowPower 16 static +../Core/Src/main.c:656:6:SetPa22dB 16 static +../Core/Src/main.c:662:6:SetTxPower 24 static +../Core/Src/main.c:668:6:SetContinuousWave 16 static +../Core/Src/main.c:673:6:SetTxInfinitePreamble 16 static +../Core/Src/main.c:678:6:SetTx 24 static +../Core/Src/main.c:684:6:SetRx 24 static +../Core/Src/main.c:692:6:SetModulationParamsLora 24 static +../Core/Src/main.c:697:6:SetModulationParamsFSK 48 static +../Core/Src/main.c:704:6:SetPacketParamsLora 32 static +../Core/Src/main.c:712:6:FSKBeep 24 static +../Core/Src/main.c:724:6:CWBeep 16 static +../Core/Src/main.c:739:6:Error_Handler 4 static,ignoring_inline_asm diff --git a/Firmware/Debug/rocketbeacon.elf b/Firmware/Debug/rocketbeacon.elf index afba389..ee35637 100644 Binary files a/Firmware/Debug/rocketbeacon.elf and b/Firmware/Debug/rocketbeacon.elf differ diff --git a/Firmware/Debug/rocketbeacon.list b/Firmware/Debug/rocketbeacon.list index a07f4ef..e214d51 100644 --- a/Firmware/Debug/rocketbeacon.list +++ b/Firmware/Debug/rocketbeacon.list @@ -5,45 +5,45 @@ Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000138 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA - 1 .text 00004848 08000138 08000138 00010138 2**3 + 1 .text 00004654 08000138 08000138 00010138 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 .rodata 0000015c 08004980 08004980 00014980 2**2 + 2 .rodata 000000f4 0800478c 0800478c 0001478c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 3 .ARM.extab 00000000 08004adc 08004adc 00020014 2**0 + 3 .ARM.extab 00000000 08004880 08004880 0002000c 2**0 CONTENTS - 4 .ARM 00000008 08004adc 08004adc 00014adc 2**2 + 4 .ARM 00000008 08004880 08004880 00014880 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 5 .preinit_array 00000000 08004ae4 08004ae4 00020014 2**0 + 5 .preinit_array 00000000 08004888 08004888 0002000c 2**0 CONTENTS, ALLOC, LOAD, DATA - 6 .init_array 00000004 08004ae4 08004ae4 00014ae4 2**2 + 6 .init_array 00000004 08004888 08004888 00014888 2**2 CONTENTS, ALLOC, LOAD, DATA - 7 .fini_array 00000004 08004ae8 08004ae8 00014ae8 2**2 + 7 .fini_array 00000004 0800488c 0800488c 0001488c 2**2 CONTENTS, ALLOC, LOAD, DATA - 8 .data 00000014 20000000 08004aec 00020000 2**2 + 8 .data 0000000c 20000000 08004890 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA - 9 .bss 00000148 20000014 08004b00 00020014 2**2 + 9 .bss 00000148 2000000c 0800489c 0002000c 2**2 ALLOC - 10 ._user_heap_stack 00000604 2000015c 08004b00 0002015c 2**0 + 10 ._user_heap_stack 00000604 20000154 0800489c 00020154 2**0 ALLOC - 11 .ARM.attributes 0000002a 00000000 00000000 00020014 2**0 + 11 .ARM.attributes 0000002a 00000000 00000000 0002000c 2**0 CONTENTS, READONLY - 12 .debug_info 00012268 00000000 00000000 0002003e 2**0 + 12 .debug_info 00012328 00000000 00000000 00020036 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 13 .debug_abbrev 00002862 00000000 00000000 000322a6 2**0 + 13 .debug_abbrev 0000285c 00000000 00000000 0003235e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 14 .debug_aranges 00001358 00000000 00000000 00034b08 2**3 + 14 .debug_aranges 00001368 00000000 00000000 00034bc0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS - 15 .debug_ranges 00001270 00000000 00000000 00035e60 2**3 + 15 .debug_ranges 00001280 00000000 00000000 00035f28 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS - 16 .debug_macro 0001ab62 00000000 00000000 000370d0 2**0 + 16 .debug_macro 0001ab62 00000000 00000000 000371a8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 17 .debug_line 00011d8a 00000000 00000000 00051c32 2**0 + 17 .debug_line 00011daa 00000000 00000000 00051d0a 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 18 .debug_str 000a7721 00000000 00000000 000639bc 2**0 + 18 .debug_str 000a7745 00000000 00000000 00063ab4 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 19 .comment 00000050 00000000 00000000 0010b0dd 2**0 + 19 .comment 00000050 00000000 00000000 0010b1f9 2**0 CONTENTS, READONLY - 20 .debug_frame 00005250 00000000 00000000 0010b130 2**2 + 20 .debug_frame 00005288 00000000 00000000 0010b24c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: @@ -60,9 +60,9 @@ Disassembly of section .text: 800014a: 2301 movs r3, #1 800014c: 7023 strb r3, [r4, #0] 800014e: bd10 pop {r4, pc} - 8000150: 20000014 .word 0x20000014 + 8000150: 2000000c .word 0x2000000c 8000154: 00000000 .word 0x00000000 - 8000158: 08004968 .word 0x08004968 + 8000158: 08004774 .word 0x08004774 0800015c : 800015c: b508 push {r3, lr} @@ -73,8 +73,8 @@ Disassembly of section .text: 8000166: f3af 8000 nop.w 800016a: bd08 pop {r3, pc} 800016c: 00000000 .word 0x00000000 - 8000170: 20000018 .word 0x20000018 - 8000174: 08004968 .word 0x08004968 + 8000170: 20000010 .word 0x20000010 + 8000174: 08004774 .word 0x08004774 08000178 <__aeabi_drsub>: 8000178: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 @@ -1054,10923 +1054,10626 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) 8000ca0: bc80 pop {r7} 8000ca2: 4770 bx lr -08000ca4 : -/* USER CODE END PFP */ +08000ca4 : + 0b10011000, // "x" + 0b10111000, // "y" + 0b11001000 // "z" +}; -/* Private user code ---------------------------------------------------------*/ -/* USER CODE BEGIN 0 */ - -void SetStandbyXOSC() { +void LED_on() { 8000ca4: b580 push {r7, lr} - 8000ca6: b082 sub sp, #8 - 8000ca8: af00 add r7, sp, #0 - uint8_t txbuf[2] = {0x80, 0x01}; - 8000caa: f44f 73c0 mov.w r3, #384 ; 0x180 - 8000cae: 80bb strh r3, [r7, #4] - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); - 8000cb0: 7939 ldrb r1, [r7, #4] - 8000cb2: 1d3a adds r2, r7, #4 - 8000cb4: 3201 adds r2, #1 - 8000cb6: 2301 movs r3, #1 - 8000cb8: 4803 ldr r0, [pc, #12] ; (8000cc8 ) - 8000cba: f002 ff63 bl 8003b84 -} - 8000cbe: bf00 nop - 8000cc0: 3708 adds r7, #8 - 8000cc2: 46bd mov sp, r7 - 8000cc4: bd80 pop {r7, pc} - 8000cc6: bf00 nop - 8000cc8: 200000b8 .word 0x200000b8 - -08000ccc : - -void SetPacketTypeLora() { - 8000ccc: b580 push {r7, lr} - 8000cce: b082 sub sp, #8 - 8000cd0: af00 add r7, sp, #0 - uint8_t txbuf[2] = {0x8A, 0x01}; - 8000cd2: f44f 73c5 mov.w r3, #394 ; 0x18a - 8000cd6: 80bb strh r3, [r7, #4] - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); - 8000cd8: 7939 ldrb r1, [r7, #4] - 8000cda: 1d3a adds r2, r7, #4 - 8000cdc: 3201 adds r2, #1 - 8000cde: 2301 movs r3, #1 - 8000ce0: 4803 ldr r0, [pc, #12] ; (8000cf0 ) - 8000ce2: f002 ff4f bl 8003b84 -} - 8000ce6: bf00 nop - 8000ce8: 3708 adds r7, #8 - 8000cea: 46bd mov sp, r7 - 8000cec: bd80 pop {r7, pc} - 8000cee: bf00 nop - 8000cf0: 200000b8 .word 0x200000b8 - -08000cf4 : - -void SetPacketTypeFSK() { - 8000cf4: b580 push {r7, lr} - 8000cf6: b082 sub sp, #8 - 8000cf8: af00 add r7, sp, #0 - uint8_t txbuf[2] = {0x8A, 0x00}; - 8000cfa: 238a movs r3, #138 ; 0x8a - 8000cfc: 80bb strh r3, [r7, #4] - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); - 8000cfe: 7939 ldrb r1, [r7, #4] - 8000d00: 1d3a adds r2, r7, #4 - 8000d02: 3201 adds r2, #1 - 8000d04: 2301 movs r3, #1 - 8000d06: 4803 ldr r0, [pc, #12] ; (8000d14 ) - 8000d08: f002 ff3c bl 8003b84 -} - 8000d0c: bf00 nop - 8000d0e: 3708 adds r7, #8 - 8000d10: 46bd mov sp, r7 - 8000d12: bd80 pop {r7, pc} - 8000d14: 200000b8 .word 0x200000b8 - -08000d18 : - -uint32_t ComputeRfFreq(double frequencyMhz) { - 8000d18: b580 push {r7, lr} - 8000d1a: b082 sub sp, #8 - 8000d1c: af00 add r7, sp, #0 - 8000d1e: e9c7 0100 strd r0, r1, [r7] - return (uint32_t)(frequencyMhz * 1048576L); //2^25/(32e6) - 8000d22: f04f 0200 mov.w r2, #0 - 8000d26: 4b08 ldr r3, [pc, #32] ; (8000d48 ) - 8000d28: e9d7 0100 ldrd r0, r1, [r7] - 8000d2c: f7ff fbe0 bl 80004f0 <__aeabi_dmul> - 8000d30: 4602 mov r2, r0 - 8000d32: 460b mov r3, r1 - 8000d34: 4610 mov r0, r2 - 8000d36: 4619 mov r1, r3 - 8000d38: f7ff fdec bl 8000914 <__aeabi_d2uiz> - 8000d3c: 4603 mov r3, r0 -} - 8000d3e: 4618 mov r0, r3 - 8000d40: 3708 adds r7, #8 - 8000d42: 46bd mov sp, r7 - 8000d44: bd80 pop {r7, pc} - 8000d46: bf00 nop - 8000d48: 41300000 .word 0x41300000 - -08000d4c : - -void SetRfFreq(uint32_t rfFreq) { - 8000d4c: b580 push {r7, lr} - 8000d4e: b084 sub sp, #16 - 8000d50: af00 add r7, sp, #0 - 8000d52: 6078 str r0, [r7, #4] - uint8_t txbuf[5] = {0x86, (rfFreq & 0xFF000000) >> 24, (rfFreq & 0x00FF0000) >> 16, (rfFreq & 0x0000FF00) >> 8, rfFreq & 0x000000FF}; - 8000d54: 2386 movs r3, #134 ; 0x86 - 8000d56: 723b strb r3, [r7, #8] - 8000d58: 687b ldr r3, [r7, #4] - 8000d5a: 0e1b lsrs r3, r3, #24 - 8000d5c: b2db uxtb r3, r3 - 8000d5e: 727b strb r3, [r7, #9] - 8000d60: 687b ldr r3, [r7, #4] - 8000d62: 0c1b lsrs r3, r3, #16 - 8000d64: b2db uxtb r3, r3 - 8000d66: 72bb strb r3, [r7, #10] - 8000d68: 687b ldr r3, [r7, #4] - 8000d6a: 0a1b lsrs r3, r3, #8 - 8000d6c: b2db uxtb r3, r3 - 8000d6e: 72fb strb r3, [r7, #11] - 8000d70: 687b ldr r3, [r7, #4] - 8000d72: b2db uxtb r3, r3 - 8000d74: 733b strb r3, [r7, #12] - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); - 8000d76: 7a39 ldrb r1, [r7, #8] - 8000d78: f107 0208 add.w r2, r7, #8 - 8000d7c: 3201 adds r2, #1 - 8000d7e: 2304 movs r3, #4 - 8000d80: 4803 ldr r0, [pc, #12] ; (8000d90 ) - 8000d82: f002 feff bl 8003b84 -} - 8000d86: bf00 nop - 8000d88: 3710 adds r7, #16 - 8000d8a: 46bd mov sp, r7 - 8000d8c: bd80 pop {r7, pc} - 8000d8e: bf00 nop - 8000d90: 200000b8 .word 0x200000b8 - -08000d94 : - // set Pa to 14 dB. - uint8_t txbuf[5] = {0x95, 0x02, 0x02, 0x00, 0x01}; - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); -} - -void SetPa22dB() { - 8000d94: b580 push {r7, lr} - 8000d96: b082 sub sp, #8 - 8000d98: af00 add r7, sp, #0 - // set Pa to the highest 22 dBm - uint8_t txbuf[5] = {0x95, 0x04, 0x07, 0x00, 0x01}; - 8000d9a: 4a09 ldr r2, [pc, #36] ; (8000dc0 ) - 8000d9c: 463b mov r3, r7 - 8000d9e: e892 0003 ldmia.w r2, {r0, r1} - 8000da2: 6018 str r0, [r3, #0] - 8000da4: 3304 adds r3, #4 - 8000da6: 7019 strb r1, [r3, #0] - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); - 8000da8: 7839 ldrb r1, [r7, #0] - 8000daa: 463a mov r2, r7 - 8000dac: 3201 adds r2, #1 - 8000dae: 2304 movs r3, #4 - 8000db0: 4804 ldr r0, [pc, #16] ; (8000dc4 ) - 8000db2: f002 fee7 bl 8003b84 -} - 8000db6: bf00 nop - 8000db8: 3708 adds r7, #8 - 8000dba: 46bd mov sp, r7 - 8000dbc: bd80 pop {r7, pc} - 8000dbe: bf00 nop - 8000dc0: 08004988 .word 0x08004988 - 8000dc4: 200000b8 .word 0x200000b8 - -08000dc8 : - -void SetTxPower(int8_t powerdBm) { - 8000dc8: b580 push {r7, lr} - 8000dca: b084 sub sp, #16 - 8000dcc: af00 add r7, sp, #0 - 8000dce: 4603 mov r3, r0 - 8000dd0: 71fb strb r3, [r7, #7] - // Between -9 and 22 - uint8_t txbuf[3] = {0x8E, (uint8_t) powerdBm, 0x02}; - 8000dd2: 238e movs r3, #142 ; 0x8e - 8000dd4: 733b strb r3, [r7, #12] - 8000dd6: 79fb ldrb r3, [r7, #7] - 8000dd8: 737b strb r3, [r7, #13] - 8000dda: 2302 movs r3, #2 - 8000ddc: 73bb strb r3, [r7, #14] - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); - 8000dde: 7b39 ldrb r1, [r7, #12] - 8000de0: f107 020c add.w r2, r7, #12 - 8000de4: 3201 adds r2, #1 - 8000de6: 2302 movs r3, #2 - 8000de8: 4803 ldr r0, [pc, #12] ; (8000df8 ) - 8000dea: f002 fecb bl 8003b84 -} - 8000dee: bf00 nop - 8000df0: 3710 adds r7, #16 - 8000df2: 46bd mov sp, r7 - 8000df4: bd80 pop {r7, pc} - 8000df6: bf00 nop - 8000df8: 200000b8 .word 0x200000b8 - -08000dfc : - -void SetContinuousWave() { - 8000dfc: b580 push {r7, lr} - 8000dfe: b082 sub sp, #8 - 8000e00: af00 add r7, sp, #0 - uint8_t txbuf[1] = {0xD1}; - 8000e02: 23d1 movs r3, #209 ; 0xd1 - 8000e04: 713b strb r3, [r7, #4] - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf, 0); - 8000e06: 7939 ldrb r1, [r7, #4] - 8000e08: 1d3a adds r2, r7, #4 - 8000e0a: 2300 movs r3, #0 - 8000e0c: 4803 ldr r0, [pc, #12] ; (8000e1c ) - 8000e0e: f002 feb9 bl 8003b84 -} - 8000e12: bf00 nop - 8000e14: 3708 adds r7, #8 - 8000e16: 46bd mov sp, r7 - 8000e18: bd80 pop {r7, pc} - 8000e1a: bf00 nop - 8000e1c: 200000b8 .word 0x200000b8 - -08000e20 : - -void SetTxInfinitePreamble() { - 8000e20: b580 push {r7, lr} - 8000e22: b082 sub sp, #8 - 8000e24: af00 add r7, sp, #0 - uint8_t txbuf[1] = {0xD2}; - 8000e26: 23d2 movs r3, #210 ; 0xd2 - 8000e28: 713b strb r3, [r7, #4] - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf, 0); - 8000e2a: 7939 ldrb r1, [r7, #4] - 8000e2c: 1d3a adds r2, r7, #4 - 8000e2e: 2300 movs r3, #0 - 8000e30: 4803 ldr r0, [pc, #12] ; (8000e40 ) - 8000e32: f002 fea7 bl 8003b84 -} - 8000e36: bf00 nop - 8000e38: 3708 adds r7, #8 - 8000e3a: 46bd mov sp, r7 - 8000e3c: bd80 pop {r7, pc} - 8000e3e: bf00 nop - 8000e40: 200000b8 .word 0x200000b8 - 8000e44: 00000000 .word 0x00000000 - -08000e48 : -void SetModulationParamsLora(const uint8_t params[4]) { - uint8_t txbuf[5] = {0x8B, params[0], params[1], params[2], params[3]}; - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); -} - -void SetModulationParamsFSK(uint32_t bitrate, uint8_t pulseshape, uint8_t bandwidth, uint32_t freq_dev) { - 8000e48: b580 push {r7, lr} - 8000e4a: b08a sub sp, #40 ; 0x28 - 8000e4c: af00 add r7, sp, #0 - 8000e4e: 60f8 str r0, [r7, #12] - 8000e50: 607b str r3, [r7, #4] - 8000e52: 460b mov r3, r1 - 8000e54: 72fb strb r3, [r7, #11] - 8000e56: 4613 mov r3, r2 - 8000e58: 72bb strb r3, [r7, #10] - uint32_t BR = 32 * 32e6 / bitrate; - 8000e5a: 68f8 ldr r0, [r7, #12] - 8000e5c: f7ff face bl 80003fc <__aeabi_ui2d> - 8000e60: 4602 mov r2, r0 - 8000e62: 460b mov r3, r1 - 8000e64: a122 add r1, pc, #136 ; (adr r1, 8000ef0 ) - 8000e66: e9d1 0100 ldrd r0, r1, [r1] - 8000e6a: f7ff fc6b bl 8000744 <__aeabi_ddiv> - 8000e6e: 4602 mov r2, r0 - 8000e70: 460b mov r3, r1 - 8000e72: 4610 mov r0, r2 - 8000e74: 4619 mov r1, r3 - 8000e76: f7ff fd4d bl 8000914 <__aeabi_d2uiz> - 8000e7a: 4603 mov r3, r0 - 8000e7c: 627b str r3, [r7, #36] ; 0x24 - uint32_t fdev = (uint32_t) (freq_dev * 1.048576L); // 2^25/32e6 = 1.048576 - 8000e7e: 6878 ldr r0, [r7, #4] - 8000e80: f7ff fabc bl 80003fc <__aeabi_ui2d> - 8000e84: a31c add r3, pc, #112 ; (adr r3, 8000ef8 ) - 8000e86: e9d3 2300 ldrd r2, r3, [r3] - 8000e8a: f7ff fb31 bl 80004f0 <__aeabi_dmul> - 8000e8e: 4602 mov r2, r0 - 8000e90: 460b mov r3, r1 - 8000e92: 4610 mov r0, r2 - 8000e94: 4619 mov r1, r3 - 8000e96: f7ff fd3d bl 8000914 <__aeabi_d2uiz> - 8000e9a: 4603 mov r3, r0 - 8000e9c: 623b str r3, [r7, #32] - uint8_t txbuf[9] = {0x8B, (BR & 0x00FF0000) >> 16, (BR & 0x0000FF00) >> 8, BR & 0x000000FF, pulseshape, bandwidth, (fdev & 0x00FF0000) >> 16, (fdev & 0x0000FF00) >> 8, fdev & 0x000000FF}; - 8000e9e: 238b movs r3, #139 ; 0x8b - 8000ea0: 753b strb r3, [r7, #20] - 8000ea2: 6a7b ldr r3, [r7, #36] ; 0x24 - 8000ea4: 0c1b lsrs r3, r3, #16 - 8000ea6: b2db uxtb r3, r3 - 8000ea8: 757b strb r3, [r7, #21] - 8000eaa: 6a7b ldr r3, [r7, #36] ; 0x24 - 8000eac: 0a1b lsrs r3, r3, #8 - 8000eae: b2db uxtb r3, r3 - 8000eb0: 75bb strb r3, [r7, #22] - 8000eb2: 6a7b ldr r3, [r7, #36] ; 0x24 - 8000eb4: b2db uxtb r3, r3 - 8000eb6: 75fb strb r3, [r7, #23] - 8000eb8: 7afb ldrb r3, [r7, #11] - 8000eba: 763b strb r3, [r7, #24] - 8000ebc: 7abb ldrb r3, [r7, #10] - 8000ebe: 767b strb r3, [r7, #25] - 8000ec0: 6a3b ldr r3, [r7, #32] - 8000ec2: 0c1b lsrs r3, r3, #16 - 8000ec4: b2db uxtb r3, r3 - 8000ec6: 76bb strb r3, [r7, #26] - 8000ec8: 6a3b ldr r3, [r7, #32] - 8000eca: 0a1b lsrs r3, r3, #8 - 8000ecc: b2db uxtb r3, r3 - 8000ece: 76fb strb r3, [r7, #27] - 8000ed0: 6a3b ldr r3, [r7, #32] - 8000ed2: b2db uxtb r3, r3 - 8000ed4: 773b strb r3, [r7, #28] - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); - 8000ed6: 7d39 ldrb r1, [r7, #20] - 8000ed8: f107 0214 add.w r2, r7, #20 - 8000edc: 3201 adds r2, #1 - 8000ede: 2308 movs r3, #8 - 8000ee0: 4807 ldr r0, [pc, #28] ; (8000f00 ) - 8000ee2: f002 fe4f bl 8003b84 -} - 8000ee6: bf00 nop - 8000ee8: 3728 adds r7, #40 ; 0x28 - 8000eea: 46bd mov sp, r7 - 8000eec: bd80 pop {r7, pc} - 8000eee: bf00 nop - 8000ef0: 00000000 .word 0x00000000 - 8000ef4: 41ce8480 .word 0x41ce8480 - 8000ef8: a0b5ed8d .word 0xa0b5ed8d - 8000efc: 3ff0c6f7 .word 0x3ff0c6f7 - 8000f00: 200000b8 .word 0x200000b8 - -08000f04 : - - HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); -} - - -void FSKBeep(int8_t powerdBm, uint32_t toneHz, uint32_t lengthMs) { - 8000f04: b580 push {r7, lr} - 8000f06: b084 sub sp, #16 - 8000f08: af00 add r7, sp, #0 - 8000f0a: 4603 mov r3, r0 - 8000f0c: 60b9 str r1, [r7, #8] - 8000f0e: 607a str r2, [r7, #4] - 8000f10: 73fb strb r3, [r7, #15] - // assume in standbyXOSC already. - HAL_Delay(1); - 8000f12: 2001 movs r0, #1 - 8000f14: f000 fccc bl 80018b0 - SetTxPower(powerdBm); - 8000f18: f997 300f ldrsb.w r3, [r7, #15] - 8000f1c: 4618 mov r0, r3 - 8000f1e: f7ff ff53 bl 8000dc8 - SetModulationParamsFSK(toneHz*2, 0x09, 0x1E, 2500); - 8000f22: 68bb ldr r3, [r7, #8] - 8000f24: 0058 lsls r0, r3, #1 - 8000f26: f640 13c4 movw r3, #2500 ; 0x9c4 - 8000f2a: 221e movs r2, #30 - 8000f2c: 2109 movs r1, #9 - 8000f2e: f7ff ff8b bl 8000e48 - HAL_Delay(5); - 8000f32: 2005 movs r0, #5 - 8000f34: f000 fcbc bl 80018b0 - SetTxInfinitePreamble(); - 8000f38: f7ff ff72 bl 8000e20 - HAL_Delay(lengthMs); - 8000f3c: 6878 ldr r0, [r7, #4] - 8000f3e: f000 fcb7 bl 80018b0 - SetStandbyXOSC(); - 8000f42: f7ff feaf bl 8000ca4 - HAL_Delay(5); - 8000f46: 2005 movs r0, #5 - 8000f48: f000 fcb2 bl 80018b0 -} - 8000f4c: bf00 nop - 8000f4e: 3710 adds r7, #16 - 8000f50: 46bd mov sp, r7 - 8000f52: bd80 pop {r7, pc} - -08000f54 : - -void CWBeep(int8_t powerdBm, uint32_t lengthMs) { - 8000f54: b580 push {r7, lr} - 8000f56: b082 sub sp, #8 - 8000f58: af00 add r7, sp, #0 - 8000f5a: 4603 mov r3, r0 - 8000f5c: 6039 str r1, [r7, #0] - 8000f5e: 71fb strb r3, [r7, #7] - HAL_Delay(1); - 8000f60: 2001 movs r0, #1 - 8000f62: f000 fca5 bl 80018b0 - SetTxPower(powerdBm); - 8000f66: f997 3007 ldrsb.w r3, [r7, #7] - 8000f6a: 4618 mov r0, r3 - 8000f6c: f7ff ff2c bl 8000dc8 - HAL_Delay(5); - 8000f70: 2005 movs r0, #5 - 8000f72: f000 fc9d bl 80018b0 - SetContinuousWave(); - 8000f76: f7ff ff41 bl 8000dfc - HAL_Delay(lengthMs); - 8000f7a: 6838 ldr r0, [r7, #0] - 8000f7c: f000 fc98 bl 80018b0 - SetStandbyXOSC(); - 8000f80: f7ff fe90 bl 8000ca4 - HAL_Delay(5); - 8000f84: 2005 movs r0, #5 - 8000f86: f000 fc93 bl 80018b0 -} - 8000f8a: bf00 nop - 8000f8c: 3708 adds r7, #8 - 8000f8e: 46bd mov sp, r7 - 8000f90: bd80 pop {r7, pc} - ... - -08000f94 : - -// https://en.wikipedia.org/wiki/Morse_code#/media/File:International_Morse_Code.svg -uint32_t morse_unit_ms = 100; -int8_t morse_power = 10; - -void play_morse_char(uint8_t ascii_letter, bool use_cw) { - 8000f94: b580 push {r7, lr} - 8000f96: b084 sub sp, #16 - 8000f98: af00 add r7, sp, #0 - 8000f9a: 4603 mov r3, r0 - 8000f9c: 460a mov r2, r1 - 8000f9e: 71fb strb r3, [r7, #7] - 8000fa0: 4613 mov r3, r2 - 8000fa2: 71bb strb r3, [r7, #6] - uint8_t morse_code = 0b11111111; - 8000fa4: 23ff movs r3, #255 ; 0xff - 8000fa6: 73fb strb r3, [r7, #15] - if (ascii_letter > 31 && ascii_letter < 123) { - 8000fa8: 79fb ldrb r3, [r7, #7] - 8000faa: 2b1f cmp r3, #31 - 8000fac: d907 bls.n 8000fbe - 8000fae: 79fb ldrb r3, [r7, #7] - 8000fb0: 2b7a cmp r3, #122 ; 0x7a - 8000fb2: d804 bhi.n 8000fbe - morse_code = morse_chars[ascii_letter - 32]; - 8000fb4: 79fb ldrb r3, [r7, #7] - 8000fb6: 3b20 subs r3, #32 - 8000fb8: 4a40 ldr r2, [pc, #256] ; (80010bc ) - 8000fba: 5cd3 ldrb r3, [r2, r3] - 8000fbc: 73fb strb r3, [r7, #15] - } - - // space - if (morse_code == 0b11111111) { - 8000fbe: 7bfb ldrb r3, [r7, #15] - 8000fc0: 2bff cmp r3, #255 ; 0xff - 8000fc2: d10e bne.n 8000fe2 - if (use_cw) { - 8000fc4: 79bb ldrb r3, [r7, #6] - 8000fc6: 2b00 cmp r3, #0 - 8000fc8: d005 beq.n 8000fd6 - HAL_Delay(morse_unit_ms); - 8000fca: 4b3d ldr r3, [pc, #244] ; (80010c0 ) - 8000fcc: 681b ldr r3, [r3, #0] - 8000fce: 4618 mov r0, r3 - 8000fd0: f000 fc6e bl 80018b0 - } else { - //FSKBeep(morse_power, 750, morse_unit_ms); - HAL_Delay(morse_unit_ms); - } - return; - 8000fd4: e06f b.n 80010b6 - HAL_Delay(morse_unit_ms); - 8000fd6: 4b3a ldr r3, [pc, #232] ; (80010c0 ) - 8000fd8: 681b ldr r3, [r3, #0] - 8000fda: 4618 mov r0, r3 - 8000fdc: f000 fc68 bl 80018b0 - return; - 8000fe0: e069 b.n 80010b6 - } - uint8_t terminatelen = 0; - 8000fe2: 2300 movs r3, #0 - 8000fe4: 73bb strb r3, [r7, #14] - for (uint8_t idx = 0; idx < 8; idx++) { - 8000fe6: 2300 movs r3, #0 - 8000fe8: 737b strb r3, [r7, #13] - 8000fea: e00d b.n 8001008 - if (morse_code & (1 << idx)) { - 8000fec: 7bfa ldrb r2, [r7, #15] - 8000fee: 7b7b ldrb r3, [r7, #13] - 8000ff0: fa42 f303 asr.w r3, r2, r3 - 8000ff4: f003 0301 and.w r3, r3, #1 - 8000ff8: 2b00 cmp r3, #0 - 8000ffa: d002 beq.n 8001002 - terminatelen = idx; - 8000ffc: 7b7b ldrb r3, [r7, #13] - 8000ffe: 73bb strb r3, [r7, #14] - break; - 8001000: e005 b.n 800100e - for (uint8_t idx = 0; idx < 8; idx++) { - 8001002: 7b7b ldrb r3, [r7, #13] - 8001004: 3301 adds r3, #1 - 8001006: 737b strb r3, [r7, #13] - 8001008: 7b7b ldrb r3, [r7, #13] - 800100a: 2b07 cmp r3, #7 - 800100c: d9ee bls.n 8000fec - } - } - - for (uint8_t i = 7; i > terminatelen; i--) { - 800100e: 2307 movs r3, #7 - 8001010: 733b strb r3, [r7, #12] - 8001012: e04c b.n 80010ae - if (morse_code & (1 << i)) { - 8001014: 7bfa ldrb r2, [r7, #15] - 8001016: 7b3b ldrb r3, [r7, #12] - 8001018: fa42 f303 asr.w r3, r2, r3 - 800101c: f003 0301 and.w r3, r3, #1 - 8001020: 2b00 cmp r3, #0 - 8001022: d01c beq.n 800105e - // make dat - //printf("-"); - if (use_cw) { - 8001024: 79bb ldrb r3, [r7, #6] - 8001026: 2b00 cmp r3, #0 - 8001028: d00b beq.n 8001042 - CWBeep(morse_power, morse_unit_ms * 3); - 800102a: 4b26 ldr r3, [pc, #152] ; (80010c4 ) - 800102c: f993 0000 ldrsb.w r0, [r3] - 8001030: 4b23 ldr r3, [pc, #140] ; (80010c0 ) - 8001032: 681a ldr r2, [r3, #0] - 8001034: 4613 mov r3, r2 - 8001036: 005b lsls r3, r3, #1 - 8001038: 4413 add r3, r2 - 800103a: 4619 mov r1, r3 - 800103c: f7ff ff8a bl 8000f54 - 8001040: e024 b.n 800108c - } else { - FSKBeep(morse_power, 750, morse_unit_ms * 3); - 8001042: 4b20 ldr r3, [pc, #128] ; (80010c4 ) - 8001044: f993 0000 ldrsb.w r0, [r3] - 8001048: 4b1d ldr r3, [pc, #116] ; (80010c0 ) - 800104a: 681a ldr r2, [r3, #0] - 800104c: 4613 mov r3, r2 - 800104e: 005b lsls r3, r3, #1 - 8001050: 4413 add r3, r2 - 8001052: 461a mov r2, r3 - 8001054: f240 21ee movw r1, #750 ; 0x2ee - 8001058: f7ff ff54 bl 8000f04 - 800105c: e016 b.n 800108c - } - } else { - // make dit - //printf("."); - if (use_cw) { - 800105e: 79bb ldrb r3, [r7, #6] - 8001060: 2b00 cmp r3, #0 - 8001062: d009 beq.n 8001078 - CWBeep(morse_power, morse_unit_ms); - 8001064: 4b17 ldr r3, [pc, #92] ; (80010c4 ) - 8001066: f993 3000 ldrsb.w r3, [r3] - 800106a: 4a15 ldr r2, [pc, #84] ; (80010c0 ) - 800106c: 6812 ldr r2, [r2, #0] - 800106e: 4611 mov r1, r2 - 8001070: 4618 mov r0, r3 - 8001072: f7ff ff6f bl 8000f54 - 8001076: e009 b.n 800108c - } else { - FSKBeep(morse_power, 750, morse_unit_ms); - 8001078: 4b12 ldr r3, [pc, #72] ; (80010c4 ) - 800107a: f993 3000 ldrsb.w r3, [r3] - 800107e: 4a10 ldr r2, [pc, #64] ; (80010c0 ) - 8001080: 6812 ldr r2, [r2, #0] - 8001082: f240 21ee movw r1, #750 ; 0x2ee - 8001086: 4618 mov r0, r3 - 8001088: f7ff ff3c bl 8000f04 - } - } - - // Make delay. - if (use_cw) { - 800108c: 79bb ldrb r3, [r7, #6] - 800108e: 2b00 cmp r3, #0 - 8001090: d005 beq.n 800109e - HAL_Delay(morse_unit_ms); - 8001092: 4b0b ldr r3, [pc, #44] ; (80010c0 ) - 8001094: 681b ldr r3, [r3, #0] - 8001096: 4618 mov r0, r3 - 8001098: f000 fc0a bl 80018b0 - 800109c: e004 b.n 80010a8 - } else { - HAL_Delay(morse_unit_ms); - 800109e: 4b08 ldr r3, [pc, #32] ; (80010c0 ) - 80010a0: 681b ldr r3, [r3, #0] - 80010a2: 4618 mov r0, r3 - 80010a4: f000 fc04 bl 80018b0 - for (uint8_t i = 7; i > terminatelen; i--) { - 80010a8: 7b3b ldrb r3, [r7, #12] - 80010aa: 3b01 subs r3, #1 - 80010ac: 733b strb r3, [r7, #12] - 80010ae: 7b3a ldrb r2, [r7, #12] - 80010b0: 7bbb ldrb r3, [r7, #14] - 80010b2: 429a cmp r2, r3 - 80010b4: d8ae bhi.n 8001014 - //CWBeep(morse_power, morse_unit_ms); - } - } -} - 80010b6: 3710 adds r7, #16 - 80010b8: 46bd mov sp, r7 - 80010ba: bd80 pop {r7, pc} - 80010bc: 080049b8 .word 0x080049b8 - 80010c0: 20000000 .word 0x20000000 - 80010c4: 20000004 .word 0x20000004 - -080010c8 : - -void play_morse_word(uint8_t* letters, uint8_t len, bool use_cw) { - 80010c8: b580 push {r7, lr} - 80010ca: b084 sub sp, #16 - 80010cc: af00 add r7, sp, #0 - 80010ce: 6078 str r0, [r7, #4] - 80010d0: 460b mov r3, r1 - 80010d2: 70fb strb r3, [r7, #3] - 80010d4: 4613 mov r3, r2 - 80010d6: 70bb strb r3, [r7, #2] - for (uint8_t i = 0; i < len; i++) { - 80010d8: 2300 movs r3, #0 - 80010da: 73fb strb r3, [r7, #15] - 80010dc: e01f b.n 800111e - play_morse_char(letters[i], use_cw); - 80010de: 7bfb ldrb r3, [r7, #15] - 80010e0: 687a ldr r2, [r7, #4] - 80010e2: 4413 add r3, r2 - 80010e4: 781b ldrb r3, [r3, #0] - 80010e6: 78ba ldrb r2, [r7, #2] - 80010e8: 4611 mov r1, r2 - 80010ea: 4618 mov r0, r3 - 80010ec: f7ff ff52 bl 8000f94 - - // Space between letters - if (use_cw) { - 80010f0: 78bb ldrb r3, [r7, #2] - 80010f2: 2b00 cmp r3, #0 - 80010f4: d008 beq.n 8001108 - HAL_Delay(morse_unit_ms * 3); - 80010f6: 4b0e ldr r3, [pc, #56] ; (8001130 ) - 80010f8: 681a ldr r2, [r3, #0] - 80010fa: 4613 mov r3, r2 - 80010fc: 005b lsls r3, r3, #1 - 80010fe: 4413 add r3, r2 - 8001100: 4618 mov r0, r3 - 8001102: f000 fbd5 bl 80018b0 - 8001106: e007 b.n 8001118 - } else { - //CWBeep(morse_power, morse_unit_ms); - HAL_Delay(morse_unit_ms * 3); - 8001108: 4b09 ldr r3, [pc, #36] ; (8001130 ) - 800110a: 681a ldr r2, [r3, #0] - 800110c: 4613 mov r3, r2 - 800110e: 005b lsls r3, r3, #1 - 8001110: 4413 add r3, r2 - 8001112: 4618 mov r0, r3 - 8001114: f000 fbcc bl 80018b0 - for (uint8_t i = 0; i < len; i++) { - 8001118: 7bfb ldrb r3, [r7, #15] - 800111a: 3301 adds r3, #1 - 800111c: 73fb strb r3, [r7, #15] - 800111e: 7bfa ldrb r2, [r7, #15] - 8001120: 78fb ldrb r3, [r7, #3] - 8001122: 429a cmp r2, r3 - 8001124: d3db bcc.n 80010de - } - } -} - 8001126: bf00 nop - 8001128: bf00 nop - 800112a: 3710 adds r7, #16 - 800112c: 46bd mov sp, r7 - 800112e: bd80 pop {r7, pc} - 8001130: 20000000 .word 0x20000000 - 8001134: 00000000 .word 0x00000000 - -08001138
: + 8000ca6: af00 add r7, sp, #0 + HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_SET); + 8000ca8: 2201 movs r2, #1 + 8000caa: f44f 7100 mov.w r1, #512 ; 0x200 + 8000cae: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 8000cb2: f001 fa6f bl 8002194 +} + 8000cb6: bf00 nop + 8000cb8: bd80 pop {r7, pc} + +08000cba : +void LED_off() { + 8000cba: b580 push {r7, lr} + 8000cbc: af00 add r7, sp, #0 + HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET); + 8000cbe: 2200 movs r2, #0 + 8000cc0: f44f 7100 mov.w r1, #512 ; 0x200 + 8000cc4: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 8000cc8: f001 fa64 bl 8002194 +} + 8000ccc: bf00 nop + 8000cce: bd80 pop {r7, pc} + +08000cd0
: /** * @brief The application entry point. * @retval int */ int main(void) { - 8001138: b580 push {r7, lr} - 800113a: b086 sub sp, #24 - 800113c: af00 add r7, sp, #0 + 8000cd0: b580 push {r7, lr} + 8000cd2: b084 sub sp, #16 + 8000cd4: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); - 800113e: f000 fb41 bl 80017c4 + 8000cd6: f000 fc7b bl 80015d0 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); - 8001142: f000 f87f bl 8001244 + 8000cda: f000 f875 bl 8000dc8 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); - 8001146: f000 f99f bl 8001488 + 8000cde: f000 f995 bl 800100c MX_ADC_Init(); - 800114a: f000 f8cf bl 80012ec + 8000ce2: f000 f8c5 bl 8000e70 MX_SUBGHZ_Init(); - 800114e: f000 f93d bl 80013cc + 8000ce6: f000 f933 bl 8000f50 MX_USART2_UART_Init(); - 8001152: f000 f94d bl 80013f0 + 8000cea: f000 f943 bl 8000f74 MX_CRC_Init(); - 8001156: f000 f917 bl 8001388 + 8000cee: f000 f90d bl 8000f0c /* USER CODE BEGIN 2 */ //EE_Status ee_status = EE_OK; - - HAL_Delay(1000); // initial start - 800115a: f44f 707a mov.w r0, #1000 ; 0x3e8 - 800115e: f000 fba7 bl 80018b0 + HAL_Delay(6000); // initial start + 8000cf2: f241 7070 movw r0, #6000 ; 0x1770 + 8000cf6: f000 fce1 bl 80016bc SetStandbyXOSC(); - 8001162: f7ff fd9f bl 8000ca4 + 8000cfa: f000 f9cf bl 800109c HAL_Delay(1); - 8001166: 2001 movs r0, #1 - 8001168: f000 fba2 bl 80018b0 + 8000cfe: 2001 movs r0, #1 + 8000d00: f000 fcdc bl 80016bc SetPacketTypeLora(); - 800116c: f7ff fdae bl 8000ccc + 8000d04: f000 f9de bl 80010c4 HAL_Delay(1); - 8001170: 2001 movs r0, #1 - 8001172: f000 fb9d bl 80018b0 - //SetPaLowPower(); - SetPa22dB(); - 8001176: f7ff fe0d bl 8000d94 + 8000d08: 2001 movs r0, #1 + 8000d0a: f000 fcd7 bl 80016bc + + //SetPaLowPower(); // For powers up to 14 dBm + SetPa22dB(); // Uncomment for powers up to 22 dBm + 8000d0e: f000 fa3d bl 800118c HAL_Delay(1); - 800117a: 2001 movs r0, #1 - 800117c: f000 fb98 bl 80018b0 + 8000d12: 2001 movs r0, #1 + 8000d14: f000 fcd2 bl 80016bc SetTxPower(-9); - 8001180: f06f 0008 mvn.w r0, #8 - 8001184: f7ff fe20 bl 8000dc8 + 8000d18: f06f 0008 mvn.w r0, #8 + 8000d1c: f000 fa50 bl 80011c0 HAL_Delay(1); - 8001188: 2001 movs r0, #1 - 800118a: f000 fb91 bl 80018b0 + 8000d20: 2001 movs r0, #1 + 8000d22: f000 fccb bl 80016bc SetPacketTypeFSK(); - 800118e: f7ff fdb1 bl 8000cf4 - - SetModulationParamsFSK(2000, 0x09, 0x1E, 3000); - 8001192: f640 33b8 movw r3, #3000 ; 0xbb8 - 8001196: 221e movs r2, #30 - 8001198: 2109 movs r1, #9 - 800119a: f44f 60fa mov.w r0, #2000 ; 0x7d0 - 800119e: f7ff fe53 bl 8000e48 - - double center_freq = 446.14375; - 80011a2: a325 add r3, pc, #148 ; (adr r3, 8001238 ) - 80011a4: e9d3 2300 ldrd r2, r3, [r3] - 80011a8: e9c7 2304 strd r2, r3, [r7, #16] - - SetRfFreq(ComputeRfFreq(center_freq)); - 80011ac: e9d7 0104 ldrd r0, r1, [r7, #16] - 80011b0: f7ff fdb2 bl 8000d18 - 80011b4: 4603 mov r3, r0 - 80011b6: 4618 mov r0, r3 - 80011b8: f7ff fdc8 bl 8000d4c - - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ + 8000d26: f000 f9e1 bl 80010ec + + SetModulationParamsFSK(2000, 0x09, 0x1E, 2500); + 8000d2a: f640 13c4 movw r3, #2500 ; 0x9c4 + 8000d2e: 221e movs r2, #30 + 8000d30: 2109 movs r1, #9 + 8000d32: f44f 60fa mov.w r0, #2000 ; 0x7d0 + 8000d36: f000 fa6f bl 8001218 + + // Frequency setting in MHz + double center_freq = PMR446[13-1] ;//434.700; + 8000d3a: a31f add r3, pc, #124 ; (adr r3, 8000db8 ) + 8000d3c: e9d3 2300 ldrd r2, r3, [r3] + 8000d40: e9c7 2302 strd r2, r3, [r7, #8] + //double center_freq = 223.010; + double freq_correction = 0.99999539941; // Try trimming caps + 8000d44: a31e add r3, pc, #120 ; (adr r3, 8000dc0 ) + 8000d46: e9d3 2300 ldrd r2, r3, [r3] + 8000d4a: e9c7 2300 strd r2, r3, [r7] + + SetRfFreq(ComputeRfFreq(center_freq * freq_correction)); + 8000d4e: e9d7 2300 ldrd r2, r3, [r7] + 8000d52: e9d7 0102 ldrd r0, r1, [r7, #8] + 8000d56: f7ff fbcb bl 80004f0 <__aeabi_dmul> + 8000d5a: 4602 mov r2, r0 + 8000d5c: 460b mov r3, r1 + 8000d5e: 4610 mov r0, r2 + 8000d60: 4619 mov r1, r3 + 8000d62: f000 f9d5 bl 8001110 + 8000d66: 4603 mov r3, r0 + 8000d68: 4618 mov r0, r3 + 8000d6a: f000 f9eb bl 8001144 + HAL_Delay(1000); + }*/ + while (1) { - HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_SET); - 80011bc: 2201 movs r2, #1 - 80011be: f44f 7100 mov.w r1, #512 ; 0x200 - 80011c2: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 - 80011c6: f001 f8df bl 8002388 + LED_on(); + 8000d6e: f7ff ff99 bl 8000ca4 FSKBeep(-9, 500, 200); - 80011ca: 22c8 movs r2, #200 ; 0xc8 - 80011cc: f44f 71fa mov.w r1, #500 ; 0x1f4 - 80011d0: f06f 0008 mvn.w r0, #8 - 80011d4: f7ff fe96 bl 8000f04 + 8000d72: 22c8 movs r2, #200 ; 0xc8 + 8000d74: f44f 71fa mov.w r1, #500 ; 0x1f4 + 8000d78: f06f 0008 mvn.w r0, #8 + 8000d7c: f000 faaa bl 80012d4 HAL_Delay(50); - 80011d8: 2032 movs r0, #50 ; 0x32 - 80011da: f000 fb69 bl 80018b0 + 8000d80: 2032 movs r0, #50 ; 0x32 + 8000d82: f000 fc9b bl 80016bc FSKBeep(2, 750, 200); - 80011de: 22c8 movs r2, #200 ; 0xc8 - 80011e0: f240 21ee movw r1, #750 ; 0x2ee - 80011e4: 2002 movs r0, #2 - 80011e6: f7ff fe8d bl 8000f04 + 8000d86: 22c8 movs r2, #200 ; 0xc8 + 8000d88: f240 21ee movw r1, #750 ; 0x2ee + 8000d8c: 2002 movs r0, #2 + 8000d8e: f000 faa1 bl 80012d4 HAL_Delay(50); - 80011ea: 2032 movs r0, #50 ; 0x32 - 80011ec: f000 fb60 bl 80018b0 - - FSKBeep(10, 1000, 200); - 80011f0: 22c8 movs r2, #200 ; 0xc8 - 80011f2: f44f 717a mov.w r1, #1000 ; 0x3e8 - 80011f6: 200a movs r0, #10 - 80011f8: f7ff fe84 bl 8000f04 + 8000d92: 2032 movs r0, #50 ; 0x32 + 8000d94: f000 fc92 bl 80016bc + + FSKBeep(14, 1000, 200); + 8000d98: 22c8 movs r2, #200 ; 0xc8 + 8000d9a: f44f 717a mov.w r1, #1000 ; 0x3e8 + 8000d9e: 200e movs r0, #14 + 8000da0: f000 fa98 bl 80012d4 HAL_Delay(50); - 80011fc: 2032 movs r0, #50 ; 0x32 - 80011fe: f000 fb57 bl 80018b0 - - HAL_Delay(1000); - 8001202: f44f 707a mov.w r0, #1000 ; 0x3e8 - 8001206: f000 fb53 bl 80018b0 - uint8_t callsign[] = "CALLSIGN"; - 800120a: 4a0d ldr r2, [pc, #52] ; (8001240 ) - 800120c: 1d3b adds r3, r7, #4 - 800120e: ca07 ldmia r2, {r0, r1, r2} - 8001210: c303 stmia r3!, {r0, r1} - 8001212: 701a strb r2, [r3, #0] - play_morse_word(callsign, sizeof(callsign)-1, false); - 8001214: 1d3b adds r3, r7, #4 - 8001216: 2200 movs r2, #0 - 8001218: 2108 movs r1, #8 - 800121a: 4618 mov r0, r3 - 800121c: f7ff ff54 bl 80010c8 - - HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET); - 8001220: 2200 movs r2, #0 - 8001222: f44f 7100 mov.w r1, #512 ; 0x200 - 8001226: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 - 800122a: f001 f8ad bl 8002388 - - HAL_Delay(3000); - 800122e: f640 30b8 movw r0, #3000 ; 0xbb8 - 8001232: f000 fb3d bl 80018b0 - { - 8001236: e7c1 b.n 80011bc - 8001238: cccccccd .word 0xcccccccd - 800123c: 407be24c .word 0x407be24c - 8001240: 08004990 .word 0x08004990 - -08001244 : + 8000da4: 2032 movs r0, #50 ; 0x32 + 8000da6: f000 fc89 bl 80016bc + //HAL_Delay(1000); + //uint8_t callsign[] = "HI"; + //play_morse_word(callsign, sizeof(callsign)-1, false); + + + LED_off(); + 8000daa: f7ff ff86 bl 8000cba + + HAL_Delay(4000); + 8000dae: f44f 607a mov.w r0, #4000 ; 0xfa0 + 8000db2: f000 fc83 bl 80016bc + LED_on(); + 8000db6: e7da b.n 8000d6e + 8000db8: 00000000 .word 0x00000000 + 8000dbc: 407be280 .word 0x407be280 + 8000dc0: 5a13b99d .word 0x5a13b99d + 8000dc4: 3feffff6 .word 0x3feffff6 + +08000dc8 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { - 8001244: b580 push {r7, lr} - 8001246: b09a sub sp, #104 ; 0x68 - 8001248: af00 add r7, sp, #0 + 8000dc8: b580 push {r7, lr} + 8000dca: b09a sub sp, #104 ; 0x68 + 8000dcc: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - 800124a: f107 0320 add.w r3, r7, #32 - 800124e: 2248 movs r2, #72 ; 0x48 - 8001250: 2100 movs r1, #0 - 8001252: 4618 mov r0, r3 - 8001254: f003 fb80 bl 8004958 + 8000dce: f107 0320 add.w r3, r7, #32 + 8000dd2: 2248 movs r2, #72 ; 0x48 + 8000dd4: 2100 movs r1, #0 + 8000dd6: 4618 mov r0, r3 + 8000dd8: f003 fcc4 bl 8004764 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - 8001258: f107 0308 add.w r3, r7, #8 - 800125c: 2200 movs r2, #0 - 800125e: 601a str r2, [r3, #0] - 8001260: 605a str r2, [r3, #4] - 8001262: 609a str r2, [r3, #8] - 8001264: 60da str r2, [r3, #12] - 8001266: 611a str r2, [r3, #16] - 8001268: 615a str r2, [r3, #20] + 8000ddc: f107 0308 add.w r3, r7, #8 + 8000de0: 2200 movs r2, #0 + 8000de2: 601a str r2, [r3, #0] + 8000de4: 605a str r2, [r3, #4] + 8000de6: 609a str r2, [r3, #8] + 8000de8: 60da str r2, [r3, #12] + 8000dea: 611a str r2, [r3, #16] + 8000dec: 615a str r2, [r3, #20] /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); - 800126a: 4b1f ldr r3, [pc, #124] ; (80012e8 ) - 800126c: 681b ldr r3, [r3, #0] - 800126e: f423 63c0 bic.w r3, r3, #1536 ; 0x600 - 8001272: 4a1d ldr r2, [pc, #116] ; (80012e8 ) - 8001274: f443 6380 orr.w r3, r3, #1024 ; 0x400 - 8001278: 6013 str r3, [r2, #0] - 800127a: 4b1b ldr r3, [pc, #108] ; (80012e8 ) - 800127c: 681b ldr r3, [r3, #0] - 800127e: f403 63c0 and.w r3, r3, #1536 ; 0x600 - 8001282: 607b str r3, [r7, #4] - 8001284: 687b ldr r3, [r7, #4] + 8000dee: 4b1f ldr r3, [pc, #124] ; (8000e6c ) + 8000df0: 681b ldr r3, [r3, #0] + 8000df2: f423 63c0 bic.w r3, r3, #1536 ; 0x600 + 8000df6: 4a1d ldr r2, [pc, #116] ; (8000e6c ) + 8000df8: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 8000dfc: 6013 str r3, [r2, #0] + 8000dfe: 4b1b ldr r3, [pc, #108] ; (8000e6c ) + 8000e00: 681b ldr r3, [r3, #0] + 8000e02: f403 63c0 and.w r3, r3, #1536 ; 0x600 + 8000e06: 607b str r3, [r7, #4] + 8000e08: 687b ldr r3, [r7, #4] /** Initializes the CPU, AHB and APB buses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - 8001286: 2301 movs r3, #1 - 8001288: 623b str r3, [r7, #32] + 8000e0a: 2301 movs r3, #1 + 8000e0c: 623b str r3, [r7, #32] RCC_OscInitStruct.HSEState = RCC_HSE_ON; - 800128a: f44f 3380 mov.w r3, #65536 ; 0x10000 - 800128e: 627b str r3, [r7, #36] ; 0x24 + 8000e0e: f44f 3380 mov.w r3, #65536 ; 0x10000 + 8000e12: 627b str r3, [r7, #36] ; 0x24 RCC_OscInitStruct.HSEDiv = RCC_HSE_DIV2; - 8001290: f44f 1380 mov.w r3, #1048576 ; 0x100000 - 8001294: 62bb str r3, [r7, #40] ; 0x28 + 8000e14: f44f 1380 mov.w r3, #1048576 ; 0x100000 + 8000e18: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - 8001296: 2300 movs r3, #0 - 8001298: 64fb str r3, [r7, #76] ; 0x4c + 8000e1a: 2300 movs r3, #0 + 8000e1c: 64fb str r3, [r7, #76] ; 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - 800129a: f107 0320 add.w r3, r7, #32 - 800129e: 4618 mov r0, r3 - 80012a0: f001 fb34 bl 800290c - 80012a4: 4603 mov r3, r0 - 80012a6: 2b00 cmp r3, #0 - 80012a8: d001 beq.n 80012ae + 8000e1e: f107 0320 add.w r3, r7, #32 + 8000e22: 4618 mov r0, r3 + 8000e24: f001 fc78 bl 8002718 + 8000e28: 4603 mov r3, r0 + 8000e2a: 2b00 cmp r3, #0 + 8000e2c: d001 beq.n 8000e32 { Error_Handler(); - 80012aa: f000 f935 bl 8001518 + 8000e2e: f000 fa79 bl 8001324 } /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK3|RCC_CLOCKTYPE_HCLK - 80012ae: 234f movs r3, #79 ; 0x4f - 80012b0: 60bb str r3, [r7, #8] + 8000e32: 234f movs r3, #79 ; 0x4f + 8000e34: 60bb str r3, [r7, #8] |RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 |RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; - 80012b2: 2302 movs r3, #2 - 80012b4: 60fb str r3, [r7, #12] + 8000e36: 2302 movs r3, #2 + 8000e38: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV16; - 80012b6: 23b0 movs r3, #176 ; 0xb0 - 80012b8: 613b str r3, [r7, #16] + 8000e3a: 23b0 movs r3, #176 ; 0xb0 + 8000e3c: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - 80012ba: 2300 movs r3, #0 - 80012bc: 617b str r3, [r7, #20] + 8000e3e: 2300 movs r3, #0 + 8000e40: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - 80012be: 2300 movs r3, #0 - 80012c0: 61bb str r3, [r7, #24] + 8000e42: 2300 movs r3, #0 + 8000e44: 61bb str r3, [r7, #24] RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV16; - 80012c2: 23b0 movs r3, #176 ; 0xb0 - 80012c4: 61fb str r3, [r7, #28] + 8000e46: 23b0 movs r3, #176 ; 0xb0 + 8000e48: 61fb str r3, [r7, #28] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) - 80012c6: f107 0308 add.w r3, r7, #8 - 80012ca: 2100 movs r1, #0 - 80012cc: 4618 mov r0, r3 - 80012ce: f001 fe9f bl 8003010 - 80012d2: 4603 mov r3, r0 - 80012d4: 2b00 cmp r3, #0 - 80012d6: d001 beq.n 80012dc + 8000e4a: f107 0308 add.w r3, r7, #8 + 8000e4e: 2100 movs r1, #0 + 8000e50: 4618 mov r0, r3 + 8000e52: f001 ffe3 bl 8002e1c + 8000e56: 4603 mov r3, r0 + 8000e58: 2b00 cmp r3, #0 + 8000e5a: d001 beq.n 8000e60 { Error_Handler(); - 80012d8: f000 f91e bl 8001518 + 8000e5c: f000 fa62 bl 8001324 } /** Enable the HSE Prescaler */ __HAL_RCC_HSE_DIV2_ENABLE(); - 80012dc: f7ff fcbc bl 8000c58 + 8000e60: f7ff fefa bl 8000c58 } - 80012e0: bf00 nop - 80012e2: 3768 adds r7, #104 ; 0x68 - 80012e4: 46bd mov sp, r7 - 80012e6: bd80 pop {r7, pc} - 80012e8: 58000400 .word 0x58000400 + 8000e64: bf00 nop + 8000e66: 3768 adds r7, #104 ; 0x68 + 8000e68: 46bd mov sp, r7 + 8000e6a: bd80 pop {r7, pc} + 8000e6c: 58000400 .word 0x58000400 -080012ec : +08000e70 : * @brief ADC Initialization Function * @param None * @retval None */ static void MX_ADC_Init(void) { - 80012ec: b580 push {r7, lr} - 80012ee: af00 add r7, sp, #0 + 8000e70: b580 push {r7, lr} + 8000e72: af00 add r7, sp, #0 /* USER CODE END ADC_Init 1 */ /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) */ hadc.Instance = ADC; - 80012f0: 4b23 ldr r3, [pc, #140] ; (8001380 ) - 80012f2: 4a24 ldr r2, [pc, #144] ; (8001384 ) - 80012f4: 601a str r2, [r3, #0] + 8000e74: 4b23 ldr r3, [pc, #140] ; (8000f04 ) + 8000e76: 4a24 ldr r2, [pc, #144] ; (8000f08 ) + 8000e78: 601a str r2, [r3, #0] hadc.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; - 80012f6: 4b22 ldr r3, [pc, #136] ; (8001380 ) - 80012f8: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 - 80012fc: 605a str r2, [r3, #4] + 8000e7a: 4b22 ldr r3, [pc, #136] ; (8000f04 ) + 8000e7c: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 + 8000e80: 605a str r2, [r3, #4] hadc.Init.Resolution = ADC_RESOLUTION_12B; - 80012fe: 4b20 ldr r3, [pc, #128] ; (8001380 ) - 8001300: 2200 movs r2, #0 - 8001302: 609a str r2, [r3, #8] + 8000e82: 4b20 ldr r3, [pc, #128] ; (8000f04 ) + 8000e84: 2200 movs r2, #0 + 8000e86: 609a str r2, [r3, #8] hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT; - 8001304: 4b1e ldr r3, [pc, #120] ; (8001380 ) - 8001306: 2200 movs r2, #0 - 8001308: 60da str r2, [r3, #12] + 8000e88: 4b1e ldr r3, [pc, #120] ; (8000f04 ) + 8000e8a: 2200 movs r2, #0 + 8000e8c: 60da str r2, [r3, #12] hadc.Init.ScanConvMode = ADC_SCAN_DISABLE; - 800130a: 4b1d ldr r3, [pc, #116] ; (8001380 ) - 800130c: 2200 movs r2, #0 - 800130e: 611a str r2, [r3, #16] + 8000e8e: 4b1d ldr r3, [pc, #116] ; (8000f04 ) + 8000e90: 2200 movs r2, #0 + 8000e92: 611a str r2, [r3, #16] hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV; - 8001310: 4b1b ldr r3, [pc, #108] ; (8001380 ) - 8001312: 2204 movs r2, #4 - 8001314: 615a str r2, [r3, #20] + 8000e94: 4b1b ldr r3, [pc, #108] ; (8000f04 ) + 8000e96: 2204 movs r2, #4 + 8000e98: 615a str r2, [r3, #20] hadc.Init.LowPowerAutoWait = DISABLE; - 8001316: 4b1a ldr r3, [pc, #104] ; (8001380 ) - 8001318: 2200 movs r2, #0 - 800131a: 761a strb r2, [r3, #24] + 8000e9a: 4b1a ldr r3, [pc, #104] ; (8000f04 ) + 8000e9c: 2200 movs r2, #0 + 8000e9e: 761a strb r2, [r3, #24] hadc.Init.LowPowerAutoPowerOff = DISABLE; - 800131c: 4b18 ldr r3, [pc, #96] ; (8001380 ) - 800131e: 2200 movs r2, #0 - 8001320: 765a strb r2, [r3, #25] + 8000ea0: 4b18 ldr r3, [pc, #96] ; (8000f04 ) + 8000ea2: 2200 movs r2, #0 + 8000ea4: 765a strb r2, [r3, #25] hadc.Init.ContinuousConvMode = DISABLE; - 8001322: 4b17 ldr r3, [pc, #92] ; (8001380 ) - 8001324: 2200 movs r2, #0 - 8001326: 769a strb r2, [r3, #26] + 8000ea6: 4b17 ldr r3, [pc, #92] ; (8000f04 ) + 8000ea8: 2200 movs r2, #0 + 8000eaa: 769a strb r2, [r3, #26] hadc.Init.NbrOfConversion = 1; - 8001328: 4b15 ldr r3, [pc, #84] ; (8001380 ) - 800132a: 2201 movs r2, #1 - 800132c: 61da str r2, [r3, #28] + 8000eac: 4b15 ldr r3, [pc, #84] ; (8000f04 ) + 8000eae: 2201 movs r2, #1 + 8000eb0: 61da str r2, [r3, #28] hadc.Init.DiscontinuousConvMode = DISABLE; - 800132e: 4b14 ldr r3, [pc, #80] ; (8001380 ) - 8001330: 2200 movs r2, #0 - 8001332: f883 2020 strb.w r2, [r3, #32] + 8000eb2: 4b14 ldr r3, [pc, #80] ; (8000f04 ) + 8000eb4: 2200 movs r2, #0 + 8000eb6: f883 2020 strb.w r2, [r3, #32] hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START; - 8001336: 4b12 ldr r3, [pc, #72] ; (8001380 ) - 8001338: 2200 movs r2, #0 - 800133a: 625a str r2, [r3, #36] ; 0x24 + 8000eba: 4b12 ldr r3, [pc, #72] ; (8000f04 ) + 8000ebc: 2200 movs r2, #0 + 8000ebe: 625a str r2, [r3, #36] ; 0x24 hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - 800133c: 4b10 ldr r3, [pc, #64] ; (8001380 ) - 800133e: 2200 movs r2, #0 - 8001340: 629a str r2, [r3, #40] ; 0x28 + 8000ec0: 4b10 ldr r3, [pc, #64] ; (8000f04 ) + 8000ec2: 2200 movs r2, #0 + 8000ec4: 629a str r2, [r3, #40] ; 0x28 hadc.Init.DMAContinuousRequests = DISABLE; - 8001342: 4b0f ldr r3, [pc, #60] ; (8001380 ) - 8001344: 2200 movs r2, #0 - 8001346: f883 202c strb.w r2, [r3, #44] ; 0x2c + 8000ec6: 4b0f ldr r3, [pc, #60] ; (8000f04 ) + 8000ec8: 2200 movs r2, #0 + 8000eca: f883 202c strb.w r2, [r3, #44] ; 0x2c hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED; - 800134a: 4b0d ldr r3, [pc, #52] ; (8001380 ) - 800134c: 2200 movs r2, #0 - 800134e: 631a str r2, [r3, #48] ; 0x30 + 8000ece: 4b0d ldr r3, [pc, #52] ; (8000f04 ) + 8000ed0: 2200 movs r2, #0 + 8000ed2: 631a str r2, [r3, #48] ; 0x30 hadc.Init.SamplingTimeCommon1 = ADC_SAMPLETIME_1CYCLE_5; - 8001350: 4b0b ldr r3, [pc, #44] ; (8001380 ) - 8001352: 2200 movs r2, #0 - 8001354: 635a str r2, [r3, #52] ; 0x34 + 8000ed4: 4b0b ldr r3, [pc, #44] ; (8000f04 ) + 8000ed6: 2200 movs r2, #0 + 8000ed8: 635a str r2, [r3, #52] ; 0x34 hadc.Init.SamplingTimeCommon2 = ADC_SAMPLETIME_1CYCLE_5; - 8001356: 4b0a ldr r3, [pc, #40] ; (8001380 ) - 8001358: 2200 movs r2, #0 - 800135a: 639a str r2, [r3, #56] ; 0x38 + 8000eda: 4b0a ldr r3, [pc, #40] ; (8000f04 ) + 8000edc: 2200 movs r2, #0 + 8000ede: 639a str r2, [r3, #56] ; 0x38 hadc.Init.OversamplingMode = DISABLE; - 800135c: 4b08 ldr r3, [pc, #32] ; (8001380 ) - 800135e: 2200 movs r2, #0 - 8001360: f883 203c strb.w r2, [r3, #60] ; 0x3c + 8000ee0: 4b08 ldr r3, [pc, #32] ; (8000f04 ) + 8000ee2: 2200 movs r2, #0 + 8000ee4: f883 203c strb.w r2, [r3, #60] ; 0x3c hadc.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH; - 8001364: 4b06 ldr r3, [pc, #24] ; (8001380 ) - 8001366: 2200 movs r2, #0 - 8001368: 64da str r2, [r3, #76] ; 0x4c + 8000ee8: 4b06 ldr r3, [pc, #24] ; (8000f04 ) + 8000eea: 2200 movs r2, #0 + 8000eec: 64da str r2, [r3, #76] ; 0x4c if (HAL_ADC_Init(&hadc) != HAL_OK) - 800136a: 4805 ldr r0, [pc, #20] ; (8001380 ) - 800136c: f000 fb44 bl 80019f8 - 8001370: 4603 mov r3, r0 - 8001372: 2b00 cmp r3, #0 - 8001374: d001 beq.n 800137a + 8000eee: 4805 ldr r0, [pc, #20] ; (8000f04 ) + 8000ef0: f000 fc88 bl 8001804 + 8000ef4: 4603 mov r3, r0 + 8000ef6: 2b00 cmp r3, #0 + 8000ef8: d001 beq.n 8000efe { Error_Handler(); - 8001376: f000 f8cf bl 8001518 + 8000efa: f000 fa13 bl 8001324 } /* USER CODE BEGIN ADC_Init 2 */ /* USER CODE END ADC_Init 2 */ } - 800137a: bf00 nop - 800137c: bd80 pop {r7, pc} - 800137e: bf00 nop - 8001380: 20000030 .word 0x20000030 - 8001384: 40012400 .word 0x40012400 + 8000efe: bf00 nop + 8000f00: bd80 pop {r7, pc} + 8000f02: bf00 nop + 8000f04: 20000028 .word 0x20000028 + 8000f08: 40012400 .word 0x40012400 -08001388 : +08000f0c : * @brief CRC Initialization Function * @param None * @retval None */ static void MX_CRC_Init(void) { - 8001388: b580 push {r7, lr} - 800138a: af00 add r7, sp, #0 + 8000f0c: b580 push {r7, lr} + 8000f0e: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; - 800138c: 4b0d ldr r3, [pc, #52] ; (80013c4 ) - 800138e: 4a0e ldr r2, [pc, #56] ; (80013c8 ) - 8001390: 601a str r2, [r3, #0] + 8000f10: 4b0d ldr r3, [pc, #52] ; (8000f48 ) + 8000f12: 4a0e ldr r2, [pc, #56] ; (8000f4c ) + 8000f14: 601a str r2, [r3, #0] hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE; - 8001392: 4b0c ldr r3, [pc, #48] ; (80013c4 ) - 8001394: 2200 movs r2, #0 - 8001396: 711a strb r2, [r3, #4] + 8000f16: 4b0c ldr r3, [pc, #48] ; (8000f48 ) + 8000f18: 2200 movs r2, #0 + 8000f1a: 711a strb r2, [r3, #4] hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE; - 8001398: 4b0a ldr r3, [pc, #40] ; (80013c4 ) - 800139a: 2200 movs r2, #0 - 800139c: 715a strb r2, [r3, #5] + 8000f1c: 4b0a ldr r3, [pc, #40] ; (8000f48 ) + 8000f1e: 2200 movs r2, #0 + 8000f20: 715a strb r2, [r3, #5] hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE; - 800139e: 4b09 ldr r3, [pc, #36] ; (80013c4 ) - 80013a0: 2200 movs r2, #0 - 80013a2: 615a str r2, [r3, #20] + 8000f22: 4b09 ldr r3, [pc, #36] ; (8000f48 ) + 8000f24: 2200 movs r2, #0 + 8000f26: 615a str r2, [r3, #20] hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE; - 80013a4: 4b07 ldr r3, [pc, #28] ; (80013c4 ) - 80013a6: 2200 movs r2, #0 - 80013a8: 619a str r2, [r3, #24] + 8000f28: 4b07 ldr r3, [pc, #28] ; (8000f48 ) + 8000f2a: 2200 movs r2, #0 + 8000f2c: 619a str r2, [r3, #24] hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; - 80013aa: 4b06 ldr r3, [pc, #24] ; (80013c4 ) - 80013ac: 2201 movs r2, #1 - 80013ae: 621a str r2, [r3, #32] + 8000f2e: 4b06 ldr r3, [pc, #24] ; (8000f48 ) + 8000f30: 2201 movs r2, #1 + 8000f32: 621a str r2, [r3, #32] if (HAL_CRC_Init(&hcrc) != HAL_OK) - 80013b0: 4804 ldr r0, [pc, #16] ; (80013c4 ) - 80013b2: f000 fd97 bl 8001ee4 - 80013b6: 4603 mov r3, r0 - 80013b8: 2b00 cmp r3, #0 - 80013ba: d001 beq.n 80013c0 + 8000f34: 4804 ldr r0, [pc, #16] ; (8000f48 ) + 8000f36: f000 fedb bl 8001cf0 + 8000f3a: 4603 mov r3, r0 + 8000f3c: 2b00 cmp r3, #0 + 8000f3e: d001 beq.n 8000f44 { Error_Handler(); - 80013bc: f000 f8ac bl 8001518 + 8000f40: f000 f9f0 bl 8001324 } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } - 80013c0: bf00 nop - 80013c2: bd80 pop {r7, pc} - 80013c4: 20000094 .word 0x20000094 - 80013c8: 40023000 .word 0x40023000 + 8000f44: bf00 nop + 8000f46: bd80 pop {r7, pc} + 8000f48: 2000008c .word 0x2000008c + 8000f4c: 40023000 .word 0x40023000 -080013cc : +08000f50 : * @brief SUBGHZ Initialization Function * @param None * @retval None */ static void MX_SUBGHZ_Init(void) { - 80013cc: b580 push {r7, lr} - 80013ce: af00 add r7, sp, #0 + 8000f50: b580 push {r7, lr} + 8000f52: af00 add r7, sp, #0 /* USER CODE END SUBGHZ_Init 0 */ /* USER CODE BEGIN SUBGHZ_Init 1 */ /* USER CODE END SUBGHZ_Init 1 */ hsubghz.Init.BaudratePrescaler = SUBGHZSPI_BAUDRATEPRESCALER_8; - 80013d0: 4b06 ldr r3, [pc, #24] ; (80013ec ) - 80013d2: 2210 movs r2, #16 - 80013d4: 601a str r2, [r3, #0] + 8000f54: 4b06 ldr r3, [pc, #24] ; (8000f70 ) + 8000f56: 2210 movs r2, #16 + 8000f58: 601a str r2, [r3, #0] if (HAL_SUBGHZ_Init(&hsubghz) != HAL_OK) - 80013d6: 4805 ldr r0, [pc, #20] ; (80013ec ) - 80013d8: f002 fb70 bl 8003abc - 80013dc: 4603 mov r3, r0 - 80013de: 2b00 cmp r3, #0 - 80013e0: d001 beq.n 80013e6 + 8000f5a: 4805 ldr r0, [pc, #20] ; (8000f70 ) + 8000f5c: f002 fcb4 bl 80038c8 + 8000f60: 4603 mov r3, r0 + 8000f62: 2b00 cmp r3, #0 + 8000f64: d001 beq.n 8000f6a { Error_Handler(); - 80013e2: f000 f899 bl 8001518 + 8000f66: f000 f9dd bl 8001324 } /* USER CODE BEGIN SUBGHZ_Init 2 */ /* USER CODE END SUBGHZ_Init 2 */ } - 80013e6: bf00 nop - 80013e8: bd80 pop {r7, pc} - 80013ea: bf00 nop - 80013ec: 200000b8 .word 0x200000b8 + 8000f6a: bf00 nop + 8000f6c: bd80 pop {r7, pc} + 8000f6e: bf00 nop + 8000f70: 200000b0 .word 0x200000b0 -080013f0 : +08000f74 : * @brief USART2 Initialization Function * @param None * @retval None */ static void MX_USART2_UART_Init(void) { - 80013f0: b580 push {r7, lr} - 80013f2: af00 add r7, sp, #0 + 8000f74: b580 push {r7, lr} + 8000f76: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; - 80013f4: 4b22 ldr r3, [pc, #136] ; (8001480 ) - 80013f6: 4a23 ldr r2, [pc, #140] ; (8001484 ) - 80013f8: 601a str r2, [r3, #0] + 8000f78: 4b22 ldr r3, [pc, #136] ; (8001004 ) + 8000f7a: 4a23 ldr r2, [pc, #140] ; (8001008 ) + 8000f7c: 601a str r2, [r3, #0] huart2.Init.BaudRate = 9600; - 80013fa: 4b21 ldr r3, [pc, #132] ; (8001480 ) - 80013fc: f44f 5216 mov.w r2, #9600 ; 0x2580 - 8001400: 605a str r2, [r3, #4] + 8000f7e: 4b21 ldr r3, [pc, #132] ; (8001004 ) + 8000f80: f44f 5216 mov.w r2, #9600 ; 0x2580 + 8000f84: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; - 8001402: 4b1f ldr r3, [pc, #124] ; (8001480 ) - 8001404: 2200 movs r2, #0 - 8001406: 609a str r2, [r3, #8] + 8000f86: 4b1f ldr r3, [pc, #124] ; (8001004 ) + 8000f88: 2200 movs r2, #0 + 8000f8a: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; - 8001408: 4b1d ldr r3, [pc, #116] ; (8001480 ) - 800140a: 2200 movs r2, #0 - 800140c: 60da str r2, [r3, #12] + 8000f8c: 4b1d ldr r3, [pc, #116] ; (8001004 ) + 8000f8e: 2200 movs r2, #0 + 8000f90: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; - 800140e: 4b1c ldr r3, [pc, #112] ; (8001480 ) - 8001410: 2200 movs r2, #0 - 8001412: 611a str r2, [r3, #16] + 8000f92: 4b1c ldr r3, [pc, #112] ; (8001004 ) + 8000f94: 2200 movs r2, #0 + 8000f96: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; - 8001414: 4b1a ldr r3, [pc, #104] ; (8001480 ) - 8001416: 220c movs r2, #12 - 8001418: 615a str r2, [r3, #20] + 8000f98: 4b1a ldr r3, [pc, #104] ; (8001004 ) + 8000f9a: 220c movs r2, #12 + 8000f9c: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; - 800141a: 4b19 ldr r3, [pc, #100] ; (8001480 ) - 800141c: 2200 movs r2, #0 - 800141e: 619a str r2, [r3, #24] + 8000f9e: 4b19 ldr r3, [pc, #100] ; (8001004 ) + 8000fa0: 2200 movs r2, #0 + 8000fa2: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; - 8001420: 4b17 ldr r3, [pc, #92] ; (8001480 ) - 8001422: 2200 movs r2, #0 - 8001424: 61da str r2, [r3, #28] + 8000fa4: 4b17 ldr r3, [pc, #92] ; (8001004 ) + 8000fa6: 2200 movs r2, #0 + 8000fa8: 61da str r2, [r3, #28] huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - 8001426: 4b16 ldr r3, [pc, #88] ; (8001480 ) - 8001428: 2200 movs r2, #0 - 800142a: 621a str r2, [r3, #32] + 8000faa: 4b16 ldr r3, [pc, #88] ; (8001004 ) + 8000fac: 2200 movs r2, #0 + 8000fae: 621a str r2, [r3, #32] huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1; - 800142c: 4b14 ldr r3, [pc, #80] ; (8001480 ) - 800142e: 2200 movs r2, #0 - 8001430: 625a str r2, [r3, #36] ; 0x24 + 8000fb0: 4b14 ldr r3, [pc, #80] ; (8001004 ) + 8000fb2: 2200 movs r2, #0 + 8000fb4: 625a str r2, [r3, #36] ; 0x24 huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - 8001432: 4b13 ldr r3, [pc, #76] ; (8001480 ) - 8001434: 2200 movs r2, #0 - 8001436: 629a str r2, [r3, #40] ; 0x28 + 8000fb6: 4b13 ldr r3, [pc, #76] ; (8001004 ) + 8000fb8: 2200 movs r2, #0 + 8000fba: 629a str r2, [r3, #40] ; 0x28 if (HAL_UART_Init(&huart2) != HAL_OK) - 8001438: 4811 ldr r0, [pc, #68] ; (8001480 ) - 800143a: f002 fcec bl 8003e16 - 800143e: 4603 mov r3, r0 - 8001440: 2b00 cmp r3, #0 - 8001442: d001 beq.n 8001448 + 8000fbc: 4811 ldr r0, [pc, #68] ; (8001004 ) + 8000fbe: f002 fe30 bl 8003c22 + 8000fc2: 4603 mov r3, r0 + 8000fc4: 2b00 cmp r3, #0 + 8000fc6: d001 beq.n 8000fcc { Error_Handler(); - 8001444: f000 f868 bl 8001518 + 8000fc8: f000 f9ac bl 8001324 } if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) - 8001448: 2100 movs r1, #0 - 800144a: 480d ldr r0, [pc, #52] ; (8001480 ) - 800144c: f003 f997 bl 800477e - 8001450: 4603 mov r3, r0 - 8001452: 2b00 cmp r3, #0 - 8001454: d001 beq.n 800145a + 8000fcc: 2100 movs r1, #0 + 8000fce: 480d ldr r0, [pc, #52] ; (8001004 ) + 8000fd0: f003 fadb bl 800458a + 8000fd4: 4603 mov r3, r0 + 8000fd6: 2b00 cmp r3, #0 + 8000fd8: d001 beq.n 8000fde { Error_Handler(); - 8001456: f000 f85f bl 8001518 + 8000fda: f000 f9a3 bl 8001324 } if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) - 800145a: 2100 movs r1, #0 - 800145c: 4808 ldr r0, [pc, #32] ; (8001480 ) - 800145e: f003 f9cc bl 80047fa - 8001462: 4603 mov r3, r0 - 8001464: 2b00 cmp r3, #0 - 8001466: d001 beq.n 800146c + 8000fde: 2100 movs r1, #0 + 8000fe0: 4808 ldr r0, [pc, #32] ; (8001004 ) + 8000fe2: f003 fb10 bl 8004606 + 8000fe6: 4603 mov r3, r0 + 8000fe8: 2b00 cmp r3, #0 + 8000fea: d001 beq.n 8000ff0 { Error_Handler(); - 8001468: f000 f856 bl 8001518 + 8000fec: f000 f99a bl 8001324 } if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK) - 800146c: 4804 ldr r0, [pc, #16] ; (8001480 ) - 800146e: f003 f94e bl 800470e - 8001472: 4603 mov r3, r0 - 8001474: 2b00 cmp r3, #0 - 8001476: d001 beq.n 800147c + 8000ff0: 4804 ldr r0, [pc, #16] ; (8001004 ) + 8000ff2: f003 fa92 bl 800451a + 8000ff6: 4603 mov r3, r0 + 8000ff8: 2b00 cmp r3, #0 + 8000ffa: d001 beq.n 8001000 { Error_Handler(); - 8001478: f000 f84e bl 8001518 + 8000ffc: f000 f992 bl 8001324 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } - 800147c: bf00 nop - 800147e: bd80 pop {r7, pc} - 8001480: 200000c4 .word 0x200000c4 - 8001484: 40004400 .word 0x40004400 + 8001000: bf00 nop + 8001002: bd80 pop {r7, pc} + 8001004: 200000bc .word 0x200000bc + 8001008: 40004400 .word 0x40004400 -08001488 : +0800100c : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { - 8001488: b580 push {r7, lr} - 800148a: b086 sub sp, #24 - 800148c: af00 add r7, sp, #0 + 800100c: b580 push {r7, lr} + 800100e: b086 sub sp, #24 + 8001010: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; - 800148e: 1d3b adds r3, r7, #4 - 8001490: 2200 movs r2, #0 - 8001492: 601a str r2, [r3, #0] - 8001494: 605a str r2, [r3, #4] - 8001496: 609a str r2, [r3, #8] - 8001498: 60da str r2, [r3, #12] - 800149a: 611a str r2, [r3, #16] + 8001012: 1d3b adds r3, r7, #4 + 8001014: 2200 movs r2, #0 + 8001016: 601a str r2, [r3, #0] + 8001018: 605a str r2, [r3, #4] + 800101a: 609a str r2, [r3, #8] + 800101c: 60da str r2, [r3, #12] + 800101e: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOB_CLK_ENABLE(); - 800149c: 2002 movs r0, #2 - 800149e: f7ff fbe9 bl 8000c74 + 8001020: 2002 movs r0, #2 + 8001022: f7ff fe27 bl 8000c74 __HAL_RCC_GPIOA_CLK_ENABLE(); - 80014a2: 2001 movs r0, #1 - 80014a4: f7ff fbe6 bl 8000c74 + 8001026: 2001 movs r0, #1 + 8001028: f7ff fe24 bl 8000c74 __HAL_RCC_GPIOH_CLK_ENABLE(); - 80014a8: 2080 movs r0, #128 ; 0x80 - 80014aa: f7ff fbe3 bl 8000c74 + 800102c: 2080 movs r0, #128 ; 0x80 + 800102e: f7ff fe21 bl 8000c74 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET); - 80014ae: 2200 movs r2, #0 - 80014b0: f44f 7100 mov.w r1, #512 ; 0x200 - 80014b4: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 - 80014b8: f000 ff66 bl 8002388 + 8001032: 2200 movs r2, #0 + 8001034: f44f 7100 mov.w r1, #512 ; 0x200 + 8001038: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 800103c: f001 f8aa bl 8002194 /*Configure GPIO pins : CONF_440_Pin CONF_868_Pin */ GPIO_InitStruct.Pin = CONF_440_Pin|CONF_868_Pin; - 80014bc: 2318 movs r3, #24 - 80014be: 607b str r3, [r7, #4] + 8001040: 2318 movs r3, #24 + 8001042: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - 80014c0: 2300 movs r3, #0 - 80014c2: 60bb str r3, [r7, #8] + 8001044: 2300 movs r3, #0 + 8001046: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80014c4: 2300 movs r3, #0 - 80014c6: 60fb str r3, [r7, #12] + 8001048: 2300 movs r3, #0 + 800104a: 60fb str r3, [r7, #12] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - 80014c8: 1d3b adds r3, r7, #4 - 80014ca: 4619 mov r1, r3 - 80014cc: 4810 ldr r0, [pc, #64] ; (8001510 ) - 80014ce: f000 fdfb bl 80020c8 + 800104c: 1d3b adds r3, r7, #4 + 800104e: 4619 mov r1, r3 + 8001050: 4810 ldr r0, [pc, #64] ; (8001094 ) + 8001052: f000 ff3f bl 8001ed4 /*Configure GPIO pin : LED_Pin */ GPIO_InitStruct.Pin = LED_Pin; - 80014d2: f44f 7300 mov.w r3, #512 ; 0x200 - 80014d6: 607b str r3, [r7, #4] + 8001056: f44f 7300 mov.w r3, #512 ; 0x200 + 800105a: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 80014d8: 2301 movs r3, #1 - 80014da: 60bb str r3, [r7, #8] + 800105c: 2301 movs r3, #1 + 800105e: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80014dc: 2300 movs r3, #0 - 80014de: 60fb str r3, [r7, #12] + 8001060: 2300 movs r3, #0 + 8001062: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 80014e0: 2300 movs r3, #0 - 80014e2: 613b str r3, [r7, #16] + 8001064: 2300 movs r3, #0 + 8001066: 613b str r3, [r7, #16] HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct); - 80014e4: 1d3b adds r3, r7, #4 - 80014e6: 4619 mov r1, r3 - 80014e8: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 - 80014ec: f000 fdec bl 80020c8 + 8001068: 1d3b adds r3, r7, #4 + 800106a: 4619 mov r1, r3 + 800106c: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 8001070: f000 ff30 bl 8001ed4 /*Configure GPIO pin : BOOT_Pin */ GPIO_InitStruct.Pin = BOOT_Pin; - 80014f0: 2308 movs r3, #8 - 80014f2: 607b str r3, [r7, #4] + 8001074: 2308 movs r3, #8 + 8001076: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - 80014f4: 2300 movs r3, #0 - 80014f6: 60bb str r3, [r7, #8] + 8001078: 2300 movs r3, #0 + 800107a: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80014f8: 2300 movs r3, #0 - 80014fa: 60fb str r3, [r7, #12] + 800107c: 2300 movs r3, #0 + 800107e: 60fb str r3, [r7, #12] HAL_GPIO_Init(BOOT_GPIO_Port, &GPIO_InitStruct); - 80014fc: 1d3b adds r3, r7, #4 - 80014fe: 4619 mov r1, r3 - 8001500: 4804 ldr r0, [pc, #16] ; (8001514 ) - 8001502: f000 fde1 bl 80020c8 + 8001080: 1d3b adds r3, r7, #4 + 8001082: 4619 mov r1, r3 + 8001084: 4804 ldr r0, [pc, #16] ; (8001098 ) + 8001086: f000 ff25 bl 8001ed4 + +} + 800108a: bf00 nop + 800108c: 3718 adds r7, #24 + 800108e: 46bd mov sp, r7 + 8001090: bd80 pop {r7, pc} + 8001092: bf00 nop + 8001094: 48000400 .word 0x48000400 + 8001098: 48001c00 .word 0x48001c00 + +0800109c : + +/* USER CODE BEGIN 4 */ +void SetStandbyXOSC() { + 800109c: b580 push {r7, lr} + 800109e: b082 sub sp, #8 + 80010a0: af00 add r7, sp, #0 + uint8_t txbuf[2] = {0x80, 0x01}; + 80010a2: f44f 73c0 mov.w r3, #384 ; 0x180 + 80010a6: 80bb strh r3, [r7, #4] + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); + 80010a8: 7939 ldrb r1, [r7, #4] + 80010aa: 1d3a adds r2, r7, #4 + 80010ac: 3201 adds r2, #1 + 80010ae: 2301 movs r3, #1 + 80010b0: 4803 ldr r0, [pc, #12] ; (80010c0 ) + 80010b2: f002 fc6d bl 8003990 +} + 80010b6: bf00 nop + 80010b8: 3708 adds r7, #8 + 80010ba: 46bd mov sp, r7 + 80010bc: bd80 pop {r7, pc} + 80010be: bf00 nop + 80010c0: 200000b0 .word 0x200000b0 + +080010c4 : + +void SetPacketTypeLora() { + 80010c4: b580 push {r7, lr} + 80010c6: b082 sub sp, #8 + 80010c8: af00 add r7, sp, #0 + uint8_t txbuf[2] = {0x8A, 0x01}; + 80010ca: f44f 73c5 mov.w r3, #394 ; 0x18a + 80010ce: 80bb strh r3, [r7, #4] + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); + 80010d0: 7939 ldrb r1, [r7, #4] + 80010d2: 1d3a adds r2, r7, #4 + 80010d4: 3201 adds r2, #1 + 80010d6: 2301 movs r3, #1 + 80010d8: 4803 ldr r0, [pc, #12] ; (80010e8 ) + 80010da: f002 fc59 bl 8003990 +} + 80010de: bf00 nop + 80010e0: 3708 adds r7, #8 + 80010e2: 46bd mov sp, r7 + 80010e4: bd80 pop {r7, pc} + 80010e6: bf00 nop + 80010e8: 200000b0 .word 0x200000b0 + +080010ec : + +void SetPacketTypeFSK() { + 80010ec: b580 push {r7, lr} + 80010ee: b082 sub sp, #8 + 80010f0: af00 add r7, sp, #0 + uint8_t txbuf[2] = {0x8A, 0x00}; + 80010f2: 238a movs r3, #138 ; 0x8a + 80010f4: 80bb strh r3, [r7, #4] + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); + 80010f6: 7939 ldrb r1, [r7, #4] + 80010f8: 1d3a adds r2, r7, #4 + 80010fa: 3201 adds r2, #1 + 80010fc: 2301 movs r3, #1 + 80010fe: 4803 ldr r0, [pc, #12] ; (800110c ) + 8001100: f002 fc46 bl 8003990 +} + 8001104: bf00 nop + 8001106: 3708 adds r7, #8 + 8001108: 46bd mov sp, r7 + 800110a: bd80 pop {r7, pc} + 800110c: 200000b0 .word 0x200000b0 + +08001110 : + +uint32_t ComputeRfFreq(double frequencyMhz) { + 8001110: b580 push {r7, lr} + 8001112: b082 sub sp, #8 + 8001114: af00 add r7, sp, #0 + 8001116: e9c7 0100 strd r0, r1, [r7] + return (uint32_t)(frequencyMhz * 1048576L); //2^25/(32e6) + 800111a: f04f 0200 mov.w r2, #0 + 800111e: 4b08 ldr r3, [pc, #32] ; (8001140 ) + 8001120: e9d7 0100 ldrd r0, r1, [r7] + 8001124: f7ff f9e4 bl 80004f0 <__aeabi_dmul> + 8001128: 4602 mov r2, r0 + 800112a: 460b mov r3, r1 + 800112c: 4610 mov r0, r2 + 800112e: 4619 mov r1, r3 + 8001130: f7ff fbf0 bl 8000914 <__aeabi_d2uiz> + 8001134: 4603 mov r3, r0 +} + 8001136: 4618 mov r0, r3 + 8001138: 3708 adds r7, #8 + 800113a: 46bd mov sp, r7 + 800113c: bd80 pop {r7, pc} + 800113e: bf00 nop + 8001140: 41300000 .word 0x41300000 + +08001144 : + +void SetRfFreq(uint32_t rfFreq) { + 8001144: b580 push {r7, lr} + 8001146: b084 sub sp, #16 + 8001148: af00 add r7, sp, #0 + 800114a: 6078 str r0, [r7, #4] + uint8_t txbuf[5] = {0x86, (rfFreq & 0xFF000000) >> 24, (rfFreq & 0x00FF0000) >> 16, (rfFreq & 0x0000FF00) >> 8, rfFreq & 0x000000FF}; + 800114c: 2386 movs r3, #134 ; 0x86 + 800114e: 723b strb r3, [r7, #8] + 8001150: 687b ldr r3, [r7, #4] + 8001152: 0e1b lsrs r3, r3, #24 + 8001154: b2db uxtb r3, r3 + 8001156: 727b strb r3, [r7, #9] + 8001158: 687b ldr r3, [r7, #4] + 800115a: 0c1b lsrs r3, r3, #16 + 800115c: b2db uxtb r3, r3 + 800115e: 72bb strb r3, [r7, #10] + 8001160: 687b ldr r3, [r7, #4] + 8001162: 0a1b lsrs r3, r3, #8 + 8001164: b2db uxtb r3, r3 + 8001166: 72fb strb r3, [r7, #11] + 8001168: 687b ldr r3, [r7, #4] + 800116a: b2db uxtb r3, r3 + 800116c: 733b strb r3, [r7, #12] + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); + 800116e: 7a39 ldrb r1, [r7, #8] + 8001170: f107 0208 add.w r2, r7, #8 + 8001174: 3201 adds r2, #1 + 8001176: 2304 movs r3, #4 + 8001178: 4803 ldr r0, [pc, #12] ; (8001188 ) + 800117a: f002 fc09 bl 8003990 +} + 800117e: bf00 nop + 8001180: 3710 adds r7, #16 + 8001182: 46bd mov sp, r7 + 8001184: bd80 pop {r7, pc} + 8001186: bf00 nop + 8001188: 200000b0 .word 0x200000b0 + +0800118c : + // set Pa to 14 dB. + uint8_t txbuf[5] = {0x95, 0x02, 0x02, 0x00, 0x01}; + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); +} + +void SetPa22dB() { + 800118c: b580 push {r7, lr} + 800118e: b082 sub sp, #8 + 8001190: af00 add r7, sp, #0 + // set Pa to the highest 22 dBm + uint8_t txbuf[5] = {0x95, 0x04, 0x07, 0x00, 0x01}; + 8001192: 4a09 ldr r2, [pc, #36] ; (80011b8 ) + 8001194: 463b mov r3, r7 + 8001196: e892 0003 ldmia.w r2, {r0, r1} + 800119a: 6018 str r0, [r3, #0] + 800119c: 3304 adds r3, #4 + 800119e: 7019 strb r1, [r3, #0] + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); + 80011a0: 7839 ldrb r1, [r7, #0] + 80011a2: 463a mov r2, r7 + 80011a4: 3201 adds r2, #1 + 80011a6: 2304 movs r3, #4 + 80011a8: 4804 ldr r0, [pc, #16] ; (80011bc ) + 80011aa: f002 fbf1 bl 8003990 +} + 80011ae: bf00 nop + 80011b0: 3708 adds r7, #8 + 80011b2: 46bd mov sp, r7 + 80011b4: bd80 pop {r7, pc} + 80011b6: bf00 nop + 80011b8: 08004794 .word 0x08004794 + 80011bc: 200000b0 .word 0x200000b0 + +080011c0 : + +void SetTxPower(int8_t powerdBm) { + 80011c0: b580 push {r7, lr} + 80011c2: b084 sub sp, #16 + 80011c4: af00 add r7, sp, #0 + 80011c6: 4603 mov r3, r0 + 80011c8: 71fb strb r3, [r7, #7] + // Between -9 and 22 + uint8_t txbuf[3] = {0x8E, (uint8_t) powerdBm, 0x02}; + 80011ca: 238e movs r3, #142 ; 0x8e + 80011cc: 733b strb r3, [r7, #12] + 80011ce: 79fb ldrb r3, [r7, #7] + 80011d0: 737b strb r3, [r7, #13] + 80011d2: 2302 movs r3, #2 + 80011d4: 73bb strb r3, [r7, #14] + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); + 80011d6: 7b39 ldrb r1, [r7, #12] + 80011d8: f107 020c add.w r2, r7, #12 + 80011dc: 3201 adds r2, #1 + 80011de: 2302 movs r3, #2 + 80011e0: 4803 ldr r0, [pc, #12] ; (80011f0 ) + 80011e2: f002 fbd5 bl 8003990 +} + 80011e6: bf00 nop + 80011e8: 3710 adds r7, #16 + 80011ea: 46bd mov sp, r7 + 80011ec: bd80 pop {r7, pc} + 80011ee: bf00 nop + 80011f0: 200000b0 .word 0x200000b0 + +080011f4 : +void SetContinuousWave() { + uint8_t txbuf[1] = {0xD1}; + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf, 0); +} + +void SetTxInfinitePreamble() { + 80011f4: b580 push {r7, lr} + 80011f6: b082 sub sp, #8 + 80011f8: af00 add r7, sp, #0 + uint8_t txbuf[1] = {0xD2}; + 80011fa: 23d2 movs r3, #210 ; 0xd2 + 80011fc: 713b strb r3, [r7, #4] + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf, 0); + 80011fe: 7939 ldrb r1, [r7, #4] + 8001200: 1d3a adds r2, r7, #4 + 8001202: 2300 movs r3, #0 + 8001204: 4803 ldr r0, [pc, #12] ; (8001214 ) + 8001206: f002 fbc3 bl 8003990 +} + 800120a: bf00 nop + 800120c: 3708 adds r7, #8 + 800120e: 46bd mov sp, r7 + 8001210: bd80 pop {r7, pc} + 8001212: bf00 nop + 8001214: 200000b0 .word 0x200000b0 + +08001218 : +void SetModulationParamsLora(const uint8_t params[4]) { + uint8_t txbuf[5] = {0x8B, params[0], params[1], params[2], params[3]}; + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); +} +void SetModulationParamsFSK(uint32_t bitrate, uint8_t pulseshape, uint8_t bandwidth, uint32_t freq_dev) { + 8001218: b580 push {r7, lr} + 800121a: b08a sub sp, #40 ; 0x28 + 800121c: af00 add r7, sp, #0 + 800121e: 60f8 str r0, [r7, #12] + 8001220: 607b str r3, [r7, #4] + 8001222: 460b mov r3, r1 + 8001224: 72fb strb r3, [r7, #11] + 8001226: 4613 mov r3, r2 + 8001228: 72bb strb r3, [r7, #10] + uint32_t BR = 32 * 32e6 / bitrate; + 800122a: 68f8 ldr r0, [r7, #12] + 800122c: f7ff f8e6 bl 80003fc <__aeabi_ui2d> + 8001230: 4602 mov r2, r0 + 8001232: 460b mov r3, r1 + 8001234: a122 add r1, pc, #136 ; (adr r1, 80012c0 ) + 8001236: e9d1 0100 ldrd r0, r1, [r1] + 800123a: f7ff fa83 bl 8000744 <__aeabi_ddiv> + 800123e: 4602 mov r2, r0 + 8001240: 460b mov r3, r1 + 8001242: 4610 mov r0, r2 + 8001244: 4619 mov r1, r3 + 8001246: f7ff fb65 bl 8000914 <__aeabi_d2uiz> + 800124a: 4603 mov r3, r0 + 800124c: 627b str r3, [r7, #36] ; 0x24 + uint32_t fdev = (uint32_t) (freq_dev * 1.048576L); // 2^25/32e6 = 1.048576 + 800124e: 6878 ldr r0, [r7, #4] + 8001250: f7ff f8d4 bl 80003fc <__aeabi_ui2d> + 8001254: a31c add r3, pc, #112 ; (adr r3, 80012c8 ) + 8001256: e9d3 2300 ldrd r2, r3, [r3] + 800125a: f7ff f949 bl 80004f0 <__aeabi_dmul> + 800125e: 4602 mov r2, r0 + 8001260: 460b mov r3, r1 + 8001262: 4610 mov r0, r2 + 8001264: 4619 mov r1, r3 + 8001266: f7ff fb55 bl 8000914 <__aeabi_d2uiz> + 800126a: 4603 mov r3, r0 + 800126c: 623b str r3, [r7, #32] + uint8_t txbuf[9] = {0x8B, (BR & 0x00FF0000) >> 16, (BR & 0x0000FF00) >> 8, BR & 0x000000FF, pulseshape, bandwidth, (fdev & 0x00FF0000) >> 16, (fdev & 0x0000FF00) >> 8, fdev & 0x000000FF}; + 800126e: 238b movs r3, #139 ; 0x8b + 8001270: 753b strb r3, [r7, #20] + 8001272: 6a7b ldr r3, [r7, #36] ; 0x24 + 8001274: 0c1b lsrs r3, r3, #16 + 8001276: b2db uxtb r3, r3 + 8001278: 757b strb r3, [r7, #21] + 800127a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800127c: 0a1b lsrs r3, r3, #8 + 800127e: b2db uxtb r3, r3 + 8001280: 75bb strb r3, [r7, #22] + 8001282: 6a7b ldr r3, [r7, #36] ; 0x24 + 8001284: b2db uxtb r3, r3 + 8001286: 75fb strb r3, [r7, #23] + 8001288: 7afb ldrb r3, [r7, #11] + 800128a: 763b strb r3, [r7, #24] + 800128c: 7abb ldrb r3, [r7, #10] + 800128e: 767b strb r3, [r7, #25] + 8001290: 6a3b ldr r3, [r7, #32] + 8001292: 0c1b lsrs r3, r3, #16 + 8001294: b2db uxtb r3, r3 + 8001296: 76bb strb r3, [r7, #26] + 8001298: 6a3b ldr r3, [r7, #32] + 800129a: 0a1b lsrs r3, r3, #8 + 800129c: b2db uxtb r3, r3 + 800129e: 76fb strb r3, [r7, #27] + 80012a0: 6a3b ldr r3, [r7, #32] + 80012a2: b2db uxtb r3, r3 + 80012a4: 773b strb r3, [r7, #28] + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); + 80012a6: 7d39 ldrb r1, [r7, #20] + 80012a8: f107 0214 add.w r2, r7, #20 + 80012ac: 3201 adds r2, #1 + 80012ae: 2308 movs r3, #8 + 80012b0: 4807 ldr r0, [pc, #28] ; (80012d0 ) + 80012b2: f002 fb6d bl 8003990 +} + 80012b6: bf00 nop + 80012b8: 3728 adds r7, #40 ; 0x28 + 80012ba: 46bd mov sp, r7 + 80012bc: bd80 pop {r7, pc} + 80012be: bf00 nop + 80012c0: 00000000 .word 0x00000000 + 80012c4: 41ce8480 .word 0x41ce8480 + 80012c8: a0b5ed8d .word 0xa0b5ed8d + 80012cc: 3ff0c6f7 .word 0x3ff0c6f7 + 80012d0: 200000b0 .word 0x200000b0 + +080012d4 : + + HAL_SUBGHZ_ExecSetCmd(&hsubghz, txbuf[0], txbuf+1, sizeof(txbuf)-1); } - 8001506: bf00 nop - 8001508: 3718 adds r7, #24 - 800150a: 46bd mov sp, r7 - 800150c: bd80 pop {r7, pc} - 800150e: bf00 nop - 8001510: 48000400 .word 0x48000400 - 8001514: 48001c00 .word 0x48001c00 -08001518 : + +void FSKBeep(int8_t powerdBm, uint32_t toneHz, uint32_t lengthMs) { + 80012d4: b580 push {r7, lr} + 80012d6: b084 sub sp, #16 + 80012d8: af00 add r7, sp, #0 + 80012da: 4603 mov r3, r0 + 80012dc: 60b9 str r1, [r7, #8] + 80012de: 607a str r2, [r7, #4] + 80012e0: 73fb strb r3, [r7, #15] + // assume in standbyXOSC already. + HAL_Delay(1); + 80012e2: 2001 movs r0, #1 + 80012e4: f000 f9ea bl 80016bc + SetTxPower(powerdBm); + 80012e8: f997 300f ldrsb.w r3, [r7, #15] + 80012ec: 4618 mov r0, r3 + 80012ee: f7ff ff67 bl 80011c0 + SetModulationParamsFSK(toneHz*2, 0x09, 0x1E, 2500); + 80012f2: 68bb ldr r3, [r7, #8] + 80012f4: 0058 lsls r0, r3, #1 + 80012f6: f640 13c4 movw r3, #2500 ; 0x9c4 + 80012fa: 221e movs r2, #30 + 80012fc: 2109 movs r1, #9 + 80012fe: f7ff ff8b bl 8001218 + HAL_Delay(5); + 8001302: 2005 movs r0, #5 + 8001304: f000 f9da bl 80016bc + SetTxInfinitePreamble(); + 8001308: f7ff ff74 bl 80011f4 + HAL_Delay(lengthMs); + 800130c: 6878 ldr r0, [r7, #4] + 800130e: f000 f9d5 bl 80016bc + SetStandbyXOSC(); + 8001312: f7ff fec3 bl 800109c + HAL_Delay(5); + 8001316: 2005 movs r0, #5 + 8001318: f000 f9d0 bl 80016bc +} + 800131c: bf00 nop + 800131e: 3710 adds r7, #16 + 8001320: 46bd mov sp, r7 + 8001322: bd80 pop {r7, pc} + +08001324 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { - 8001518: b480 push {r7} - 800151a: af00 add r7, sp, #0 + 8001324: b480 push {r7} + 8001326: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); - 800151c: b672 cpsid i + 8001328: b672 cpsid i } - 800151e: bf00 nop + 800132a: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) - 8001520: e7fe b.n 8001520 + 800132c: e7fe b.n 800132c -08001522 : +0800132e : { - 8001522: b480 push {r7} - 8001524: b085 sub sp, #20 - 8001526: af00 add r7, sp, #0 - 8001528: 6078 str r0, [r7, #4] + 800132e: b480 push {r7} + 8001330: b085 sub sp, #20 + 8001332: af00 add r7, sp, #0 + 8001334: 6078 str r0, [r7, #4] SET_BIT(RCC->AHB1ENR, Periphs); - 800152a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800152e: 6c9a ldr r2, [r3, #72] ; 0x48 - 8001530: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 8001534: 687b ldr r3, [r7, #4] - 8001536: 4313 orrs r3, r2 - 8001538: 648b str r3, [r1, #72] ; 0x48 + 8001336: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800133a: 6c9a ldr r2, [r3, #72] ; 0x48 + 800133c: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8001340: 687b ldr r3, [r7, #4] + 8001342: 4313 orrs r3, r2 + 8001344: 648b str r3, [r1, #72] ; 0x48 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); - 800153a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800153e: 6c9a ldr r2, [r3, #72] ; 0x48 - 8001540: 687b ldr r3, [r7, #4] - 8001542: 4013 ands r3, r2 - 8001544: 60fb str r3, [r7, #12] + 8001346: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800134a: 6c9a ldr r2, [r3, #72] ; 0x48 + 800134c: 687b ldr r3, [r7, #4] + 800134e: 4013 ands r3, r2 + 8001350: 60fb str r3, [r7, #12] (void)tmpreg; - 8001546: 68fb ldr r3, [r7, #12] + 8001352: 68fb ldr r3, [r7, #12] } - 8001548: bf00 nop - 800154a: 3714 adds r7, #20 - 800154c: 46bd mov sp, r7 - 800154e: bc80 pop {r7} - 8001550: 4770 bx lr + 8001354: bf00 nop + 8001356: 3714 adds r7, #20 + 8001358: 46bd mov sp, r7 + 800135a: bc80 pop {r7} + 800135c: 4770 bx lr -08001552 : +0800135e : { - 8001552: b480 push {r7} - 8001554: b085 sub sp, #20 - 8001556: af00 add r7, sp, #0 - 8001558: 6078 str r0, [r7, #4] + 800135e: b480 push {r7} + 8001360: b085 sub sp, #20 + 8001362: af00 add r7, sp, #0 + 8001364: 6078 str r0, [r7, #4] SET_BIT(RCC->AHB2ENR, Periphs); - 800155a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800155e: 6cda ldr r2, [r3, #76] ; 0x4c - 8001560: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 8001564: 687b ldr r3, [r7, #4] - 8001566: 4313 orrs r3, r2 - 8001568: 64cb str r3, [r1, #76] ; 0x4c + 8001366: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800136a: 6cda ldr r2, [r3, #76] ; 0x4c + 800136c: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8001370: 687b ldr r3, [r7, #4] + 8001372: 4313 orrs r3, r2 + 8001374: 64cb str r3, [r1, #76] ; 0x4c tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); - 800156a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800156e: 6cda ldr r2, [r3, #76] ; 0x4c - 8001570: 687b ldr r3, [r7, #4] - 8001572: 4013 ands r3, r2 - 8001574: 60fb str r3, [r7, #12] + 8001376: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800137a: 6cda ldr r2, [r3, #76] ; 0x4c + 800137c: 687b ldr r3, [r7, #4] + 800137e: 4013 ands r3, r2 + 8001380: 60fb str r3, [r7, #12] (void)tmpreg; - 8001576: 68fb ldr r3, [r7, #12] + 8001382: 68fb ldr r3, [r7, #12] } - 8001578: bf00 nop - 800157a: 3714 adds r7, #20 - 800157c: 46bd mov sp, r7 - 800157e: bc80 pop {r7} - 8001580: 4770 bx lr + 8001384: bf00 nop + 8001386: 3714 adds r7, #20 + 8001388: 46bd mov sp, r7 + 800138a: bc80 pop {r7} + 800138c: 4770 bx lr -08001582 : +0800138e : * @arg @ref LL_APB1_GRP1_PERIPH_DAC * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 * @retval None */ __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) { - 8001582: b480 push {r7} - 8001584: b085 sub sp, #20 - 8001586: af00 add r7, sp, #0 - 8001588: 6078 str r0, [r7, #4] + 800138e: b480 push {r7} + 8001390: b085 sub sp, #20 + 8001392: af00 add r7, sp, #0 + 8001394: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR1, Periphs); - 800158a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800158e: 6d9a ldr r2, [r3, #88] ; 0x58 - 8001590: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 8001594: 687b ldr r3, [r7, #4] - 8001596: 4313 orrs r3, r2 - 8001598: 658b str r3, [r1, #88] ; 0x58 + 8001396: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800139a: 6d9a ldr r2, [r3, #88] ; 0x58 + 800139c: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80013a0: 687b ldr r3, [r7, #4] + 80013a2: 4313 orrs r3, r2 + 80013a4: 658b str r3, [r1, #88] ; 0x58 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); - 800159a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800159e: 6d9a ldr r2, [r3, #88] ; 0x58 - 80015a0: 687b ldr r3, [r7, #4] - 80015a2: 4013 ands r3, r2 - 80015a4: 60fb str r3, [r7, #12] + 80013a6: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80013aa: 6d9a ldr r2, [r3, #88] ; 0x58 + 80013ac: 687b ldr r3, [r7, #4] + 80013ae: 4013 ands r3, r2 + 80013b0: 60fb str r3, [r7, #12] (void)tmpreg; - 80015a6: 68fb ldr r3, [r7, #12] + 80013b2: 68fb ldr r3, [r7, #12] } - 80015a8: bf00 nop - 80015aa: 3714 adds r7, #20 - 80015ac: 46bd mov sp, r7 - 80015ae: bc80 pop {r7} - 80015b0: 4770 bx lr + 80013b4: bf00 nop + 80013b6: 3714 adds r7, #20 + 80013b8: 46bd mov sp, r7 + 80013ba: bc80 pop {r7} + 80013bc: 4770 bx lr -080015b2 : +080013be : * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 * @retval None */ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) { - 80015b2: b480 push {r7} - 80015b4: b085 sub sp, #20 - 80015b6: af00 add r7, sp, #0 - 80015b8: 6078 str r0, [r7, #4] + 80013be: b480 push {r7} + 80013c0: b085 sub sp, #20 + 80013c2: af00 add r7, sp, #0 + 80013c4: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, Periphs); - 80015ba: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80015be: 6e1a ldr r2, [r3, #96] ; 0x60 - 80015c0: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 80015c4: 687b ldr r3, [r7, #4] - 80015c6: 4313 orrs r3, r2 - 80015c8: 660b str r3, [r1, #96] ; 0x60 + 80013c6: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80013ca: 6e1a ldr r2, [r3, #96] ; 0x60 + 80013cc: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80013d0: 687b ldr r3, [r7, #4] + 80013d2: 4313 orrs r3, r2 + 80013d4: 660b str r3, [r1, #96] ; 0x60 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB2ENR, Periphs); - 80015ca: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80015ce: 6e1a ldr r2, [r3, #96] ; 0x60 - 80015d0: 687b ldr r3, [r7, #4] - 80015d2: 4013 ands r3, r2 - 80015d4: 60fb str r3, [r7, #12] + 80013d6: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80013da: 6e1a ldr r2, [r3, #96] ; 0x60 + 80013dc: 687b ldr r3, [r7, #4] + 80013de: 4013 ands r3, r2 + 80013e0: 60fb str r3, [r7, #12] (void)tmpreg; - 80015d6: 68fb ldr r3, [r7, #12] + 80013e2: 68fb ldr r3, [r7, #12] } - 80015d8: bf00 nop - 80015da: 3714 adds r7, #20 - 80015dc: 46bd mov sp, r7 - 80015de: bc80 pop {r7} - 80015e0: 4770 bx lr + 80013e4: bf00 nop + 80013e6: 3714 adds r7, #20 + 80013e8: 46bd mov sp, r7 + 80013ea: bc80 pop {r7} + 80013ec: 4770 bx lr -080015e2 : +080013ee : * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI * @retval None */ __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs) { - 80015e2: b480 push {r7} - 80015e4: b085 sub sp, #20 - 80015e6: af00 add r7, sp, #0 - 80015e8: 6078 str r0, [r7, #4] + 80013ee: b480 push {r7} + 80013f0: b085 sub sp, #20 + 80013f2: af00 add r7, sp, #0 + 80013f4: 6078 str r0, [r7, #4] __IO uint32_t tmpreg; SET_BIT(RCC->APB3ENR, Periphs); - 80015ea: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80015ee: 6e5a ldr r2, [r3, #100] ; 0x64 - 80015f0: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 80015f4: 687b ldr r3, [r7, #4] - 80015f6: 4313 orrs r3, r2 - 80015f8: 664b str r3, [r1, #100] ; 0x64 + 80013f6: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80013fa: 6e5a ldr r2, [r3, #100] ; 0x64 + 80013fc: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8001400: 687b ldr r3, [r7, #4] + 8001402: 4313 orrs r3, r2 + 8001404: 664b str r3, [r1, #100] ; 0x64 /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB3ENR, Periphs); - 80015fa: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80015fe: 6e5a ldr r2, [r3, #100] ; 0x64 - 8001600: 687b ldr r3, [r7, #4] - 8001602: 4013 ands r3, r2 - 8001604: 60fb str r3, [r7, #12] + 8001406: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800140a: 6e5a ldr r2, [r3, #100] ; 0x64 + 800140c: 687b ldr r3, [r7, #4] + 800140e: 4013 ands r3, r2 + 8001410: 60fb str r3, [r7, #12] (void)tmpreg; - 8001606: 68fb ldr r3, [r7, #12] + 8001412: 68fb ldr r3, [r7, #12] } - 8001608: bf00 nop - 800160a: 3714 adds r7, #20 - 800160c: 46bd mov sp, r7 - 800160e: bc80 pop {r7} - 8001610: 4770 bx lr + 8001414: bf00 nop + 8001416: 3714 adds r7, #20 + 8001418: 46bd mov sp, r7 + 800141a: bc80 pop {r7} + 800141c: 4770 bx lr -08001612 : +0800141e : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { - 8001612: b480 push {r7} - 8001614: af00 add r7, sp, #0 + 800141e: b480 push {r7} + 8001420: af00 add r7, sp, #0 /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } - 8001616: bf00 nop - 8001618: 46bd mov sp, r7 - 800161a: bc80 pop {r7} - 800161c: 4770 bx lr + 8001422: bf00 nop + 8001424: 46bd mov sp, r7 + 8001426: bc80 pop {r7} + 8001428: 4770 bx lr ... -08001620 : +0800142c : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { - 8001620: b580 push {r7, lr} - 8001622: b082 sub sp, #8 - 8001624: af00 add r7, sp, #0 - 8001626: 6078 str r0, [r7, #4] + 800142c: b580 push {r7, lr} + 800142e: b082 sub sp, #8 + 8001430: af00 add r7, sp, #0 + 8001432: 6078 str r0, [r7, #4] if(hadc->Instance==ADC) - 8001628: 687b ldr r3, [r7, #4] - 800162a: 681b ldr r3, [r3, #0] - 800162c: 4a05 ldr r2, [pc, #20] ; (8001644 ) - 800162e: 4293 cmp r3, r2 - 8001630: d103 bne.n 800163a + 8001434: 687b ldr r3, [r7, #4] + 8001436: 681b ldr r3, [r3, #0] + 8001438: 4a05 ldr r2, [pc, #20] ; (8001450 ) + 800143a: 4293 cmp r3, r2 + 800143c: d103 bne.n 8001446 { /* USER CODE BEGIN ADC_MspInit 0 */ /* USER CODE END ADC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_ADC_CLK_ENABLE(); - 8001632: f44f 7000 mov.w r0, #512 ; 0x200 - 8001636: f7ff ffbc bl 80015b2 + 800143e: f44f 7000 mov.w r0, #512 ; 0x200 + 8001442: f7ff ffbc bl 80013be /* USER CODE BEGIN ADC_MspInit 1 */ /* USER CODE END ADC_MspInit 1 */ } } - 800163a: bf00 nop - 800163c: 3708 adds r7, #8 - 800163e: 46bd mov sp, r7 - 8001640: bd80 pop {r7, pc} - 8001642: bf00 nop - 8001644: 40012400 .word 0x40012400 + 8001446: bf00 nop + 8001448: 3708 adds r7, #8 + 800144a: 46bd mov sp, r7 + 800144c: bd80 pop {r7, pc} + 800144e: bf00 nop + 8001450: 40012400 .word 0x40012400 -08001648 : +08001454 : * This function configures the hardware resources used in this example * @param hcrc: CRC handle pointer * @retval None */ void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) { - 8001648: b580 push {r7, lr} - 800164a: b082 sub sp, #8 - 800164c: af00 add r7, sp, #0 - 800164e: 6078 str r0, [r7, #4] + 8001454: b580 push {r7, lr} + 8001456: b082 sub sp, #8 + 8001458: af00 add r7, sp, #0 + 800145a: 6078 str r0, [r7, #4] if(hcrc->Instance==CRC) - 8001650: 687b ldr r3, [r7, #4] - 8001652: 681b ldr r3, [r3, #0] - 8001654: 4a05 ldr r2, [pc, #20] ; (800166c ) - 8001656: 4293 cmp r3, r2 - 8001658: d103 bne.n 8001662 + 800145c: 687b ldr r3, [r7, #4] + 800145e: 681b ldr r3, [r3, #0] + 8001460: 4a05 ldr r2, [pc, #20] ; (8001478 ) + 8001462: 4293 cmp r3, r2 + 8001464: d103 bne.n 800146e { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); - 800165a: f44f 5080 mov.w r0, #4096 ; 0x1000 - 800165e: f7ff ff60 bl 8001522 + 8001466: f44f 5080 mov.w r0, #4096 ; 0x1000 + 800146a: f7ff ff60 bl 800132e /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } - 8001662: bf00 nop - 8001664: 3708 adds r7, #8 - 8001666: 46bd mov sp, r7 - 8001668: bd80 pop {r7, pc} - 800166a: bf00 nop - 800166c: 40023000 .word 0x40023000 + 800146e: bf00 nop + 8001470: 3708 adds r7, #8 + 8001472: 46bd mov sp, r7 + 8001474: bd80 pop {r7, pc} + 8001476: bf00 nop + 8001478: 40023000 .word 0x40023000 -08001670 : +0800147c : * This function configures the hardware resources used in this example * @param hsubghz: SUBGHZ handle pointer * @retval None */ void HAL_SUBGHZ_MspInit(SUBGHZ_HandleTypeDef* hsubghz) { - 8001670: b580 push {r7, lr} - 8001672: b082 sub sp, #8 - 8001674: af00 add r7, sp, #0 - 8001676: 6078 str r0, [r7, #4] + 800147c: b580 push {r7, lr} + 800147e: b082 sub sp, #8 + 8001480: af00 add r7, sp, #0 + 8001482: 6078 str r0, [r7, #4] /* USER CODE BEGIN SUBGHZ_MspInit 0 */ /* USER CODE END SUBGHZ_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SUBGHZSPI_CLK_ENABLE(); - 8001678: 2001 movs r0, #1 - 800167a: f7ff ffb2 bl 80015e2 + 8001484: 2001 movs r0, #1 + 8001486: f7ff ffb2 bl 80013ee /* USER CODE BEGIN SUBGHZ_MspInit 1 */ /* USER CODE END SUBGHZ_MspInit 1 */ } - 800167e: bf00 nop - 8001680: 3708 adds r7, #8 - 8001682: 46bd mov sp, r7 - 8001684: bd80 pop {r7, pc} + 800148a: bf00 nop + 800148c: 3708 adds r7, #8 + 800148e: 46bd mov sp, r7 + 8001490: bd80 pop {r7, pc} ... -08001688 : +08001494 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { - 8001688: b580 push {r7, lr} - 800168a: b096 sub sp, #88 ; 0x58 - 800168c: af00 add r7, sp, #0 - 800168e: 6078 str r0, [r7, #4] + 8001494: b580 push {r7, lr} + 8001496: b096 sub sp, #88 ; 0x58 + 8001498: af00 add r7, sp, #0 + 800149a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8001690: f107 0344 add.w r3, r7, #68 ; 0x44 - 8001694: 2200 movs r2, #0 - 8001696: 601a str r2, [r3, #0] - 8001698: 605a str r2, [r3, #4] - 800169a: 609a str r2, [r3, #8] - 800169c: 60da str r2, [r3, #12] - 800169e: 611a str r2, [r3, #16] + 800149c: f107 0344 add.w r3, r7, #68 ; 0x44 + 80014a0: 2200 movs r2, #0 + 80014a2: 601a str r2, [r3, #0] + 80014a4: 605a str r2, [r3, #4] + 80014a6: 609a str r2, [r3, #8] + 80014a8: 60da str r2, [r3, #12] + 80014aa: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - 80016a0: f107 030c add.w r3, r7, #12 - 80016a4: 2238 movs r2, #56 ; 0x38 - 80016a6: 2100 movs r1, #0 - 80016a8: 4618 mov r0, r3 - 80016aa: f003 f955 bl 8004958 + 80014ac: f107 030c add.w r3, r7, #12 + 80014b0: 2238 movs r2, #56 ; 0x38 + 80014b2: 2100 movs r1, #0 + 80014b4: 4618 mov r0, r3 + 80014b6: f003 f955 bl 8004764 if(huart->Instance==USART2) - 80016ae: 687b ldr r3, [r7, #4] - 80016b0: 681b ldr r3, [r3, #0] - 80016b2: 4a17 ldr r2, [pc, #92] ; (8001710 ) - 80016b4: 4293 cmp r3, r2 - 80016b6: d126 bne.n 8001706 + 80014ba: 687b ldr r3, [r7, #4] + 80014bc: 681b ldr r3, [r3, #0] + 80014be: 4a17 ldr r2, [pc, #92] ; (800151c ) + 80014c0: 4293 cmp r3, r2 + 80014c2: d126 bne.n 8001512 /* USER CODE END USART2_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART2; - 80016b8: 2302 movs r3, #2 - 80016ba: 60fb str r3, [r7, #12] + 80014c4: 2302 movs r3, #2 + 80014c6: 60fb str r3, [r7, #12] PeriphClkInitStruct.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; - 80016bc: f44f 2340 mov.w r3, #786432 ; 0xc0000 - 80016c0: 617b str r3, [r7, #20] + 80014c8: f44f 2340 mov.w r3, #786432 ; 0xc0000 + 80014cc: 617b str r3, [r7, #20] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - 80016c2: f107 030c add.w r3, r7, #12 - 80016c6: 4618 mov r0, r3 - 80016c8: f002 f844 bl 8003754 - 80016cc: 4603 mov r3, r0 - 80016ce: 2b00 cmp r3, #0 - 80016d0: d001 beq.n 80016d6 + 80014ce: f107 030c add.w r3, r7, #12 + 80014d2: 4618 mov r0, r3 + 80014d4: f002 f844 bl 8003560 + 80014d8: 4603 mov r3, r0 + 80014da: 2b00 cmp r3, #0 + 80014dc: d001 beq.n 80014e2 { Error_Handler(); - 80016d2: f7ff ff21 bl 8001518 + 80014de: f7ff ff21 bl 8001324 } /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - 80016d6: f44f 3000 mov.w r0, #131072 ; 0x20000 - 80016da: f7ff ff52 bl 8001582 + 80014e2: f44f 3000 mov.w r0, #131072 ; 0x20000 + 80014e6: f7ff ff52 bl 800138e __HAL_RCC_GPIOA_CLK_ENABLE(); - 80016de: 2001 movs r0, #1 - 80016e0: f7ff ff37 bl 8001552 + 80014ea: 2001 movs r0, #1 + 80014ec: f7ff ff37 bl 800135e /**USART2 GPIO Configuration PA2 ------> USART2_TX PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; - 80016e4: 230c movs r3, #12 - 80016e6: 647b str r3, [r7, #68] ; 0x44 + 80014f0: 230c movs r3, #12 + 80014f2: 647b str r3, [r7, #68] ; 0x44 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 80016e8: 2302 movs r3, #2 - 80016ea: 64bb str r3, [r7, #72] ; 0x48 + 80014f4: 2302 movs r3, #2 + 80014f6: 64bb str r3, [r7, #72] ; 0x48 GPIO_InitStruct.Pull = GPIO_NOPULL; - 80016ec: 2300 movs r3, #0 - 80016ee: 64fb str r3, [r7, #76] ; 0x4c + 80014f8: 2300 movs r3, #0 + 80014fa: 64fb str r3, [r7, #76] ; 0x4c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 80016f0: 2300 movs r3, #0 - 80016f2: 653b str r3, [r7, #80] ; 0x50 + 80014fc: 2300 movs r3, #0 + 80014fe: 653b str r3, [r7, #80] ; 0x50 GPIO_InitStruct.Alternate = GPIO_AF7_USART2; - 80016f4: 2307 movs r3, #7 - 80016f6: 657b str r3, [r7, #84] ; 0x54 + 8001500: 2307 movs r3, #7 + 8001502: 657b str r3, [r7, #84] ; 0x54 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 80016f8: f107 0344 add.w r3, r7, #68 ; 0x44 - 80016fc: 4619 mov r1, r3 - 80016fe: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 - 8001702: f000 fce1 bl 80020c8 + 8001504: f107 0344 add.w r3, r7, #68 ; 0x44 + 8001508: 4619 mov r1, r3 + 800150a: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 800150e: f000 fce1 bl 8001ed4 /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } - 8001706: bf00 nop - 8001708: 3758 adds r7, #88 ; 0x58 - 800170a: 46bd mov sp, r7 - 800170c: bd80 pop {r7, pc} - 800170e: bf00 nop - 8001710: 40004400 .word 0x40004400 + 8001512: bf00 nop + 8001514: 3758 adds r7, #88 ; 0x58 + 8001516: 46bd mov sp, r7 + 8001518: bd80 pop {r7, pc} + 800151a: bf00 nop + 800151c: 40004400 .word 0x40004400 -08001714 : +08001520 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { - 8001714: b480 push {r7} - 8001716: af00 add r7, sp, #0 + 8001520: b480 push {r7} + 8001522: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) - 8001718: e7fe b.n 8001718 + 8001524: e7fe b.n 8001524 -0800171a : +08001526 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { - 800171a: b480 push {r7} - 800171c: af00 add r7, sp, #0 + 8001526: b480 push {r7} + 8001528: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) - 800171e: e7fe b.n 800171e + 800152a: e7fe b.n 800152a -08001720 : +0800152c : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { - 8001720: b480 push {r7} - 8001722: af00 add r7, sp, #0 + 800152c: b480 push {r7} + 800152e: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) - 8001724: e7fe b.n 8001724 + 8001530: e7fe b.n 8001530 -08001726 : +08001532 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { - 8001726: b480 push {r7} - 8001728: af00 add r7, sp, #0 + 8001532: b480 push {r7} + 8001534: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) - 800172a: e7fe b.n 800172a + 8001536: e7fe b.n 8001536 -0800172c : +08001538 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { - 800172c: b480 push {r7} - 800172e: af00 add r7, sp, #0 + 8001538: b480 push {r7} + 800153a: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) - 8001730: e7fe b.n 8001730 + 800153c: e7fe b.n 800153c -08001732 : +0800153e : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { - 8001732: b480 push {r7} - 8001734: af00 add r7, sp, #0 + 800153e: b480 push {r7} + 8001540: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } - 8001736: bf00 nop - 8001738: 46bd mov sp, r7 - 800173a: bc80 pop {r7} - 800173c: 4770 bx lr + 8001542: bf00 nop + 8001544: 46bd mov sp, r7 + 8001546: bc80 pop {r7} + 8001548: 4770 bx lr -0800173e : +0800154a : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { - 800173e: b480 push {r7} - 8001740: af00 add r7, sp, #0 + 800154a: b480 push {r7} + 800154c: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } - 8001742: bf00 nop - 8001744: 46bd mov sp, r7 - 8001746: bc80 pop {r7} - 8001748: 4770 bx lr + 800154e: bf00 nop + 8001550: 46bd mov sp, r7 + 8001552: bc80 pop {r7} + 8001554: 4770 bx lr -0800174a : +08001556 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { - 800174a: b480 push {r7} - 800174c: af00 add r7, sp, #0 + 8001556: b480 push {r7} + 8001558: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } - 800174e: bf00 nop - 8001750: 46bd mov sp, r7 - 8001752: bc80 pop {r7} - 8001754: 4770 bx lr + 800155a: bf00 nop + 800155c: 46bd mov sp, r7 + 800155e: bc80 pop {r7} + 8001560: 4770 bx lr -08001756 : +08001562 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { - 8001756: b580 push {r7, lr} - 8001758: af00 add r7, sp, #0 + 8001562: b580 push {r7, lr} + 8001564: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); - 800175a: f000 f88d bl 8001878 + 8001566: f000 f88d bl 8001684 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } - 800175e: bf00 nop - 8001760: bd80 pop {r7, pc} + 800156a: bf00 nop + 800156c: bd80 pop {r7, pc} -08001762 : +0800156e : * @brief Setup the microcontroller system. * @param None * @retval None */ void SystemInit(void) { - 8001762: b480 push {r7} - 8001764: af00 add r7, sp, #0 + 800156e: b480 push {r7} + 8001570: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL))); /* set CP10 and CP11 Full Access */ #endif } - 8001766: bf00 nop - 8001768: 46bd mov sp, r7 - 800176a: bc80 pop {r7} - 800176c: 4770 bx lr + 8001572: bf00 nop + 8001574: 46bd mov sp, r7 + 8001576: bc80 pop {r7} + 8001578: 4770 bx lr ... -08001770 : +0800157c : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack - 8001770: 480d ldr r0, [pc, #52] ; (80017a8 ) + 800157c: 480d ldr r0, [pc, #52] ; (80015b4 ) mov sp, r0 /* set stack pointer */ - 8001772: 4685 mov sp, r0 + 800157e: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit - 8001774: f7ff fff5 bl 8001762 + 8001580: f7ff fff5 bl 800156e /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata - 8001778: 480c ldr r0, [pc, #48] ; (80017ac ) + 8001584: 480c ldr r0, [pc, #48] ; (80015b8 ) ldr r1, =_edata - 800177a: 490d ldr r1, [pc, #52] ; (80017b0 ) + 8001586: 490d ldr r1, [pc, #52] ; (80015bc ) ldr r2, =_sidata - 800177c: 4a0d ldr r2, [pc, #52] ; (80017b4 ) + 8001588: 4a0d ldr r2, [pc, #52] ; (80015c0 ) movs r3, #0 - 800177e: 2300 movs r3, #0 + 800158a: 2300 movs r3, #0 b LoopCopyDataInit - 8001780: e002 b.n 8001788 + 800158c: e002 b.n 8001594 -08001782 : +0800158e : CopyDataInit: ldr r4, [r2, r3] - 8001782: 58d4 ldr r4, [r2, r3] + 800158e: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] - 8001784: 50c4 str r4, [r0, r3] + 8001590: 50c4 str r4, [r0, r3] adds r3, r3, #4 - 8001786: 3304 adds r3, #4 + 8001592: 3304 adds r3, #4 -08001788 : +08001594 : LoopCopyDataInit: adds r4, r0, r3 - 8001788: 18c4 adds r4, r0, r3 + 8001594: 18c4 adds r4, r0, r3 cmp r4, r1 - 800178a: 428c cmp r4, r1 + 8001596: 428c cmp r4, r1 bcc CopyDataInit - 800178c: d3f9 bcc.n 8001782 + 8001598: d3f9 bcc.n 800158e /* Zero fill the bss segment. */ ldr r2, =_sbss - 800178e: 4a0a ldr r2, [pc, #40] ; (80017b8 ) + 800159a: 4a0a ldr r2, [pc, #40] ; (80015c4 ) ldr r4, =_ebss - 8001790: 4c0a ldr r4, [pc, #40] ; (80017bc ) + 800159c: 4c0a ldr r4, [pc, #40] ; (80015c8 ) movs r3, #0 - 8001792: 2300 movs r3, #0 + 800159e: 2300 movs r3, #0 b LoopFillZerobss - 8001794: e001 b.n 800179a + 80015a0: e001 b.n 80015a6 -08001796 : +080015a2 : FillZerobss: str r3, [r2] - 8001796: 6013 str r3, [r2, #0] + 80015a2: 6013 str r3, [r2, #0] adds r2, r2, #4 - 8001798: 3204 adds r2, #4 + 80015a4: 3204 adds r2, #4 -0800179a : +080015a6 : LoopFillZerobss: cmp r2, r4 - 800179a: 42a2 cmp r2, r4 + 80015a6: 42a2 cmp r2, r4 bcc FillZerobss - 800179c: d3fb bcc.n 8001796 + 80015a8: d3fb bcc.n 80015a2 /* Call static constructors */ bl __libc_init_array - 800179e: f003 f8b7 bl 8004910 <__libc_init_array> + 80015aa: f003 f8b7 bl 800471c <__libc_init_array> /* Call the application's entry point.*/ bl main - 80017a2: f7ff fcc9 bl 8001138
+ 80015ae: f7ff fb8f bl 8000cd0
-080017a6 : +080015b2 : LoopForever: b LoopForever - 80017a6: e7fe b.n 80017a6 + 80015b2: e7fe b.n 80015b2 ldr r0, =_estack - 80017a8: 20004000 .word 0x20004000 + 80015b4: 20004000 .word 0x20004000 ldr r0, =_sdata - 80017ac: 20000000 .word 0x20000000 + 80015b8: 20000000 .word 0x20000000 ldr r1, =_edata - 80017b0: 20000014 .word 0x20000014 + 80015bc: 2000000c .word 0x2000000c ldr r2, =_sidata - 80017b4: 08004aec .word 0x08004aec + 80015c0: 08004890 .word 0x08004890 ldr r2, =_sbss - 80017b8: 20000014 .word 0x20000014 + 80015c4: 2000000c .word 0x2000000c ldr r4, =_ebss - 80017bc: 2000015c .word 0x2000015c + 80015c8: 20000154 .word 0x20000154 -080017c0 : +080015cc : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop - 80017c0: e7fe b.n 80017c0 + 80015cc: e7fe b.n 80015cc ... -080017c4 : +080015d0 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { - 80017c4: b580 push {r7, lr} - 80017c6: b082 sub sp, #8 - 80017c8: af00 add r7, sp, #0 + 80015d0: b580 push {r7, lr} + 80015d2: b082 sub sp, #8 + 80015d4: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; - 80017ca: 2300 movs r3, #0 - 80017cc: 71fb strb r3, [r7, #7] + 80015d6: 2300 movs r3, #0 + 80015d8: 71fb strb r3, [r7, #7] #endif /* PREFETCH_ENABLE */ #ifdef CORE_CM0PLUS #else /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - 80017ce: 2003 movs r0, #3 - 80017d0: f000 fb56 bl 8001e80 + 80015da: 2003 movs r0, #3 + 80015dc: f000 fb56 bl 8001c8c /* Update the SystemCoreClock global variable */ #if defined(DUAL_CORE) && defined(CORE_CM0PLUS) SystemCoreClock = HAL_RCC_GetHCLK2Freq(); #else SystemCoreClock = HAL_RCC_GetHCLKFreq(); - 80017d4: f001 fde0 bl 8003398 - 80017d8: 4603 mov r3, r0 - 80017da: 4a09 ldr r2, [pc, #36] ; (8001800 ) - 80017dc: 6013 str r3, [r2, #0] + 80015e0: f001 fde0 bl 80031a4 + 80015e4: 4603 mov r3, r0 + 80015e6: 4a09 ldr r2, [pc, #36] ; (800160c ) + 80015e8: 6013 str r3, [r2, #0] #endif /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) - 80017de: 200f movs r0, #15 - 80017e0: f000 f810 bl 8001804 - 80017e4: 4603 mov r3, r0 - 80017e6: 2b00 cmp r3, #0 - 80017e8: d002 beq.n 80017f0 + 80015ea: 200f movs r0, #15 + 80015ec: f000 f810 bl 8001610 + 80015f0: 4603 mov r3, r0 + 80015f2: 2b00 cmp r3, #0 + 80015f4: d002 beq.n 80015fc { status = HAL_ERROR; - 80017ea: 2301 movs r3, #1 - 80017ec: 71fb strb r3, [r7, #7] - 80017ee: e001 b.n 80017f4 + 80015f6: 2301 movs r3, #1 + 80015f8: 71fb strb r3, [r7, #7] + 80015fa: e001 b.n 8001600 } else { /* Init the low level hardware */ HAL_MspInit(); - 80017f0: f7ff ff0f bl 8001612 + 80015fc: f7ff ff0f bl 800141e } /* Return function status */ return status; - 80017f4: 79fb ldrb r3, [r7, #7] + 8001600: 79fb ldrb r3, [r7, #7] } - 80017f6: 4618 mov r0, r3 - 80017f8: 3708 adds r7, #8 - 80017fa: 46bd mov sp, r7 - 80017fc: bd80 pop {r7, pc} - 80017fe: bf00 nop - 8001800: 20000008 .word 0x20000008 + 8001602: 4618 mov r0, r3 + 8001604: 3708 adds r7, #8 + 8001606: 46bd mov sp, r7 + 8001608: bd80 pop {r7, pc} + 800160a: bf00 nop + 800160c: 20000000 .word 0x20000000 -08001804 : +08001610 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - 8001804: b580 push {r7, lr} - 8001806: b084 sub sp, #16 - 8001808: af00 add r7, sp, #0 - 800180a: 6078 str r0, [r7, #4] + 8001610: b580 push {r7, lr} + 8001612: b084 sub sp, #16 + 8001614: af00 add r7, sp, #0 + 8001616: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; - 800180c: 2300 movs r3, #0 - 800180e: 73fb strb r3, [r7, #15] + 8001618: 2300 movs r3, #0 + 800161a: 73fb strb r3, [r7, #15] /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ if ((uint32_t)uwTickFreq != 0U) - 8001810: 4b17 ldr r3, [pc, #92] ; (8001870 ) - 8001812: 781b ldrb r3, [r3, #0] - 8001814: 2b00 cmp r3, #0 - 8001816: d024 beq.n 8001862 + 800161c: 4b17 ldr r3, [pc, #92] ; (800167c ) + 800161e: 781b ldrb r3, [r3, #0] + 8001620: 2b00 cmp r3, #0 + 8001622: d024 beq.n 800166e { /*Configure the SysTick to have interrupt in 1ms time basis*/ #ifdef CORE_CM0PLUS if (HAL_SYSTICK_Config(HAL_RCC_GetHCLK2Freq() / (1000U / (uint32_t)uwTickFreq)) == 0U) #else if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / (1000U / (uint32_t)uwTickFreq)) == 0U) - 8001818: f001 fdbe bl 8003398 - 800181c: 4602 mov r2, r0 - 800181e: 4b14 ldr r3, [pc, #80] ; (8001870 ) - 8001820: 781b ldrb r3, [r3, #0] - 8001822: 4619 mov r1, r3 - 8001824: f44f 737a mov.w r3, #1000 ; 0x3e8 - 8001828: fbb3 f3f1 udiv r3, r3, r1 - 800182c: fbb2 f3f3 udiv r3, r2, r3 - 8001830: 4618 mov r0, r3 - 8001832: f000 fb4a bl 8001eca - 8001836: 4603 mov r3, r0 - 8001838: 2b00 cmp r3, #0 - 800183a: d10f bne.n 800185c + 8001624: f001 fdbe bl 80031a4 + 8001628: 4602 mov r2, r0 + 800162a: 4b14 ldr r3, [pc, #80] ; (800167c ) + 800162c: 781b ldrb r3, [r3, #0] + 800162e: 4619 mov r1, r3 + 8001630: f44f 737a mov.w r3, #1000 ; 0x3e8 + 8001634: fbb3 f3f1 udiv r3, r3, r1 + 8001638: fbb2 f3f3 udiv r3, r2, r3 + 800163c: 4618 mov r0, r3 + 800163e: f000 fb4a bl 8001cd6 + 8001642: 4603 mov r3, r0 + 8001644: 2b00 cmp r3, #0 + 8001646: d10f bne.n 8001668 #endif { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - 800183c: 687b ldr r3, [r7, #4] - 800183e: 2b0f cmp r3, #15 - 8001840: d809 bhi.n 8001856 + 8001648: 687b ldr r3, [r7, #4] + 800164a: 2b0f cmp r3, #15 + 800164c: d809 bhi.n 8001662 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - 8001842: 2200 movs r2, #0 - 8001844: 6879 ldr r1, [r7, #4] - 8001846: f04f 30ff mov.w r0, #4294967295 - 800184a: f000 fb24 bl 8001e96 + 800164e: 2200 movs r2, #0 + 8001650: 6879 ldr r1, [r7, #4] + 8001652: f04f 30ff mov.w r0, #4294967295 + 8001656: f000 fb24 bl 8001ca2 uwTickPrio = TickPriority; - 800184e: 4a09 ldr r2, [pc, #36] ; (8001874 ) - 8001850: 687b ldr r3, [r7, #4] - 8001852: 6013 str r3, [r2, #0] - 8001854: e007 b.n 8001866 + 800165a: 4a09 ldr r2, [pc, #36] ; (8001680 ) + 800165c: 687b ldr r3, [r7, #4] + 800165e: 6013 str r3, [r2, #0] + 8001660: e007 b.n 8001672 } else { status = HAL_ERROR; - 8001856: 2301 movs r3, #1 - 8001858: 73fb strb r3, [r7, #15] - 800185a: e004 b.n 8001866 + 8001662: 2301 movs r3, #1 + 8001664: 73fb strb r3, [r7, #15] + 8001666: e004 b.n 8001672 } } else { status = HAL_ERROR; - 800185c: 2301 movs r3, #1 - 800185e: 73fb strb r3, [r7, #15] - 8001860: e001 b.n 8001866 + 8001668: 2301 movs r3, #1 + 800166a: 73fb strb r3, [r7, #15] + 800166c: e001 b.n 8001672 } } else { status = HAL_ERROR; - 8001862: 2301 movs r3, #1 - 8001864: 73fb strb r3, [r7, #15] + 800166e: 2301 movs r3, #1 + 8001670: 73fb strb r3, [r7, #15] } /* Return function status */ return status; - 8001866: 7bfb ldrb r3, [r7, #15] + 8001672: 7bfb ldrb r3, [r7, #15] } - 8001868: 4618 mov r0, r3 - 800186a: 3710 adds r7, #16 - 800186c: 46bd mov sp, r7 - 800186e: bd80 pop {r7, pc} - 8001870: 20000010 .word 0x20000010 - 8001874: 2000000c .word 0x2000000c + 8001674: 4618 mov r0, r3 + 8001676: 3710 adds r7, #16 + 8001678: 46bd mov sp, r7 + 800167a: bd80 pop {r7, pc} + 800167c: 20000008 .word 0x20000008 + 8001680: 20000004 .word 0x20000004 -08001878 : +08001684 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { - 8001878: b480 push {r7} - 800187a: af00 add r7, sp, #0 + 8001684: b480 push {r7} + 8001686: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; - 800187c: 4b05 ldr r3, [pc, #20] ; (8001894 ) - 800187e: 781b ldrb r3, [r3, #0] - 8001880: 461a mov r2, r3 - 8001882: 4b05 ldr r3, [pc, #20] ; (8001898 ) - 8001884: 681b ldr r3, [r3, #0] - 8001886: 4413 add r3, r2 - 8001888: 4a03 ldr r2, [pc, #12] ; (8001898 ) - 800188a: 6013 str r3, [r2, #0] -} - 800188c: bf00 nop - 800188e: 46bd mov sp, r7 - 8001890: bc80 pop {r7} - 8001892: 4770 bx lr - 8001894: 20000010 .word 0x20000010 - 8001898: 20000158 .word 0x20000158 - -0800189c : + 8001688: 4b05 ldr r3, [pc, #20] ; (80016a0 ) + 800168a: 781b ldrb r3, [r3, #0] + 800168c: 461a mov r2, r3 + 800168e: 4b05 ldr r3, [pc, #20] ; (80016a4 ) + 8001690: 681b ldr r3, [r3, #0] + 8001692: 4413 add r3, r2 + 8001694: 4a03 ldr r2, [pc, #12] ; (80016a4 ) + 8001696: 6013 str r3, [r2, #0] +} + 8001698: bf00 nop + 800169a: 46bd mov sp, r7 + 800169c: bc80 pop {r7} + 800169e: 4770 bx lr + 80016a0: 20000008 .word 0x20000008 + 80016a4: 20000150 .word 0x20000150 + +080016a8 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { - 800189c: b480 push {r7} - 800189e: af00 add r7, sp, #0 + 80016a8: b480 push {r7} + 80016aa: af00 add r7, sp, #0 return uwTick; - 80018a0: 4b02 ldr r3, [pc, #8] ; (80018ac ) - 80018a2: 681b ldr r3, [r3, #0] + 80016ac: 4b02 ldr r3, [pc, #8] ; (80016b8 ) + 80016ae: 681b ldr r3, [r3, #0] } - 80018a4: 4618 mov r0, r3 - 80018a6: 46bd mov sp, r7 - 80018a8: bc80 pop {r7} - 80018aa: 4770 bx lr - 80018ac: 20000158 .word 0x20000158 + 80016b0: 4618 mov r0, r3 + 80016b2: 46bd mov sp, r7 + 80016b4: bc80 pop {r7} + 80016b6: 4770 bx lr + 80016b8: 20000150 .word 0x20000150 -080018b0 : +080016bc : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { - 80018b0: b580 push {r7, lr} - 80018b2: b084 sub sp, #16 - 80018b4: af00 add r7, sp, #0 - 80018b6: 6078 str r0, [r7, #4] + 80016bc: b580 push {r7, lr} + 80016be: b084 sub sp, #16 + 80016c0: af00 add r7, sp, #0 + 80016c2: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); - 80018b8: f7ff fff0 bl 800189c - 80018bc: 60b8 str r0, [r7, #8] + 80016c4: f7ff fff0 bl 80016a8 + 80016c8: 60b8 str r0, [r7, #8] uint32_t wait = Delay; - 80018be: 687b ldr r3, [r7, #4] - 80018c0: 60fb str r3, [r7, #12] + 80016ca: 687b ldr r3, [r7, #4] + 80016cc: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) - 80018c2: 68fb ldr r3, [r7, #12] - 80018c4: f1b3 3fff cmp.w r3, #4294967295 - 80018c8: d005 beq.n 80018d6 + 80016ce: 68fb ldr r3, [r7, #12] + 80016d0: f1b3 3fff cmp.w r3, #4294967295 + 80016d4: d005 beq.n 80016e2 { wait += (uint32_t)(uwTickFreq); - 80018ca: 4b0a ldr r3, [pc, #40] ; (80018f4 ) - 80018cc: 781b ldrb r3, [r3, #0] - 80018ce: 461a mov r2, r3 - 80018d0: 68fb ldr r3, [r7, #12] - 80018d2: 4413 add r3, r2 - 80018d4: 60fb str r3, [r7, #12] + 80016d6: 4b0a ldr r3, [pc, #40] ; (8001700 ) + 80016d8: 781b ldrb r3, [r3, #0] + 80016da: 461a mov r2, r3 + 80016dc: 68fb ldr r3, [r7, #12] + 80016de: 4413 add r3, r2 + 80016e0: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) - 80018d6: bf00 nop - 80018d8: f7ff ffe0 bl 800189c - 80018dc: 4602 mov r2, r0 - 80018de: 68bb ldr r3, [r7, #8] - 80018e0: 1ad3 subs r3, r2, r3 - 80018e2: 68fa ldr r2, [r7, #12] - 80018e4: 429a cmp r2, r3 - 80018e6: d8f7 bhi.n 80018d8 + 80016e2: bf00 nop + 80016e4: f7ff ffe0 bl 80016a8 + 80016e8: 4602 mov r2, r0 + 80016ea: 68bb ldr r3, [r7, #8] + 80016ec: 1ad3 subs r3, r2, r3 + 80016ee: 68fa ldr r2, [r7, #12] + 80016f0: 429a cmp r2, r3 + 80016f2: d8f7 bhi.n 80016e4 { } } - 80018e8: bf00 nop - 80018ea: bf00 nop - 80018ec: 3710 adds r7, #16 - 80018ee: 46bd mov sp, r7 - 80018f0: bd80 pop {r7, pc} - 80018f2: bf00 nop - 80018f4: 20000010 .word 0x20000010 + 80016f4: bf00 nop + 80016f6: bf00 nop + 80016f8: 3710 adds r7, #16 + 80016fa: 46bd mov sp, r7 + 80016fc: bd80 pop {r7, pc} + 80016fe: bf00 nop + 8001700: 20000008 .word 0x20000008 -080018f8 : +08001704 : * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 * @retval None */ __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY, uint32_t SamplingTime) { - 80018f8: b480 push {r7} - 80018fa: b085 sub sp, #20 - 80018fc: af00 add r7, sp, #0 - 80018fe: 60f8 str r0, [r7, #12] - 8001900: 60b9 str r1, [r7, #8] - 8001902: 607a str r2, [r7, #4] + 8001704: b480 push {r7} + 8001706: b085 sub sp, #20 + 8001708: af00 add r7, sp, #0 + 800170a: 60f8 str r0, [r7, #12] + 800170c: 60b9 str r1, [r7, #8] + 800170e: 607a str r2, [r7, #4] MODIFY_REG(ADCx->SMPR, - 8001904: 68fb ldr r3, [r7, #12] - 8001906: 695a ldr r2, [r3, #20] - 8001908: 68bb ldr r3, [r7, #8] - 800190a: f003 0304 and.w r3, r3, #4 - 800190e: 2107 movs r1, #7 - 8001910: fa01 f303 lsl.w r3, r1, r3 - 8001914: 43db mvns r3, r3 - 8001916: 401a ands r2, r3 - 8001918: 68bb ldr r3, [r7, #8] - 800191a: f003 0304 and.w r3, r3, #4 - 800191e: 6879 ldr r1, [r7, #4] - 8001920: fa01 f303 lsl.w r3, r1, r3 - 8001924: 431a orrs r2, r3 - 8001926: 68fb ldr r3, [r7, #12] - 8001928: 615a str r2, [r3, #20] + 8001710: 68fb ldr r3, [r7, #12] + 8001712: 695a ldr r2, [r3, #20] + 8001714: 68bb ldr r3, [r7, #8] + 8001716: f003 0304 and.w r3, r3, #4 + 800171a: 2107 movs r1, #7 + 800171c: fa01 f303 lsl.w r3, r1, r3 + 8001720: 43db mvns r3, r3 + 8001722: 401a ands r2, r3 + 8001724: 68bb ldr r3, [r7, #8] + 8001726: f003 0304 and.w r3, r3, #4 + 800172a: 6879 ldr r1, [r7, #4] + 800172c: fa01 f303 lsl.w r3, r1, r3 + 8001730: 431a orrs r2, r3 + 8001732: 68fb ldr r3, [r7, #12] + 8001734: 615a str r2, [r3, #20] ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK), SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); } - 800192a: bf00 nop - 800192c: 3714 adds r7, #20 - 800192e: 46bd mov sp, r7 - 8001930: bc80 pop {r7} - 8001932: 4770 bx lr + 8001736: bf00 nop + 8001738: 3714 adds r7, #20 + 800173a: 46bd mov sp, r7 + 800173c: bc80 pop {r7} + 800173e: 4770 bx lr -08001934 : +08001740 : * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 */ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY) { - 8001934: b480 push {r7} - 8001936: b083 sub sp, #12 - 8001938: af00 add r7, sp, #0 - 800193a: 6078 str r0, [r7, #4] - 800193c: 6039 str r1, [r7, #0] + 8001740: b480 push {r7} + 8001742: b083 sub sp, #12 + 8001744: af00 add r7, sp, #0 + 8001746: 6078 str r0, [r7, #4] + 8001748: 6039 str r1, [r7, #0] return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK))) - 800193e: 687b ldr r3, [r7, #4] - 8001940: 695a ldr r2, [r3, #20] - 8001942: 683b ldr r3, [r7, #0] - 8001944: f003 0304 and.w r3, r3, #4 - 8001948: 2107 movs r1, #7 - 800194a: fa01 f303 lsl.w r3, r1, r3 - 800194e: 401a ands r2, r3 + 800174a: 687b ldr r3, [r7, #4] + 800174c: 695a ldr r2, [r3, #20] + 800174e: 683b ldr r3, [r7, #0] + 8001750: f003 0304 and.w r3, r3, #4 + 8001754: 2107 movs r1, #7 + 8001756: fa01 f303 lsl.w r3, r1, r3 + 800175a: 401a ands r2, r3 >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); - 8001950: 683b ldr r3, [r7, #0] - 8001952: f003 0304 and.w r3, r3, #4 + 800175c: 683b ldr r3, [r7, #0] + 800175e: f003 0304 and.w r3, r3, #4 return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK))) - 8001956: fa22 f303 lsr.w r3, r2, r3 + 8001762: fa22 f303 lsr.w r3, r2, r3 } - 800195a: 4618 mov r0, r3 - 800195c: 370c adds r7, #12 - 800195e: 46bd mov sp, r7 - 8001960: bc80 pop {r7} - 8001962: 4770 bx lr + 8001766: 4618 mov r0, r3 + 8001768: 370c adds r7, #12 + 800176a: 46bd mov sp, r7 + 800176c: bc80 pop {r7} + 800176e: 4770 bx lr -08001964 : +08001770 : * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) { - 8001964: b480 push {r7} - 8001966: b083 sub sp, #12 - 8001968: af00 add r7, sp, #0 - 800196a: 6078 str r0, [r7, #4] + 8001770: b480 push {r7} + 8001772: b083 sub sp, #12 + 8001774: af00 add r7, sp, #0 + 8001776: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, - 800196c: 687b ldr r3, [r7, #4] - 800196e: 689b ldr r3, [r3, #8] - 8001970: f023 4310 bic.w r3, r3, #2415919104 ; 0x90000000 - 8001974: f023 0317 bic.w r3, r3, #23 - 8001978: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000 - 800197c: 687b ldr r3, [r7, #4] - 800197e: 609a str r2, [r3, #8] + 8001778: 687b ldr r3, [r7, #4] + 800177a: 689b ldr r3, [r3, #8] + 800177c: f023 4310 bic.w r3, r3, #2415919104 ; 0x90000000 + 8001780: f023 0317 bic.w r3, r3, #23 + 8001784: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000 + 8001788: 687b ldr r3, [r7, #4] + 800178a: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN); } - 8001980: bf00 nop - 8001982: 370c adds r7, #12 - 8001984: 46bd mov sp, r7 - 8001986: bc80 pop {r7} - 8001988: 4770 bx lr + 800178c: bf00 nop + 800178e: 370c adds r7, #12 + 8001790: 46bd mov sp, r7 + 8001792: bc80 pop {r7} + 8001794: 4770 bx lr -0800198a : +08001796 : * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) { - 800198a: b480 push {r7} - 800198c: b083 sub sp, #12 - 800198e: af00 add r7, sp, #0 - 8001990: 6078 str r0, [r7, #4] + 8001796: b480 push {r7} + 8001798: b083 sub sp, #12 + 800179a: af00 add r7, sp, #0 + 800179c: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); - 8001992: 687b ldr r3, [r7, #4] - 8001994: 689b ldr r3, [r3, #8] - 8001996: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 800199a: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 - 800199e: d101 bne.n 80019a4 - 80019a0: 2301 movs r3, #1 - 80019a2: e000 b.n 80019a6 - 80019a4: 2300 movs r3, #0 -} - 80019a6: 4618 mov r0, r3 - 80019a8: 370c adds r7, #12 - 80019aa: 46bd mov sp, r7 - 80019ac: bc80 pop {r7} - 80019ae: 4770 bx lr - -080019b0 : + 800179e: 687b ldr r3, [r7, #4] + 80017a0: 689b ldr r3, [r3, #8] + 80017a2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 80017a6: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 + 80017aa: d101 bne.n 80017b0 + 80017ac: 2301 movs r3, #1 + 80017ae: e000 b.n 80017b2 + 80017b0: 2300 movs r3, #0 +} + 80017b2: 4618 mov r0, r3 + 80017b4: 370c adds r7, #12 + 80017b6: 46bd mov sp, r7 + 80017b8: bc80 pop {r7} + 80017ba: 4770 bx lr + +080017bc : * @rmtoll CR ADEN LL_ADC_IsEnabled * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) { - 80019b0: b480 push {r7} - 80019b2: b083 sub sp, #12 - 80019b4: af00 add r7, sp, #0 - 80019b6: 6078 str r0, [r7, #4] + 80017bc: b480 push {r7} + 80017be: b083 sub sp, #12 + 80017c0: af00 add r7, sp, #0 + 80017c2: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); - 80019b8: 687b ldr r3, [r7, #4] - 80019ba: 689b ldr r3, [r3, #8] - 80019bc: f003 0301 and.w r3, r3, #1 - 80019c0: 2b01 cmp r3, #1 - 80019c2: d101 bne.n 80019c8 - 80019c4: 2301 movs r3, #1 - 80019c6: e000 b.n 80019ca - 80019c8: 2300 movs r3, #0 -} - 80019ca: 4618 mov r0, r3 - 80019cc: 370c adds r7, #12 - 80019ce: 46bd mov sp, r7 - 80019d0: bc80 pop {r7} - 80019d2: 4770 bx lr - -080019d4 : + 80017c4: 687b ldr r3, [r7, #4] + 80017c6: 689b ldr r3, [r3, #8] + 80017c8: f003 0301 and.w r3, r3, #1 + 80017cc: 2b01 cmp r3, #1 + 80017ce: d101 bne.n 80017d4 + 80017d0: 2301 movs r3, #1 + 80017d2: e000 b.n 80017d6 + 80017d4: 2300 movs r3, #0 +} + 80017d6: 4618 mov r0, r3 + 80017d8: 370c adds r7, #12 + 80017da: 46bd mov sp, r7 + 80017dc: bc80 pop {r7} + 80017de: 4770 bx lr + +080017e0 : * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) { - 80019d4: b480 push {r7} - 80019d6: b083 sub sp, #12 - 80019d8: af00 add r7, sp, #0 - 80019da: 6078 str r0, [r7, #4] + 80017e0: b480 push {r7} + 80017e2: b083 sub sp, #12 + 80017e4: af00 add r7, sp, #0 + 80017e6: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); - 80019dc: 687b ldr r3, [r7, #4] - 80019de: 689b ldr r3, [r3, #8] - 80019e0: f003 0304 and.w r3, r3, #4 - 80019e4: 2b04 cmp r3, #4 - 80019e6: d101 bne.n 80019ec - 80019e8: 2301 movs r3, #1 - 80019ea: e000 b.n 80019ee - 80019ec: 2300 movs r3, #0 -} - 80019ee: 4618 mov r0, r3 - 80019f0: 370c adds r7, #12 - 80019f2: 46bd mov sp, r7 - 80019f4: bc80 pop {r7} - 80019f6: 4770 bx lr - -080019f8 : + 80017e8: 687b ldr r3, [r7, #4] + 80017ea: 689b ldr r3, [r3, #8] + 80017ec: f003 0304 and.w r3, r3, #4 + 80017f0: 2b04 cmp r3, #4 + 80017f2: d101 bne.n 80017f8 + 80017f4: 2301 movs r3, #1 + 80017f6: e000 b.n 80017fa + 80017f8: 2300 movs r3, #0 +} + 80017fa: 4618 mov r0, r3 + 80017fc: 370c adds r7, #12 + 80017fe: 46bd mov sp, r7 + 8001800: bc80 pop {r7} + 8001802: 4770 bx lr + +08001804 : * of structure "ADC_InitTypeDef". * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { - 80019f8: b580 push {r7, lr} - 80019fa: b088 sub sp, #32 - 80019fc: af00 add r7, sp, #0 - 80019fe: 6078 str r0, [r7, #4] + 8001804: b580 push {r7, lr} + 8001806: b088 sub sp, #32 + 8001808: af00 add r7, sp, #0 + 800180a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; - 8001a00: 2300 movs r3, #0 - 8001a02: 77fb strb r3, [r7, #31] + 800180c: 2300 movs r3, #0 + 800180e: 77fb strb r3, [r7, #31] uint32_t tmpCFGR1 = 0UL; - 8001a04: 2300 movs r3, #0 - 8001a06: 61bb str r3, [r7, #24] + 8001810: 2300 movs r3, #0 + 8001812: 61bb str r3, [r7, #24] uint32_t tmpCFGR2 = 0UL; - 8001a08: 2300 movs r3, #0 - 8001a0a: 617b str r3, [r7, #20] + 8001814: 2300 movs r3, #0 + 8001816: 617b str r3, [r7, #20] uint32_t tmp_adc_reg_is_conversion_on_going; __IO uint32_t wait_loop_index = 0UL; - 8001a0c: 2300 movs r3, #0 - 8001a0e: 60fb str r3, [r7, #12] + 8001818: 2300 movs r3, #0 + 800181a: 60fb str r3, [r7, #12] /* Check ADC handle */ if (hadc == NULL) - 8001a10: 687b ldr r3, [r7, #4] - 8001a12: 2b00 cmp r3, #0 - 8001a14: d101 bne.n 8001a1a + 800181c: 687b ldr r3, [r7, #4] + 800181e: 2b00 cmp r3, #0 + 8001820: d101 bne.n 8001826 { return HAL_ERROR; - 8001a16: 2301 movs r3, #1 - 8001a18: e17e b.n 8001d18 + 8001822: 2301 movs r3, #1 + 8001824: e17e b.n 8001b24 assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); } assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) - 8001a1a: 687b ldr r3, [r7, #4] - 8001a1c: 691b ldr r3, [r3, #16] - 8001a1e: 2b00 cmp r3, #0 + 8001826: 687b ldr r3, [r7, #4] + 8001828: 691b ldr r3, [r3, #16] + 800182a: 2b00 cmp r3, #0 /* continuous mode is disabled. */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) - 8001a20: 687b ldr r3, [r7, #4] - 8001a22: 6d9b ldr r3, [r3, #88] ; 0x58 - 8001a24: 2b00 cmp r3, #0 - 8001a26: d109 bne.n 8001a3c + 800182c: 687b ldr r3, [r7, #4] + 800182e: 6d9b ldr r3, [r3, #88] ; 0x58 + 8001830: 2b00 cmp r3, #0 + 8001832: d109 bne.n 8001848 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); - 8001a28: 6878 ldr r0, [r7, #4] - 8001a2a: f7ff fdf9 bl 8001620 + 8001834: 6878 ldr r0, [r7, #4] + 8001836: f7ff fdf9 bl 800142c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); - 8001a2e: 687b ldr r3, [r7, #4] - 8001a30: 2200 movs r2, #0 - 8001a32: 65da str r2, [r3, #92] ; 0x5c + 800183a: 687b ldr r3, [r7, #4] + 800183c: 2200 movs r2, #0 + 800183e: 65da str r2, [r3, #92] ; 0x5c /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; - 8001a34: 687b ldr r3, [r7, #4] - 8001a36: 2200 movs r2, #0 - 8001a38: f883 2054 strb.w r2, [r3, #84] ; 0x54 + 8001840: 687b ldr r3, [r7, #4] + 8001842: 2200 movs r2, #0 + 8001844: f883 2054 strb.w r2, [r3, #84] ; 0x54 } if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) - 8001a3c: 687b ldr r3, [r7, #4] - 8001a3e: 681b ldr r3, [r3, #0] - 8001a40: 4618 mov r0, r3 - 8001a42: f7ff ffa2 bl 800198a - 8001a46: 4603 mov r3, r0 - 8001a48: 2b00 cmp r3, #0 - 8001a4a: d115 bne.n 8001a78 + 8001848: 687b ldr r3, [r7, #4] + 800184a: 681b ldr r3, [r3, #0] + 800184c: 4618 mov r0, r3 + 800184e: f7ff ffa2 bl 8001796 + 8001852: 4603 mov r3, r0 + 8001854: 2b00 cmp r3, #0 + 8001856: d115 bne.n 8001884 { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); - 8001a4c: 687b ldr r3, [r7, #4] - 8001a4e: 681b ldr r3, [r3, #0] - 8001a50: 4618 mov r0, r3 - 8001a52: f7ff ff87 bl 8001964 + 8001858: 687b ldr r3, [r7, #4] + 800185a: 681b ldr r3, [r3, #0] + 800185c: 4618 mov r0, r3 + 800185e: f7ff ff87 bl 8001770 /* Delay for ADC stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); - 8001a56: 4b9e ldr r3, [pc, #632] ; (8001cd0 ) - 8001a58: 681b ldr r3, [r3, #0] - 8001a5a: 099b lsrs r3, r3, #6 - 8001a5c: 4a9d ldr r2, [pc, #628] ; (8001cd4 ) - 8001a5e: fba2 2303 umull r2, r3, r2, r3 - 8001a62: 099b lsrs r3, r3, #6 - 8001a64: 3301 adds r3, #1 - 8001a66: 005b lsls r3, r3, #1 - 8001a68: 60fb str r3, [r7, #12] + 8001862: 4b9e ldr r3, [pc, #632] ; (8001adc ) + 8001864: 681b ldr r3, [r3, #0] + 8001866: 099b lsrs r3, r3, #6 + 8001868: 4a9d ldr r2, [pc, #628] ; (8001ae0 ) + 800186a: fba2 2303 umull r2, r3, r2, r3 + 800186e: 099b lsrs r3, r3, #6 + 8001870: 3301 adds r3, #1 + 8001872: 005b lsls r3, r3, #1 + 8001874: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) - 8001a6a: e002 b.n 8001a72 + 8001876: e002 b.n 800187e { wait_loop_index--; - 8001a6c: 68fb ldr r3, [r7, #12] - 8001a6e: 3b01 subs r3, #1 - 8001a70: 60fb str r3, [r7, #12] + 8001878: 68fb ldr r3, [r7, #12] + 800187a: 3b01 subs r3, #1 + 800187c: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) - 8001a72: 68fb ldr r3, [r7, #12] - 8001a74: 2b00 cmp r3, #0 - 8001a76: d1f9 bne.n 8001a6c + 800187e: 68fb ldr r3, [r7, #12] + 8001880: 2b00 cmp r3, #0 + 8001882: d1f9 bne.n 8001878 } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) - 8001a78: 687b ldr r3, [r7, #4] - 8001a7a: 681b ldr r3, [r3, #0] - 8001a7c: 4618 mov r0, r3 - 8001a7e: f7ff ff84 bl 800198a - 8001a82: 4603 mov r3, r0 - 8001a84: 2b00 cmp r3, #0 - 8001a86: d10d bne.n 8001aa4 + 8001884: 687b ldr r3, [r7, #4] + 8001886: 681b ldr r3, [r3, #0] + 8001888: 4618 mov r0, r3 + 800188a: f7ff ff84 bl 8001796 + 800188e: 4603 mov r3, r0 + 8001890: 2b00 cmp r3, #0 + 8001892: d10d bne.n 80018b0 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 8001a88: 687b ldr r3, [r7, #4] - 8001a8a: 6d9b ldr r3, [r3, #88] ; 0x58 - 8001a8c: f043 0210 orr.w r2, r3, #16 - 8001a90: 687b ldr r3, [r7, #4] - 8001a92: 659a str r2, [r3, #88] ; 0x58 + 8001894: 687b ldr r3, [r7, #4] + 8001896: 6d9b ldr r3, [r3, #88] ; 0x58 + 8001898: f043 0210 orr.w r2, r3, #16 + 800189c: 687b ldr r3, [r7, #4] + 800189e: 659a str r2, [r3, #88] ; 0x58 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8001a94: 687b ldr r3, [r7, #4] - 8001a96: 6ddb ldr r3, [r3, #92] ; 0x5c - 8001a98: f043 0201 orr.w r2, r3, #1 - 8001a9c: 687b ldr r3, [r7, #4] - 8001a9e: 65da str r2, [r3, #92] ; 0x5c + 80018a0: 687b ldr r3, [r7, #4] + 80018a2: 6ddb ldr r3, [r3, #92] ; 0x5c + 80018a4: f043 0201 orr.w r2, r3, #1 + 80018a8: 687b ldr r3, [r7, #4] + 80018aa: 65da str r2, [r3, #92] ; 0x5c tmp_hal_status = HAL_ERROR; - 8001aa0: 2301 movs r3, #1 - 8001aa2: 77fb strb r3, [r7, #31] + 80018ac: 2301 movs r3, #1 + 80018ae: 77fb strb r3, [r7, #31] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - 8001aa4: 687b ldr r3, [r7, #4] - 8001aa6: 681b ldr r3, [r3, #0] - 8001aa8: 4618 mov r0, r3 - 8001aaa: f7ff ff93 bl 80019d4 - 8001aae: 6138 str r0, [r7, #16] + 80018b0: 687b ldr r3, [r7, #4] + 80018b2: 681b ldr r3, [r3, #0] + 80018b4: 4618 mov r0, r3 + 80018b6: f7ff ff93 bl 80017e0 + 80018ba: 6138 str r0, [r7, #16] if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) - 8001ab0: 687b ldr r3, [r7, #4] - 8001ab2: 6d9b ldr r3, [r3, #88] ; 0x58 - 8001ab4: f003 0310 and.w r3, r3, #16 - 8001ab8: 2b00 cmp r3, #0 - 8001aba: f040 8124 bne.w 8001d06 + 80018bc: 687b ldr r3, [r7, #4] + 80018be: 6d9b ldr r3, [r3, #88] ; 0x58 + 80018c0: f003 0310 and.w r3, r3, #16 + 80018c4: 2b00 cmp r3, #0 + 80018c6: f040 8124 bne.w 8001b12 && (tmp_adc_reg_is_conversion_on_going == 0UL) - 8001abe: 693b ldr r3, [r7, #16] - 8001ac0: 2b00 cmp r3, #0 - 8001ac2: f040 8120 bne.w 8001d06 + 80018ca: 693b ldr r3, [r7, #16] + 80018cc: 2b00 cmp r3, #0 + 80018ce: f040 8120 bne.w 8001b12 ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, - 8001ac6: 687b ldr r3, [r7, #4] - 8001ac8: 6d9b ldr r3, [r3, #88] ; 0x58 - 8001aca: f423 7381 bic.w r3, r3, #258 ; 0x102 - 8001ace: f043 0202 orr.w r2, r3, #2 - 8001ad2: 687b ldr r3, [r7, #4] - 8001ad4: 659a str r2, [r3, #88] ; 0x58 + 80018d2: 687b ldr r3, [r7, #4] + 80018d4: 6d9b ldr r3, [r3, #88] ; 0x58 + 80018d6: f423 7381 bic.w r3, r3, #258 ; 0x102 + 80018da: f043 0202 orr.w r2, r3, #2 + 80018de: 687b ldr r3, [r7, #4] + 80018e0: 659a str r2, [r3, #88] ; 0x58 /* - DMA continuous request */ /* - Trigger frequency mode */ /* Note: If low power mode AutoPowerOff is enabled, ADC enable */ /* and disable phases are performed automatically by hardware */ /* (in this case, flag ADC_FLAG_RDY is not set). */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - 8001ad6: 687b ldr r3, [r7, #4] - 8001ad8: 681b ldr r3, [r3, #0] - 8001ada: 4618 mov r0, r3 - 8001adc: f7ff ff68 bl 80019b0 - 8001ae0: 4603 mov r3, r0 - 8001ae2: 2b00 cmp r3, #0 - 8001ae4: f040 80a7 bne.w 8001c36 + 80018e2: 687b ldr r3, [r7, #4] + 80018e4: 681b ldr r3, [r3, #0] + 80018e6: 4618 mov r0, r3 + 80018e8: f7ff ff68 bl 80017bc + 80018ec: 4603 mov r3, r0 + 80018ee: 2b00 cmp r3, #0 + 80018f0: f040 80a7 bne.w 8001a42 /* without needing to reconfigure all other ADC groups/channels */ /* parameters): */ /* - internal measurement paths (VrefInt, ...) */ /* (set into HAL_ADC_ConfigChannel() ) */ tmpCFGR1 |= (hadc->Init.Resolution | - 8001ae8: 687b ldr r3, [r7, #4] - 8001aea: 689a ldr r2, [r3, #8] + 80018f4: 687b ldr r3, [r7, #4] + 80018f6: 689a ldr r2, [r3, #8] ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | - 8001aec: 687b ldr r3, [r7, #4] - 8001aee: 7e1b ldrb r3, [r3, #24] - 8001af0: 039b lsls r3, r3, #14 + 80018f8: 687b ldr r3, [r7, #4] + 80018fa: 7e1b ldrb r3, [r3, #24] + 80018fc: 039b lsls r3, r3, #14 tmpCFGR1 |= (hadc->Init.Resolution | - 8001af2: 431a orrs r2, r3 + 80018fe: 431a orrs r2, r3 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | - 8001af4: 687b ldr r3, [r7, #4] - 8001af6: 7e5b ldrb r3, [r3, #25] - 8001af8: 03db lsls r3, r3, #15 + 8001900: 687b ldr r3, [r7, #4] + 8001902: 7e5b ldrb r3, [r3, #25] + 8001904: 03db lsls r3, r3, #15 ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | - 8001afa: 431a orrs r2, r3 + 8001906: 431a orrs r2, r3 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | - 8001afc: 687b ldr r3, [r7, #4] - 8001afe: 7e9b ldrb r3, [r3, #26] - 8001b00: 035b lsls r3, r3, #13 + 8001908: 687b ldr r3, [r7, #4] + 800190a: 7e9b ldrb r3, [r3, #26] + 800190c: 035b lsls r3, r3, #13 ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | - 8001b02: 4313 orrs r3, r2 + 800190e: 4313 orrs r3, r2 ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | - 8001b04: 687a ldr r2, [r7, #4] - 8001b06: 6b12 ldr r2, [r2, #48] ; 0x30 - 8001b08: 2a00 cmp r2, #0 - 8001b0a: d002 beq.n 8001b12 - 8001b0c: f44f 5280 mov.w r2, #4096 ; 0x1000 - 8001b10: e000 b.n 8001b14 - 8001b12: 2200 movs r2, #0 + 8001910: 687a ldr r2, [r7, #4] + 8001912: 6b12 ldr r2, [r2, #48] ; 0x30 + 8001914: 2a00 cmp r2, #0 + 8001916: d002 beq.n 800191e + 8001918: f44f 5280 mov.w r2, #4096 ; 0x1000 + 800191c: e000 b.n 8001920 + 800191e: 2200 movs r2, #0 ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | - 8001b14: 431a orrs r2, r3 + 8001920: 431a orrs r2, r3 hadc->Init.DataAlign | - 8001b16: 687b ldr r3, [r7, #4] - 8001b18: 68db ldr r3, [r3, #12] + 8001922: 687b ldr r3, [r7, #4] + 8001924: 68db ldr r3, [r3, #12] ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | - 8001b1a: 431a orrs r2, r3 + 8001926: 431a orrs r2, r3 ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) | - 8001b1c: 687b ldr r3, [r7, #4] - 8001b1e: 691b ldr r3, [r3, #16] - 8001b20: 2b00 cmp r3, #0 - 8001b22: da04 bge.n 8001b2e - 8001b24: 687b ldr r3, [r7, #4] - 8001b26: 691b ldr r3, [r3, #16] - 8001b28: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 - 8001b2c: e001 b.n 8001b32 - 8001b2e: f44f 1300 mov.w r3, #2097152 ; 0x200000 + 8001928: 687b ldr r3, [r7, #4] + 800192a: 691b ldr r3, [r3, #16] + 800192c: 2b00 cmp r3, #0 + 800192e: da04 bge.n 800193a + 8001930: 687b ldr r3, [r7, #4] + 8001932: 691b ldr r3, [r3, #16] + 8001934: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 + 8001938: e001 b.n 800193e + 800193a: f44f 1300 mov.w r3, #2097152 ; 0x200000 hadc->Init.DataAlign | - 8001b32: 431a orrs r2, r3 + 800193e: 431a orrs r2, r3 ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); - 8001b34: 687b ldr r3, [r7, #4] - 8001b36: f893 302c ldrb.w r3, [r3, #44] ; 0x2c - 8001b3a: 005b lsls r3, r3, #1 + 8001940: 687b ldr r3, [r7, #4] + 8001942: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 8001946: 005b lsls r3, r3, #1 ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) | - 8001b3c: 4313 orrs r3, r2 + 8001948: 4313 orrs r3, r2 tmpCFGR1 |= (hadc->Init.Resolution | - 8001b3e: 69ba ldr r2, [r7, #24] - 8001b40: 4313 orrs r3, r2 - 8001b42: 61bb str r3, [r7, #24] + 800194a: 69ba ldr r2, [r7, #24] + 800194c: 4313 orrs r3, r2 + 800194e: 61bb str r3, [r7, #24] /* Update setting of discontinuous mode only if continuous mode is disabled */ if (hadc->Init.DiscontinuousConvMode == ENABLE) - 8001b44: 687b ldr r3, [r7, #4] - 8001b46: f893 3020 ldrb.w r3, [r3, #32] - 8001b4a: 2b01 cmp r3, #1 - 8001b4c: d114 bne.n 8001b78 + 8001950: 687b ldr r3, [r7, #4] + 8001952: f893 3020 ldrb.w r3, [r3, #32] + 8001956: 2b01 cmp r3, #1 + 8001958: d114 bne.n 8001984 { if (hadc->Init.ContinuousConvMode == DISABLE) - 8001b4e: 687b ldr r3, [r7, #4] - 8001b50: 7e9b ldrb r3, [r3, #26] - 8001b52: 2b00 cmp r3, #0 - 8001b54: d104 bne.n 8001b60 + 800195a: 687b ldr r3, [r7, #4] + 800195c: 7e9b ldrb r3, [r3, #26] + 800195e: 2b00 cmp r3, #0 + 8001960: d104 bne.n 800196c { /* Enable the selected ADC group regular discontinuous mode */ tmpCFGR1 |= ADC_CFGR1_DISCEN; - 8001b56: 69bb ldr r3, [r7, #24] - 8001b58: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 8001b5c: 61bb str r3, [r7, #24] - 8001b5e: e00b b.n 8001b78 + 8001962: 69bb ldr r3, [r7, #24] + 8001964: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8001968: 61bb str r3, [r7, #24] + 800196a: e00b b.n 8001984 /* ADC regular group discontinuous was intended to be enabled, */ /* but ADC regular group modes continuous and sequencer discontinuous */ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - 8001b60: 687b ldr r3, [r7, #4] - 8001b62: 6d9b ldr r3, [r3, #88] ; 0x58 - 8001b64: f043 0220 orr.w r2, r3, #32 - 8001b68: 687b ldr r3, [r7, #4] - 8001b6a: 659a str r2, [r3, #88] ; 0x58 + 800196c: 687b ldr r3, [r7, #4] + 800196e: 6d9b ldr r3, [r3, #88] ; 0x58 + 8001970: f043 0220 orr.w r2, r3, #32 + 8001974: 687b ldr r3, [r7, #4] + 8001976: 659a str r2, [r3, #88] ; 0x58 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8001b6c: 687b ldr r3, [r7, #4] - 8001b6e: 6ddb ldr r3, [r3, #92] ; 0x5c - 8001b70: f043 0201 orr.w r2, r3, #1 - 8001b74: 687b ldr r3, [r7, #4] - 8001b76: 65da str r2, [r3, #92] ; 0x5c + 8001978: 687b ldr r3, [r7, #4] + 800197a: 6ddb ldr r3, [r3, #92] ; 0x5c + 800197c: f043 0201 orr.w r2, r3, #1 + 8001980: 687b ldr r3, [r7, #4] + 8001982: 65da str r2, [r3, #92] ; 0x5c /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) - 8001b78: 687b ldr r3, [r7, #4] - 8001b7a: 6a5b ldr r3, [r3, #36] ; 0x24 - 8001b7c: 2b00 cmp r3, #0 - 8001b7e: d009 beq.n 8001b94 + 8001984: 687b ldr r3, [r7, #4] + 8001986: 6a5b ldr r3, [r3, #36] ; 0x24 + 8001988: 2b00 cmp r3, #0 + 800198a: d009 beq.n 80019a0 { tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) | - 8001b80: 687b ldr r3, [r7, #4] - 8001b82: 6a5b ldr r3, [r3, #36] ; 0x24 - 8001b84: f403 72e0 and.w r2, r3, #448 ; 0x1c0 + 800198c: 687b ldr r3, [r7, #4] + 800198e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8001990: f403 72e0 and.w r2, r3, #448 ; 0x1c0 hadc->Init.ExternalTrigConvEdge); - 8001b88: 687b ldr r3, [r7, #4] - 8001b8a: 6a9b ldr r3, [r3, #40] ; 0x28 + 8001994: 687b ldr r3, [r7, #4] + 8001996: 6a9b ldr r3, [r3, #40] ; 0x28 tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) | - 8001b8c: 4313 orrs r3, r2 - 8001b8e: 69ba ldr r2, [r7, #24] - 8001b90: 4313 orrs r3, r2 - 8001b92: 61bb str r3, [r7, #24] + 8001998: 4313 orrs r3, r2 + 800199a: 69ba ldr r2, [r7, #24] + 800199c: 4313 orrs r3, r2 + 800199e: 61bb str r3, [r7, #24] } /* Update ADC configuration register with previous settings */ MODIFY_REG(hadc->Instance->CFGR1, - 8001b94: 687b ldr r3, [r7, #4] - 8001b96: 681b ldr r3, [r3, #0] - 8001b98: 68db ldr r3, [r3, #12] - 8001b9a: f423 33fe bic.w r3, r3, #130048 ; 0x1fc00 - 8001b9e: f423 73ff bic.w r3, r3, #510 ; 0x1fe - 8001ba2: 687a ldr r2, [r7, #4] - 8001ba4: 6812 ldr r2, [r2, #0] - 8001ba6: 69b9 ldr r1, [r7, #24] - 8001ba8: 430b orrs r3, r1 - 8001baa: 60d3 str r3, [r2, #12] + 80019a0: 687b ldr r3, [r7, #4] + 80019a2: 681b ldr r3, [r3, #0] + 80019a4: 68db ldr r3, [r3, #12] + 80019a6: f423 33fe bic.w r3, r3, #130048 ; 0x1fc00 + 80019aa: f423 73ff bic.w r3, r3, #510 ; 0x1fe + 80019ae: 687a ldr r2, [r7, #4] + 80019b0: 6812 ldr r2, [r2, #0] + 80019b2: 69b9 ldr r1, [r7, #24] + 80019b4: 430b orrs r3, r1 + 80019b6: 60d3 str r3, [r2, #12] ADC_CFGR1_ALIGN | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG, tmpCFGR1); tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | - 8001bac: 687b ldr r3, [r7, #4] - 8001bae: 685b ldr r3, [r3, #4] - 8001bb0: f003 4240 and.w r2, r3, #3221225472 ; 0xc0000000 + 80019b8: 687b ldr r3, [r7, #4] + 80019ba: 685b ldr r3, [r3, #4] + 80019bc: f003 4240 and.w r2, r3, #3221225472 ; 0xc0000000 hadc->Init.TriggerFrequencyMode - 8001bb4: 687b ldr r3, [r7, #4] - 8001bb6: 6cdb ldr r3, [r3, #76] ; 0x4c + 80019c0: 687b ldr r3, [r7, #4] + 80019c2: 6cdb ldr r3, [r3, #76] ; 0x4c tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | - 8001bb8: 4313 orrs r3, r2 - 8001bba: 697a ldr r2, [r7, #20] - 8001bbc: 4313 orrs r3, r2 - 8001bbe: 617b str r3, [r7, #20] + 80019c4: 4313 orrs r3, r2 + 80019c6: 697a ldr r2, [r7, #20] + 80019c8: 4313 orrs r3, r2 + 80019ca: 617b str r3, [r7, #20] ); if (hadc->Init.OversamplingMode == ENABLE) - 8001bc0: 687b ldr r3, [r7, #4] - 8001bc2: f893 303c ldrb.w r3, [r3, #60] ; 0x3c - 8001bc6: 2b01 cmp r3, #1 - 8001bc8: d111 bne.n 8001bee + 80019cc: 687b ldr r3, [r7, #4] + 80019ce: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 80019d2: 2b01 cmp r3, #1 + 80019d4: d111 bne.n 80019fa { tmpCFGR2 |= (ADC_CFGR2_OVSE | (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | - 8001bca: 687b ldr r3, [r7, #4] - 8001bcc: 685b ldr r3, [r3, #4] - 8001bce: f003 4240 and.w r2, r3, #3221225472 ; 0xc0000000 + 80019d6: 687b ldr r3, [r7, #4] + 80019d8: 685b ldr r3, [r3, #4] + 80019da: f003 4240 and.w r2, r3, #3221225472 ; 0xc0000000 hadc->Init.Oversampling.Ratio | - 8001bd2: 687b ldr r3, [r7, #4] - 8001bd4: 6c1b ldr r3, [r3, #64] ; 0x40 + 80019de: 687b ldr r3, [r7, #4] + 80019e0: 6c1b ldr r3, [r3, #64] ; 0x40 (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | - 8001bd6: 431a orrs r2, r3 + 80019e2: 431a orrs r2, r3 hadc->Init.Oversampling.RightBitShift | - 8001bd8: 687b ldr r3, [r7, #4] - 8001bda: 6c5b ldr r3, [r3, #68] ; 0x44 + 80019e4: 687b ldr r3, [r7, #4] + 80019e6: 6c5b ldr r3, [r3, #68] ; 0x44 hadc->Init.Oversampling.Ratio | - 8001bdc: 431a orrs r2, r3 + 80019e8: 431a orrs r2, r3 hadc->Init.Oversampling.TriggeredMode - 8001bde: 687b ldr r3, [r7, #4] - 8001be0: 6c9b ldr r3, [r3, #72] ; 0x48 + 80019ea: 687b ldr r3, [r7, #4] + 80019ec: 6c9b ldr r3, [r3, #72] ; 0x48 hadc->Init.Oversampling.RightBitShift | - 8001be2: 431a orrs r2, r3 + 80019ee: 431a orrs r2, r3 tmpCFGR2 |= (ADC_CFGR2_OVSE | - 8001be4: 697b ldr r3, [r7, #20] - 8001be6: 4313 orrs r3, r2 - 8001be8: f043 0301 orr.w r3, r3, #1 - 8001bec: 617b str r3, [r7, #20] + 80019f0: 697b ldr r3, [r7, #20] + 80019f2: 4313 orrs r3, r2 + 80019f4: f043 0301 orr.w r3, r3, #1 + 80019f8: 617b str r3, [r7, #20] ); } MODIFY_REG(hadc->Instance->CFGR2, - 8001bee: 687b ldr r3, [r7, #4] - 8001bf0: 681b ldr r3, [r3, #0] - 8001bf2: 691a ldr r2, [r3, #16] - 8001bf4: 4b38 ldr r3, [pc, #224] ; (8001cd8 ) - 8001bf6: 4013 ands r3, r2 - 8001bf8: 687a ldr r2, [r7, #4] - 8001bfa: 6812 ldr r2, [r2, #0] - 8001bfc: 6979 ldr r1, [r7, #20] - 8001bfe: 430b orrs r3, r1 - 8001c00: 6113 str r3, [r2, #16] + 80019fa: 687b ldr r3, [r7, #4] + 80019fc: 681b ldr r3, [r3, #0] + 80019fe: 691a ldr r2, [r3, #16] + 8001a00: 4b38 ldr r3, [pc, #224] ; (8001ae4 ) + 8001a02: 4013 ands r3, r2 + 8001a04: 687a ldr r2, [r7, #4] + 8001a06: 6812 ldr r2, [r2, #0] + 8001a08: 6979 ldr r1, [r7, #20] + 8001a0a: 430b orrs r3, r1 + 8001a0c: 6113 str r3, [r2, #16] ADC_CFGR2_TOVS, tmpCFGR2); /* Configuration of ADC clock mode: asynchronous clock source */ /* with selectable prescaler. */ if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) && - 8001c02: 687b ldr r3, [r7, #4] - 8001c04: 685b ldr r3, [r3, #4] - 8001c06: f1b3 4f40 cmp.w r3, #3221225472 ; 0xc0000000 - 8001c0a: d014 beq.n 8001c36 + 8001a0e: 687b ldr r3, [r7, #4] + 8001a10: 685b ldr r3, [r3, #4] + 8001a12: f1b3 4f40 cmp.w r3, #3221225472 ; 0xc0000000 + 8001a16: d014 beq.n 8001a42 ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) && - 8001c0c: 687b ldr r3, [r7, #4] - 8001c0e: 685b ldr r3, [r3, #4] + 8001a18: 687b ldr r3, [r7, #4] + 8001a1a: 685b ldr r3, [r3, #4] if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) && - 8001c10: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 - 8001c14: d00f beq.n 8001c36 + 8001a1c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 8001a20: d00f beq.n 8001a42 ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4)) - 8001c16: 687b ldr r3, [r7, #4] - 8001c18: 685b ldr r3, [r3, #4] + 8001a22: 687b ldr r3, [r7, #4] + 8001a24: 685b ldr r3, [r3, #4] ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) && - 8001c1a: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 - 8001c1e: d00a beq.n 8001c36 + 8001a26: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 + 8001a2a: d00a beq.n 8001a42 { MODIFY_REG(ADC_COMMON->CCR, - 8001c20: 4b2e ldr r3, [pc, #184] ; (8001cdc ) - 8001c22: 681b ldr r3, [r3, #0] - 8001c24: f423 1270 bic.w r2, r3, #3932160 ; 0x3c0000 - 8001c28: 687b ldr r3, [r7, #4] - 8001c2a: 685b ldr r3, [r3, #4] - 8001c2c: f403 1370 and.w r3, r3, #3932160 ; 0x3c0000 - 8001c30: 492a ldr r1, [pc, #168] ; (8001cdc ) - 8001c32: 4313 orrs r3, r2 - 8001c34: 600b str r3, [r1, #0] + 8001a2c: 4b2e ldr r3, [pc, #184] ; (8001ae8 ) + 8001a2e: 681b ldr r3, [r3, #0] + 8001a30: f423 1270 bic.w r2, r3, #3932160 ; 0x3c0000 + 8001a34: 687b ldr r3, [r7, #4] + 8001a36: 685b ldr r3, [r3, #4] + 8001a38: f403 1370 and.w r3, r3, #3932160 ; 0x3c0000 + 8001a3c: 492a ldr r1, [pc, #168] ; (8001ae8 ) + 8001a3e: 4313 orrs r3, r2 + 8001a40: 600b str r3, [r1, #0] hadc->Init.ClockPrescaler & ADC_CCR_PRESC); } } /* Channel sampling time configuration */ LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1); - 8001c36: 687b ldr r3, [r7, #4] - 8001c38: 6818 ldr r0, [r3, #0] - 8001c3a: 687b ldr r3, [r7, #4] - 8001c3c: 6b5b ldr r3, [r3, #52] ; 0x34 - 8001c3e: 461a mov r2, r3 - 8001c40: 2100 movs r1, #0 - 8001c42: f7ff fe59 bl 80018f8 + 8001a42: 687b ldr r3, [r7, #4] + 8001a44: 6818 ldr r0, [r3, #0] + 8001a46: 687b ldr r3, [r7, #4] + 8001a48: 6b5b ldr r3, [r3, #52] ; 0x34 + 8001a4a: 461a mov r2, r3 + 8001a4c: 2100 movs r1, #0 + 8001a4e: f7ff fe59 bl 8001704 LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, hadc->Init.SamplingTimeCommon2); - 8001c46: 687b ldr r3, [r7, #4] - 8001c48: 6818 ldr r0, [r3, #0] - 8001c4a: 687b ldr r3, [r7, #4] - 8001c4c: 6b9b ldr r3, [r3, #56] ; 0x38 - 8001c4e: 461a mov r2, r3 - 8001c50: 4923 ldr r1, [pc, #140] ; (8001ce0 ) - 8001c52: f7ff fe51 bl 80018f8 + 8001a52: 687b ldr r3, [r7, #4] + 8001a54: 6818 ldr r0, [r3, #0] + 8001a56: 687b ldr r3, [r7, #4] + 8001a58: 6b9b ldr r3, [r3, #56] ; 0x38 + 8001a5a: 461a mov r2, r3 + 8001a5c: 4923 ldr r1, [pc, #140] ; (8001aec ) + 8001a5e: f7ff fe51 bl 8001704 /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ /* Channels must be configured into each rank using function */ /* "HAL_ADC_ConfigChannel()". */ if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) - 8001c56: 687b ldr r3, [r7, #4] - 8001c58: 691b ldr r3, [r3, #16] - 8001c5a: 2b00 cmp r3, #0 - 8001c5c: d108 bne.n 8001c70 + 8001a62: 687b ldr r3, [r7, #4] + 8001a64: 691b ldr r3, [r3, #16] + 8001a66: 2b00 cmp r3, #0 + 8001a68: d108 bne.n 8001a7c { /* Set sequencer scan length by clearing ranks above rank 1 */ /* and do not modify rank 1 value. */ SET_BIT(hadc->Instance->CHSELR, - 8001c5e: 687b ldr r3, [r7, #4] - 8001c60: 681b ldr r3, [r3, #0] - 8001c62: 6a9a ldr r2, [r3, #40] ; 0x28 - 8001c64: 687b ldr r3, [r7, #4] - 8001c66: 681b ldr r3, [r3, #0] - 8001c68: f062 020f orn r2, r2, #15 - 8001c6c: 629a str r2, [r3, #40] ; 0x28 - 8001c6e: e017 b.n 8001ca0 + 8001a6a: 687b ldr r3, [r7, #4] + 8001a6c: 681b ldr r3, [r3, #0] + 8001a6e: 6a9a ldr r2, [r3, #40] ; 0x28 + 8001a70: 687b ldr r3, [r7, #4] + 8001a72: 681b ldr r3, [r3, #0] + 8001a74: f062 020f orn r2, r2, #15 + 8001a78: 629a str r2, [r3, #40] ; 0x28 + 8001a7a: e017 b.n 8001aac ADC_CHSELR_SQ2_TO_SQ8); } else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) - 8001c70: 687b ldr r3, [r7, #4] - 8001c72: 691b ldr r3, [r3, #16] - 8001c74: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 - 8001c78: d112 bne.n 8001ca0 + 8001a7c: 687b ldr r3, [r7, #4] + 8001a7e: 691b ldr r3, [r3, #16] + 8001a80: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 + 8001a84: d112 bne.n 8001aac /* therefore after the first call of "HAL_ADC_Init()", */ /* each rank corresponding to parameter "NbrOfConversion" */ /* must be set using "HAL_ADC_ConfigChannel()". */ /* - Set sequencer scan length by clearing ranks above maximum rank */ /* and do not modify other ranks value. */ MODIFY_REG(hadc->Instance->CHSELR, - 8001c7a: 687b ldr r3, [r7, #4] - 8001c7c: 681b ldr r3, [r3, #0] - 8001c7e: 6a9b ldr r3, [r3, #40] ; 0x28 - 8001c80: 687b ldr r3, [r7, #4] - 8001c82: 69db ldr r3, [r3, #28] - 8001c84: 3b01 subs r3, #1 - 8001c86: 009b lsls r3, r3, #2 - 8001c88: f003 031c and.w r3, r3, #28 - 8001c8c: f06f 020f mvn.w r2, #15 - 8001c90: fa02 f103 lsl.w r1, r2, r3 - 8001c94: 687b ldr r3, [r7, #4] - 8001c96: 6e1a ldr r2, [r3, #96] ; 0x60 - 8001c98: 687b ldr r3, [r7, #4] - 8001c9a: 681b ldr r3, [r3, #0] - 8001c9c: 430a orrs r2, r1 - 8001c9e: 629a str r2, [r3, #40] ; 0x28 + 8001a86: 687b ldr r3, [r7, #4] + 8001a88: 681b ldr r3, [r3, #0] + 8001a8a: 6a9b ldr r3, [r3, #40] ; 0x28 + 8001a8c: 687b ldr r3, [r7, #4] + 8001a8e: 69db ldr r3, [r3, #28] + 8001a90: 3b01 subs r3, #1 + 8001a92: 009b lsls r3, r3, #2 + 8001a94: f003 031c and.w r3, r3, #28 + 8001a98: f06f 020f mvn.w r2, #15 + 8001a9c: fa02 f103 lsl.w r1, r2, r3 + 8001aa0: 687b ldr r3, [r7, #4] + 8001aa2: 6e1a ldr r2, [r3, #96] ; 0x60 + 8001aa4: 687b ldr r3, [r7, #4] + 8001aa6: 681b ldr r3, [r3, #0] + 8001aa8: 430a orrs r2, r1 + 8001aaa: 629a str r2, [r3, #40] ; 0x28 ); } /* Check back that ADC registers have effectively been configured to */ /* ensure of no potential problem of ADC core peripheral clocking. */ if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1) - 8001ca0: 687b ldr r3, [r7, #4] - 8001ca2: 681b ldr r3, [r3, #0] - 8001ca4: 2100 movs r1, #0 - 8001ca6: 4618 mov r0, r3 - 8001ca8: f7ff fe44 bl 8001934 - 8001cac: 4602 mov r2, r0 + 8001aac: 687b ldr r3, [r7, #4] + 8001aae: 681b ldr r3, [r3, #0] + 8001ab0: 2100 movs r1, #0 + 8001ab2: 4618 mov r0, r3 + 8001ab4: f7ff fe44 bl 8001740 + 8001ab8: 4602 mov r2, r0 == hadc->Init.SamplingTimeCommon1) - 8001cae: 687b ldr r3, [r7, #4] - 8001cb0: 6b5b ldr r3, [r3, #52] ; 0x34 + 8001aba: 687b ldr r3, [r7, #4] + 8001abc: 6b5b ldr r3, [r3, #52] ; 0x34 if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1) - 8001cb2: 429a cmp r2, r3 - 8001cb4: d116 bne.n 8001ce4 + 8001abe: 429a cmp r2, r3 + 8001ac0: d116 bne.n 8001af0 { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); - 8001cb6: 687b ldr r3, [r7, #4] - 8001cb8: 2200 movs r2, #0 - 8001cba: 65da str r2, [r3, #92] ; 0x5c + 8001ac2: 687b ldr r3, [r7, #4] + 8001ac4: 2200 movs r2, #0 + 8001ac6: 65da str r2, [r3, #92] ; 0x5c /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, - 8001cbc: 687b ldr r3, [r7, #4] - 8001cbe: 6d9b ldr r3, [r3, #88] ; 0x58 - 8001cc0: f023 0303 bic.w r3, r3, #3 - 8001cc4: f043 0201 orr.w r2, r3, #1 - 8001cc8: 687b ldr r3, [r7, #4] - 8001cca: 659a str r2, [r3, #88] ; 0x58 + 8001ac8: 687b ldr r3, [r7, #4] + 8001aca: 6d9b ldr r3, [r3, #88] ; 0x58 + 8001acc: f023 0303 bic.w r3, r3, #3 + 8001ad0: f043 0201 orr.w r2, r3, #1 + 8001ad4: 687b ldr r3, [r7, #4] + 8001ad6: 659a str r2, [r3, #88] ; 0x58 if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1) - 8001ccc: e023 b.n 8001d16 - 8001cce: bf00 nop - 8001cd0: 20000008 .word 0x20000008 - 8001cd4: 053e2d63 .word 0x053e2d63 - 8001cd8: 1ffffc02 .word 0x1ffffc02 - 8001cdc: 40012708 .word 0x40012708 - 8001ce0: 03ffff04 .word 0x03ffff04 + 8001ad8: e023 b.n 8001b22 + 8001ada: bf00 nop + 8001adc: 20000000 .word 0x20000000 + 8001ae0: 053e2d63 .word 0x053e2d63 + 8001ae4: 1ffffc02 .word 0x1ffffc02 + 8001ae8: 40012708 .word 0x40012708 + 8001aec: 03ffff04 .word 0x03ffff04 HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, - 8001ce4: 687b ldr r3, [r7, #4] - 8001ce6: 6d9b ldr r3, [r3, #88] ; 0x58 - 8001ce8: f023 0312 bic.w r3, r3, #18 - 8001cec: f043 0210 orr.w r2, r3, #16 - 8001cf0: 687b ldr r3, [r7, #4] - 8001cf2: 659a str r2, [r3, #88] ; 0x58 + 8001af0: 687b ldr r3, [r7, #4] + 8001af2: 6d9b ldr r3, [r3, #88] ; 0x58 + 8001af4: f023 0312 bic.w r3, r3, #18 + 8001af8: f043 0210 orr.w r2, r3, #16 + 8001afc: 687b ldr r3, [r7, #4] + 8001afe: 659a str r2, [r3, #88] ; 0x58 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8001cf4: 687b ldr r3, [r7, #4] - 8001cf6: 6ddb ldr r3, [r3, #92] ; 0x5c - 8001cf8: f043 0201 orr.w r2, r3, #1 - 8001cfc: 687b ldr r3, [r7, #4] - 8001cfe: 65da str r2, [r3, #92] ; 0x5c + 8001b00: 687b ldr r3, [r7, #4] + 8001b02: 6ddb ldr r3, [r3, #92] ; 0x5c + 8001b04: f043 0201 orr.w r2, r3, #1 + 8001b08: 687b ldr r3, [r7, #4] + 8001b0a: 65da str r2, [r3, #92] ; 0x5c tmp_hal_status = HAL_ERROR; - 8001d00: 2301 movs r3, #1 - 8001d02: 77fb strb r3, [r7, #31] + 8001b0c: 2301 movs r3, #1 + 8001b0e: 77fb strb r3, [r7, #31] if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1) - 8001d04: e007 b.n 8001d16 + 8001b10: e007 b.n 8001b22 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 8001d06: 687b ldr r3, [r7, #4] - 8001d08: 6d9b ldr r3, [r3, #88] ; 0x58 - 8001d0a: f043 0210 orr.w r2, r3, #16 - 8001d0e: 687b ldr r3, [r7, #4] - 8001d10: 659a str r2, [r3, #88] ; 0x58 + 8001b12: 687b ldr r3, [r7, #4] + 8001b14: 6d9b ldr r3, [r3, #88] ; 0x58 + 8001b16: f043 0210 orr.w r2, r3, #16 + 8001b1a: 687b ldr r3, [r7, #4] + 8001b1c: 659a str r2, [r3, #88] ; 0x58 tmp_hal_status = HAL_ERROR; - 8001d12: 2301 movs r3, #1 - 8001d14: 77fb strb r3, [r7, #31] + 8001b1e: 2301 movs r3, #1 + 8001b20: 77fb strb r3, [r7, #31] } return tmp_hal_status; - 8001d16: 7ffb ldrb r3, [r7, #31] + 8001b22: 7ffb ldrb r3, [r7, #31] } - 8001d18: 4618 mov r0, r3 - 8001d1a: 3720 adds r7, #32 - 8001d1c: 46bd mov sp, r7 - 8001d1e: bd80 pop {r7, pc} + 8001b24: 4618 mov r0, r3 + 8001b26: 3720 adds r7, #32 + 8001b28: 46bd mov sp, r7 + 8001b2a: bd80 pop {r7, pc} -08001d20 <__NVIC_SetPriorityGrouping>: +08001b2c <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 8001d20: b480 push {r7} - 8001d22: b085 sub sp, #20 - 8001d24: af00 add r7, sp, #0 - 8001d26: 6078 str r0, [r7, #4] + 8001b2c: b480 push {r7} + 8001b2e: b085 sub sp, #20 + 8001b30: af00 add r7, sp, #0 + 8001b32: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8001d28: 687b ldr r3, [r7, #4] - 8001d2a: f003 0307 and.w r3, r3, #7 - 8001d2e: 60fb str r3, [r7, #12] + 8001b34: 687b ldr r3, [r7, #4] + 8001b36: f003 0307 and.w r3, r3, #7 + 8001b3a: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ - 8001d30: 4b0c ldr r3, [pc, #48] ; (8001d64 <__NVIC_SetPriorityGrouping+0x44>) - 8001d32: 68db ldr r3, [r3, #12] - 8001d34: 60bb str r3, [r7, #8] + 8001b3c: 4b0c ldr r3, [pc, #48] ; (8001b70 <__NVIC_SetPriorityGrouping+0x44>) + 8001b3e: 68db ldr r3, [r3, #12] + 8001b40: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - 8001d36: 68ba ldr r2, [r7, #8] - 8001d38: f64f 03ff movw r3, #63743 ; 0xf8ff - 8001d3c: 4013 ands r3, r2 - 8001d3e: 60bb str r3, [r7, #8] + 8001b42: 68ba ldr r2, [r7, #8] + 8001b44: f64f 03ff movw r3, #63743 ; 0xf8ff + 8001b48: 4013 ands r3, r2 + 8001b4a: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - 8001d40: 68fb ldr r3, [r7, #12] - 8001d42: 021a lsls r2, r3, #8 + 8001b4c: 68fb ldr r3, [r7, #12] + 8001b4e: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - 8001d44: 68bb ldr r3, [r7, #8] - 8001d46: 4313 orrs r3, r2 + 8001b50: 68bb ldr r3, [r7, #8] + 8001b52: 4313 orrs r3, r2 reg_value = (reg_value | - 8001d48: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 - 8001d4c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 - 8001d50: 60bb str r3, [r7, #8] + 8001b54: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 + 8001b58: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 8001b5c: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; - 8001d52: 4a04 ldr r2, [pc, #16] ; (8001d64 <__NVIC_SetPriorityGrouping+0x44>) - 8001d54: 68bb ldr r3, [r7, #8] - 8001d56: 60d3 str r3, [r2, #12] -} - 8001d58: bf00 nop - 8001d5a: 3714 adds r7, #20 - 8001d5c: 46bd mov sp, r7 - 8001d5e: bc80 pop {r7} - 8001d60: 4770 bx lr - 8001d62: bf00 nop - 8001d64: e000ed00 .word 0xe000ed00 - -08001d68 <__NVIC_GetPriorityGrouping>: + 8001b5e: 4a04 ldr r2, [pc, #16] ; (8001b70 <__NVIC_SetPriorityGrouping+0x44>) + 8001b60: 68bb ldr r3, [r7, #8] + 8001b62: 60d3 str r3, [r2, #12] +} + 8001b64: bf00 nop + 8001b66: 3714 adds r7, #20 + 8001b68: 46bd mov sp, r7 + 8001b6a: bc80 pop {r7} + 8001b6c: 4770 bx lr + 8001b6e: bf00 nop + 8001b70: e000ed00 .word 0xe000ed00 + +08001b74 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { - 8001d68: b480 push {r7} - 8001d6a: af00 add r7, sp, #0 + 8001b74: b480 push {r7} + 8001b76: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); - 8001d6c: 4b04 ldr r3, [pc, #16] ; (8001d80 <__NVIC_GetPriorityGrouping+0x18>) - 8001d6e: 68db ldr r3, [r3, #12] - 8001d70: 0a1b lsrs r3, r3, #8 - 8001d72: f003 0307 and.w r3, r3, #7 -} - 8001d76: 4618 mov r0, r3 - 8001d78: 46bd mov sp, r7 - 8001d7a: bc80 pop {r7} - 8001d7c: 4770 bx lr - 8001d7e: bf00 nop - 8001d80: e000ed00 .word 0xe000ed00 - -08001d84 <__NVIC_SetPriority>: + 8001b78: 4b04 ldr r3, [pc, #16] ; (8001b8c <__NVIC_GetPriorityGrouping+0x18>) + 8001b7a: 68db ldr r3, [r3, #12] + 8001b7c: 0a1b lsrs r3, r3, #8 + 8001b7e: f003 0307 and.w r3, r3, #7 +} + 8001b82: 4618 mov r0, r3 + 8001b84: 46bd mov sp, r7 + 8001b86: bc80 pop {r7} + 8001b88: 4770 bx lr + 8001b8a: bf00 nop + 8001b8c: e000ed00 .word 0xe000ed00 + +08001b90 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - 8001d84: b480 push {r7} - 8001d86: b083 sub sp, #12 - 8001d88: af00 add r7, sp, #0 - 8001d8a: 4603 mov r3, r0 - 8001d8c: 6039 str r1, [r7, #0] - 8001d8e: 71fb strb r3, [r7, #7] + 8001b90: b480 push {r7} + 8001b92: b083 sub sp, #12 + 8001b94: af00 add r7, sp, #0 + 8001b96: 4603 mov r3, r0 + 8001b98: 6039 str r1, [r7, #0] + 8001b9a: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) - 8001d90: f997 3007 ldrsb.w r3, [r7, #7] - 8001d94: 2b00 cmp r3, #0 - 8001d96: db0a blt.n 8001dae <__NVIC_SetPriority+0x2a> + 8001b9c: f997 3007 ldrsb.w r3, [r7, #7] + 8001ba0: 2b00 cmp r3, #0 + 8001ba2: db0a blt.n 8001bba <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 8001d98: 683b ldr r3, [r7, #0] - 8001d9a: b2da uxtb r2, r3 - 8001d9c: 490c ldr r1, [pc, #48] ; (8001dd0 <__NVIC_SetPriority+0x4c>) - 8001d9e: f997 3007 ldrsb.w r3, [r7, #7] - 8001da2: 0112 lsls r2, r2, #4 - 8001da4: b2d2 uxtb r2, r2 - 8001da6: 440b add r3, r1 - 8001da8: f883 2300 strb.w r2, [r3, #768] ; 0x300 + 8001ba4: 683b ldr r3, [r7, #0] + 8001ba6: b2da uxtb r2, r3 + 8001ba8: 490c ldr r1, [pc, #48] ; (8001bdc <__NVIC_SetPriority+0x4c>) + 8001baa: f997 3007 ldrsb.w r3, [r7, #7] + 8001bae: 0112 lsls r2, r2, #4 + 8001bb0: b2d2 uxtb r2, r2 + 8001bb2: 440b add r3, r1 + 8001bb4: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } - 8001dac: e00a b.n 8001dc4 <__NVIC_SetPriority+0x40> + 8001bb8: e00a b.n 8001bd0 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 8001dae: 683b ldr r3, [r7, #0] - 8001db0: b2da uxtb r2, r3 - 8001db2: 4908 ldr r1, [pc, #32] ; (8001dd4 <__NVIC_SetPriority+0x50>) - 8001db4: 79fb ldrb r3, [r7, #7] - 8001db6: f003 030f and.w r3, r3, #15 - 8001dba: 3b04 subs r3, #4 - 8001dbc: 0112 lsls r2, r2, #4 - 8001dbe: b2d2 uxtb r2, r2 - 8001dc0: 440b add r3, r1 - 8001dc2: 761a strb r2, [r3, #24] -} - 8001dc4: bf00 nop - 8001dc6: 370c adds r7, #12 - 8001dc8: 46bd mov sp, r7 - 8001dca: bc80 pop {r7} - 8001dcc: 4770 bx lr - 8001dce: bf00 nop - 8001dd0: e000e100 .word 0xe000e100 - 8001dd4: e000ed00 .word 0xe000ed00 - -08001dd8 : + 8001bba: 683b ldr r3, [r7, #0] + 8001bbc: b2da uxtb r2, r3 + 8001bbe: 4908 ldr r1, [pc, #32] ; (8001be0 <__NVIC_SetPriority+0x50>) + 8001bc0: 79fb ldrb r3, [r7, #7] + 8001bc2: f003 030f and.w r3, r3, #15 + 8001bc6: 3b04 subs r3, #4 + 8001bc8: 0112 lsls r2, r2, #4 + 8001bca: b2d2 uxtb r2, r2 + 8001bcc: 440b add r3, r1 + 8001bce: 761a strb r2, [r3, #24] +} + 8001bd0: bf00 nop + 8001bd2: 370c adds r7, #12 + 8001bd4: 46bd mov sp, r7 + 8001bd6: bc80 pop {r7} + 8001bd8: 4770 bx lr + 8001bda: bf00 nop + 8001bdc: e000e100 .word 0xe000e100 + 8001be0: e000ed00 .word 0xe000ed00 + +08001be4 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - 8001dd8: b480 push {r7} - 8001dda: b089 sub sp, #36 ; 0x24 - 8001ddc: af00 add r7, sp, #0 - 8001dde: 60f8 str r0, [r7, #12] - 8001de0: 60b9 str r1, [r7, #8] - 8001de2: 607a str r2, [r7, #4] + 8001be4: b480 push {r7} + 8001be6: b089 sub sp, #36 ; 0x24 + 8001be8: af00 add r7, sp, #0 + 8001bea: 60f8 str r0, [r7, #12] + 8001bec: 60b9 str r1, [r7, #8] + 8001bee: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8001de4: 68fb ldr r3, [r7, #12] - 8001de6: f003 0307 and.w r3, r3, #7 - 8001dea: 61fb str r3, [r7, #28] + 8001bf0: 68fb ldr r3, [r7, #12] + 8001bf2: f003 0307 and.w r3, r3, #7 + 8001bf6: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - 8001dec: 69fb ldr r3, [r7, #28] - 8001dee: f1c3 0307 rsb r3, r3, #7 - 8001df2: 2b04 cmp r3, #4 - 8001df4: bf28 it cs - 8001df6: 2304 movcs r3, #4 - 8001df8: 61bb str r3, [r7, #24] + 8001bf8: 69fb ldr r3, [r7, #28] + 8001bfa: f1c3 0307 rsb r3, r3, #7 + 8001bfe: 2b04 cmp r3, #4 + 8001c00: bf28 it cs + 8001c02: 2304 movcs r3, #4 + 8001c04: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - 8001dfa: 69fb ldr r3, [r7, #28] - 8001dfc: 3304 adds r3, #4 - 8001dfe: 2b06 cmp r3, #6 - 8001e00: d902 bls.n 8001e08 - 8001e02: 69fb ldr r3, [r7, #28] - 8001e04: 3b03 subs r3, #3 - 8001e06: e000 b.n 8001e0a - 8001e08: 2300 movs r3, #0 - 8001e0a: 617b str r3, [r7, #20] + 8001c06: 69fb ldr r3, [r7, #28] + 8001c08: 3304 adds r3, #4 + 8001c0a: 2b06 cmp r3, #6 + 8001c0c: d902 bls.n 8001c14 + 8001c0e: 69fb ldr r3, [r7, #28] + 8001c10: 3b03 subs r3, #3 + 8001c12: e000 b.n 8001c16 + 8001c14: 2300 movs r3, #0 + 8001c16: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8001e0c: f04f 32ff mov.w r2, #4294967295 - 8001e10: 69bb ldr r3, [r7, #24] - 8001e12: fa02 f303 lsl.w r3, r2, r3 - 8001e16: 43da mvns r2, r3 - 8001e18: 68bb ldr r3, [r7, #8] - 8001e1a: 401a ands r2, r3 - 8001e1c: 697b ldr r3, [r7, #20] - 8001e1e: 409a lsls r2, r3 + 8001c18: f04f 32ff mov.w r2, #4294967295 + 8001c1c: 69bb ldr r3, [r7, #24] + 8001c1e: fa02 f303 lsl.w r3, r2, r3 + 8001c22: 43da mvns r2, r3 + 8001c24: 68bb ldr r3, [r7, #8] + 8001c26: 401a ands r2, r3 + 8001c28: 697b ldr r3, [r7, #20] + 8001c2a: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - 8001e20: f04f 31ff mov.w r1, #4294967295 - 8001e24: 697b ldr r3, [r7, #20] - 8001e26: fa01 f303 lsl.w r3, r1, r3 - 8001e2a: 43d9 mvns r1, r3 - 8001e2c: 687b ldr r3, [r7, #4] - 8001e2e: 400b ands r3, r1 + 8001c2c: f04f 31ff mov.w r1, #4294967295 + 8001c30: 697b ldr r3, [r7, #20] + 8001c32: fa01 f303 lsl.w r3, r1, r3 + 8001c36: 43d9 mvns r1, r3 + 8001c38: 687b ldr r3, [r7, #4] + 8001c3a: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8001e30: 4313 orrs r3, r2 + 8001c3c: 4313 orrs r3, r2 ); } - 8001e32: 4618 mov r0, r3 - 8001e34: 3724 adds r7, #36 ; 0x24 - 8001e36: 46bd mov sp, r7 - 8001e38: bc80 pop {r7} - 8001e3a: 4770 bx lr + 8001c3e: 4618 mov r0, r3 + 8001c40: 3724 adds r7, #36 ; 0x24 + 8001c42: 46bd mov sp, r7 + 8001c44: bc80 pop {r7} + 8001c46: 4770 bx lr -08001e3c : +08001c48 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - 8001e3c: b580 push {r7, lr} - 8001e3e: b082 sub sp, #8 - 8001e40: af00 add r7, sp, #0 - 8001e42: 6078 str r0, [r7, #4] + 8001c48: b580 push {r7, lr} + 8001c4a: b082 sub sp, #8 + 8001c4c: af00 add r7, sp, #0 + 8001c4e: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - 8001e44: 687b ldr r3, [r7, #4] - 8001e46: 3b01 subs r3, #1 - 8001e48: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 - 8001e4c: d301 bcc.n 8001e52 + 8001c50: 687b ldr r3, [r7, #4] + 8001c52: 3b01 subs r3, #1 + 8001c54: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 + 8001c58: d301 bcc.n 8001c5e { return (1UL); /* Reload value impossible */ - 8001e4e: 2301 movs r3, #1 - 8001e50: e00f b.n 8001e72 + 8001c5a: 2301 movs r3, #1 + 8001c5c: e00f b.n 8001c7e } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - 8001e52: 4a0a ldr r2, [pc, #40] ; (8001e7c ) - 8001e54: 687b ldr r3, [r7, #4] - 8001e56: 3b01 subs r3, #1 - 8001e58: 6053 str r3, [r2, #4] + 8001c5e: 4a0a ldr r2, [pc, #40] ; (8001c88 ) + 8001c60: 687b ldr r3, [r7, #4] + 8001c62: 3b01 subs r3, #1 + 8001c64: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - 8001e5a: 210f movs r1, #15 - 8001e5c: f04f 30ff mov.w r0, #4294967295 - 8001e60: f7ff ff90 bl 8001d84 <__NVIC_SetPriority> + 8001c66: 210f movs r1, #15 + 8001c68: f04f 30ff mov.w r0, #4294967295 + 8001c6c: f7ff ff90 bl 8001b90 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - 8001e64: 4b05 ldr r3, [pc, #20] ; (8001e7c ) - 8001e66: 2200 movs r2, #0 - 8001e68: 609a str r2, [r3, #8] + 8001c70: 4b05 ldr r3, [pc, #20] ; (8001c88 ) + 8001c72: 2200 movs r2, #0 + 8001c74: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - 8001e6a: 4b04 ldr r3, [pc, #16] ; (8001e7c ) - 8001e6c: 2207 movs r2, #7 - 8001e6e: 601a str r2, [r3, #0] + 8001c76: 4b04 ldr r3, [pc, #16] ; (8001c88 ) + 8001c78: 2207 movs r2, #7 + 8001c7a: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ - 8001e70: 2300 movs r3, #0 + 8001c7c: 2300 movs r3, #0 } - 8001e72: 4618 mov r0, r3 - 8001e74: 3708 adds r7, #8 - 8001e76: 46bd mov sp, r7 - 8001e78: bd80 pop {r7, pc} - 8001e7a: bf00 nop - 8001e7c: e000e010 .word 0xe000e010 + 8001c7e: 4618 mov r0, r3 + 8001c80: 3708 adds r7, #8 + 8001c82: 46bd mov sp, r7 + 8001c84: bd80 pop {r7, pc} + 8001c86: bf00 nop + 8001c88: e000e010 .word 0xe000e010 -08001e80 : +08001c8c : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 8001e80: b580 push {r7, lr} - 8001e82: b082 sub sp, #8 - 8001e84: af00 add r7, sp, #0 - 8001e86: 6078 str r0, [r7, #4] + 8001c8c: b580 push {r7, lr} + 8001c8e: b082 sub sp, #8 + 8001c90: af00 add r7, sp, #0 + 8001c92: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); - 8001e88: 6878 ldr r0, [r7, #4] - 8001e8a: f7ff ff49 bl 8001d20 <__NVIC_SetPriorityGrouping> + 8001c94: 6878 ldr r0, [r7, #4] + 8001c96: f7ff ff49 bl 8001b2c <__NVIC_SetPriorityGrouping> } - 8001e8e: bf00 nop - 8001e90: 3708 adds r7, #8 - 8001e92: 46bd mov sp, r7 - 8001e94: bd80 pop {r7, pc} + 8001c9a: bf00 nop + 8001c9c: 3708 adds r7, #8 + 8001c9e: 46bd mov sp, r7 + 8001ca0: bd80 pop {r7, pc} -08001e96 : +08001ca2 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { - 8001e96: b580 push {r7, lr} - 8001e98: b086 sub sp, #24 - 8001e9a: af00 add r7, sp, #0 - 8001e9c: 4603 mov r3, r0 - 8001e9e: 60b9 str r1, [r7, #8] - 8001ea0: 607a str r2, [r7, #4] - 8001ea2: 73fb strb r3, [r7, #15] + 8001ca2: b580 push {r7, lr} + 8001ca4: b086 sub sp, #24 + 8001ca6: af00 add r7, sp, #0 + 8001ca8: 4603 mov r3, r0 + 8001caa: 60b9 str r1, [r7, #8] + 8001cac: 607a str r2, [r7, #4] + 8001cae: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); - 8001ea4: f7ff ff60 bl 8001d68 <__NVIC_GetPriorityGrouping> - 8001ea8: 6178 str r0, [r7, #20] + 8001cb0: f7ff ff60 bl 8001b74 <__NVIC_GetPriorityGrouping> + 8001cb4: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); - 8001eaa: 687a ldr r2, [r7, #4] - 8001eac: 68b9 ldr r1, [r7, #8] - 8001eae: 6978 ldr r0, [r7, #20] - 8001eb0: f7ff ff92 bl 8001dd8 - 8001eb4: 4602 mov r2, r0 - 8001eb6: f997 300f ldrsb.w r3, [r7, #15] - 8001eba: 4611 mov r1, r2 - 8001ebc: 4618 mov r0, r3 - 8001ebe: f7ff ff61 bl 8001d84 <__NVIC_SetPriority> -} - 8001ec2: bf00 nop - 8001ec4: 3718 adds r7, #24 - 8001ec6: 46bd mov sp, r7 - 8001ec8: bd80 pop {r7, pc} - -08001eca : + 8001cb6: 687a ldr r2, [r7, #4] + 8001cb8: 68b9 ldr r1, [r7, #8] + 8001cba: 6978 ldr r0, [r7, #20] + 8001cbc: f7ff ff92 bl 8001be4 + 8001cc0: 4602 mov r2, r0 + 8001cc2: f997 300f ldrsb.w r3, [r7, #15] + 8001cc6: 4611 mov r1, r2 + 8001cc8: 4618 mov r0, r3 + 8001cca: f7ff ff61 bl 8001b90 <__NVIC_SetPriority> +} + 8001cce: bf00 nop + 8001cd0: 3718 adds r7, #24 + 8001cd2: 46bd mov sp, r7 + 8001cd4: bd80 pop {r7, pc} + +08001cd6 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { - 8001eca: b580 push {r7, lr} - 8001ecc: b082 sub sp, #8 - 8001ece: af00 add r7, sp, #0 - 8001ed0: 6078 str r0, [r7, #4] + 8001cd6: b580 push {r7, lr} + 8001cd8: b082 sub sp, #8 + 8001cda: af00 add r7, sp, #0 + 8001cdc: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); - 8001ed2: 6878 ldr r0, [r7, #4] - 8001ed4: f7ff ffb2 bl 8001e3c - 8001ed8: 4603 mov r3, r0 -} - 8001eda: 4618 mov r0, r3 - 8001edc: 3708 adds r7, #8 - 8001ede: 46bd mov sp, r7 - 8001ee0: bd80 pop {r7, pc} + 8001cde: 6878 ldr r0, [r7, #4] + 8001ce0: f7ff ffb2 bl 8001c48 + 8001ce4: 4603 mov r3, r0 +} + 8001ce6: 4618 mov r0, r3 + 8001ce8: 3708 adds r7, #8 + 8001cea: 46bd mov sp, r7 + 8001cec: bd80 pop {r7, pc} ... -08001ee4 : +08001cf0 : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { - 8001ee4: b580 push {r7, lr} - 8001ee6: b082 sub sp, #8 - 8001ee8: af00 add r7, sp, #0 - 8001eea: 6078 str r0, [r7, #4] + 8001cf0: b580 push {r7, lr} + 8001cf2: b082 sub sp, #8 + 8001cf4: af00 add r7, sp, #0 + 8001cf6: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) - 8001eec: 687b ldr r3, [r7, #4] - 8001eee: 2b00 cmp r3, #0 - 8001ef0: d101 bne.n 8001ef6 + 8001cf8: 687b ldr r3, [r7, #4] + 8001cfa: 2b00 cmp r3, #0 + 8001cfc: d101 bne.n 8001d02 { return HAL_ERROR; - 8001ef2: 2301 movs r3, #1 - 8001ef4: e054 b.n 8001fa0 + 8001cfe: 2301 movs r3, #1 + 8001d00: e054 b.n 8001dac } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) - 8001ef6: 687b ldr r3, [r7, #4] - 8001ef8: 7f5b ldrb r3, [r3, #29] - 8001efa: b2db uxtb r3, r3 - 8001efc: 2b00 cmp r3, #0 - 8001efe: d105 bne.n 8001f0c + 8001d02: 687b ldr r3, [r7, #4] + 8001d04: 7f5b ldrb r3, [r3, #29] + 8001d06: b2db uxtb r3, r3 + 8001d08: 2b00 cmp r3, #0 + 8001d0a: d105 bne.n 8001d18 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; - 8001f00: 687b ldr r3, [r7, #4] - 8001f02: 2200 movs r2, #0 - 8001f04: 771a strb r2, [r3, #28] + 8001d0c: 687b ldr r3, [r7, #4] + 8001d0e: 2200 movs r2, #0 + 8001d10: 771a strb r2, [r3, #28] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); - 8001f06: 6878 ldr r0, [r7, #4] - 8001f08: f7ff fb9e bl 8001648 + 8001d12: 6878 ldr r0, [r7, #4] + 8001d14: f7ff fb9e bl 8001454 } hcrc->State = HAL_CRC_STATE_BUSY; - 8001f0c: 687b ldr r3, [r7, #4] - 8001f0e: 2202 movs r2, #2 - 8001f10: 775a strb r2, [r3, #29] + 8001d18: 687b ldr r3, [r7, #4] + 8001d1a: 2202 movs r2, #2 + 8001d1c: 775a strb r2, [r3, #29] /* check whether or not non-default generating polynomial has been * picked up by user */ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) - 8001f12: 687b ldr r3, [r7, #4] - 8001f14: 791b ldrb r3, [r3, #4] - 8001f16: 2b00 cmp r3, #0 - 8001f18: d10c bne.n 8001f34 + 8001d1e: 687b ldr r3, [r7, #4] + 8001d20: 791b ldrb r3, [r3, #4] + 8001d22: 2b00 cmp r3, #0 + 8001d24: d10c bne.n 8001d40 { /* initialize peripheral with default generating polynomial */ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); - 8001f1a: 687b ldr r3, [r7, #4] - 8001f1c: 681b ldr r3, [r3, #0] - 8001f1e: 4a22 ldr r2, [pc, #136] ; (8001fa8 ) - 8001f20: 615a str r2, [r3, #20] + 8001d26: 687b ldr r3, [r7, #4] + 8001d28: 681b ldr r3, [r3, #0] + 8001d2a: 4a22 ldr r2, [pc, #136] ; (8001db4 ) + 8001d2c: 615a str r2, [r3, #20] MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); - 8001f22: 687b ldr r3, [r7, #4] - 8001f24: 681b ldr r3, [r3, #0] - 8001f26: 689a ldr r2, [r3, #8] - 8001f28: 687b ldr r3, [r7, #4] - 8001f2a: 681b ldr r3, [r3, #0] - 8001f2c: f022 0218 bic.w r2, r2, #24 - 8001f30: 609a str r2, [r3, #8] - 8001f32: e00c b.n 8001f4e + 8001d2e: 687b ldr r3, [r7, #4] + 8001d30: 681b ldr r3, [r3, #0] + 8001d32: 689a ldr r2, [r3, #8] + 8001d34: 687b ldr r3, [r7, #4] + 8001d36: 681b ldr r3, [r3, #0] + 8001d38: f022 0218 bic.w r2, r2, #24 + 8001d3c: 609a str r2, [r3, #8] + 8001d3e: e00c b.n 8001d5a } else { /* initialize CRC peripheral with generating polynomial defined by user */ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) - 8001f34: 687b ldr r3, [r7, #4] - 8001f36: 6899 ldr r1, [r3, #8] - 8001f38: 687b ldr r3, [r7, #4] - 8001f3a: 68db ldr r3, [r3, #12] - 8001f3c: 461a mov r2, r3 - 8001f3e: 6878 ldr r0, [r7, #4] - 8001f40: f000 f834 bl 8001fac - 8001f44: 4603 mov r3, r0 - 8001f46: 2b00 cmp r3, #0 - 8001f48: d001 beq.n 8001f4e + 8001d40: 687b ldr r3, [r7, #4] + 8001d42: 6899 ldr r1, [r3, #8] + 8001d44: 687b ldr r3, [r7, #4] + 8001d46: 68db ldr r3, [r3, #12] + 8001d48: 461a mov r2, r3 + 8001d4a: 6878 ldr r0, [r7, #4] + 8001d4c: f000 f834 bl 8001db8 + 8001d50: 4603 mov r3, r0 + 8001d52: 2b00 cmp r3, #0 + 8001d54: d001 beq.n 8001d5a { return HAL_ERROR; - 8001f4a: 2301 movs r3, #1 - 8001f4c: e028 b.n 8001fa0 + 8001d56: 2301 movs r3, #1 + 8001d58: e028 b.n 8001dac } /* check whether or not non-default CRC initial value has been * picked up by user */ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) - 8001f4e: 687b ldr r3, [r7, #4] - 8001f50: 795b ldrb r3, [r3, #5] - 8001f52: 2b00 cmp r3, #0 - 8001f54: d105 bne.n 8001f62 + 8001d5a: 687b ldr r3, [r7, #4] + 8001d5c: 795b ldrb r3, [r3, #5] + 8001d5e: 2b00 cmp r3, #0 + 8001d60: d105 bne.n 8001d6e { WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); - 8001f56: 687b ldr r3, [r7, #4] - 8001f58: 681b ldr r3, [r3, #0] - 8001f5a: f04f 32ff mov.w r2, #4294967295 - 8001f5e: 611a str r2, [r3, #16] - 8001f60: e004 b.n 8001f6c + 8001d62: 687b ldr r3, [r7, #4] + 8001d64: 681b ldr r3, [r3, #0] + 8001d66: f04f 32ff mov.w r2, #4294967295 + 8001d6a: 611a str r2, [r3, #16] + 8001d6c: e004 b.n 8001d78 } else { WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); - 8001f62: 687b ldr r3, [r7, #4] - 8001f64: 681b ldr r3, [r3, #0] - 8001f66: 687a ldr r2, [r7, #4] - 8001f68: 6912 ldr r2, [r2, #16] - 8001f6a: 611a str r2, [r3, #16] + 8001d6e: 687b ldr r3, [r7, #4] + 8001d70: 681b ldr r3, [r3, #0] + 8001d72: 687a ldr r2, [r7, #4] + 8001d74: 6912 ldr r2, [r2, #16] + 8001d76: 611a str r2, [r3, #16] } /* set input data inversion mode */ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); - 8001f6c: 687b ldr r3, [r7, #4] - 8001f6e: 681b ldr r3, [r3, #0] - 8001f70: 689b ldr r3, [r3, #8] - 8001f72: f023 0160 bic.w r1, r3, #96 ; 0x60 - 8001f76: 687b ldr r3, [r7, #4] - 8001f78: 695a ldr r2, [r3, #20] - 8001f7a: 687b ldr r3, [r7, #4] - 8001f7c: 681b ldr r3, [r3, #0] - 8001f7e: 430a orrs r2, r1 - 8001f80: 609a str r2, [r3, #8] + 8001d78: 687b ldr r3, [r7, #4] + 8001d7a: 681b ldr r3, [r3, #0] + 8001d7c: 689b ldr r3, [r3, #8] + 8001d7e: f023 0160 bic.w r1, r3, #96 ; 0x60 + 8001d82: 687b ldr r3, [r7, #4] + 8001d84: 695a ldr r2, [r3, #20] + 8001d86: 687b ldr r3, [r7, #4] + 8001d88: 681b ldr r3, [r3, #0] + 8001d8a: 430a orrs r2, r1 + 8001d8c: 609a str r2, [r3, #8] /* set output data inversion mode */ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); - 8001f82: 687b ldr r3, [r7, #4] - 8001f84: 681b ldr r3, [r3, #0] - 8001f86: 689b ldr r3, [r3, #8] - 8001f88: f023 0180 bic.w r1, r3, #128 ; 0x80 - 8001f8c: 687b ldr r3, [r7, #4] - 8001f8e: 699a ldr r2, [r3, #24] - 8001f90: 687b ldr r3, [r7, #4] - 8001f92: 681b ldr r3, [r3, #0] - 8001f94: 430a orrs r2, r1 - 8001f96: 609a str r2, [r3, #8] + 8001d8e: 687b ldr r3, [r7, #4] + 8001d90: 681b ldr r3, [r3, #0] + 8001d92: 689b ldr r3, [r3, #8] + 8001d94: f023 0180 bic.w r1, r3, #128 ; 0x80 + 8001d98: 687b ldr r3, [r7, #4] + 8001d9a: 699a ldr r2, [r3, #24] + 8001d9c: 687b ldr r3, [r7, #4] + 8001d9e: 681b ldr r3, [r3, #0] + 8001da0: 430a orrs r2, r1 + 8001da2: 609a str r2, [r3, #8] /* makes sure the input data format (bytes, halfwords or words stream) * is properly specified by user */ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; - 8001f98: 687b ldr r3, [r7, #4] - 8001f9a: 2201 movs r2, #1 - 8001f9c: 775a strb r2, [r3, #29] + 8001da4: 687b ldr r3, [r7, #4] + 8001da6: 2201 movs r2, #1 + 8001da8: 775a strb r2, [r3, #29] /* Return function status */ return HAL_OK; - 8001f9e: 2300 movs r3, #0 + 8001daa: 2300 movs r3, #0 } - 8001fa0: 4618 mov r0, r3 - 8001fa2: 3708 adds r7, #8 - 8001fa4: 46bd mov sp, r7 - 8001fa6: bd80 pop {r7, pc} - 8001fa8: 04c11db7 .word 0x04c11db7 + 8001dac: 4618 mov r0, r3 + 8001dae: 3708 adds r7, #8 + 8001db0: 46bd mov sp, r7 + 8001db2: bd80 pop {r7, pc} + 8001db4: 04c11db7 .word 0x04c11db7 -08001fac : +08001db8 : * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) { - 8001fac: b480 push {r7} - 8001fae: b087 sub sp, #28 - 8001fb0: af00 add r7, sp, #0 - 8001fb2: 60f8 str r0, [r7, #12] - 8001fb4: 60b9 str r1, [r7, #8] - 8001fb6: 607a str r2, [r7, #4] + 8001db8: b480 push {r7} + 8001dba: b087 sub sp, #28 + 8001dbc: af00 add r7, sp, #0 + 8001dbe: 60f8 str r0, [r7, #12] + 8001dc0: 60b9 str r1, [r7, #8] + 8001dc2: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; - 8001fb8: 2300 movs r3, #0 - 8001fba: 75fb strb r3, [r7, #23] + 8001dc4: 2300 movs r3, #0 + 8001dc6: 75fb strb r3, [r7, #23] uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ - 8001fbc: 231f movs r3, #31 - 8001fbe: 613b str r3, [r7, #16] + 8001dc8: 231f movs r3, #31 + 8001dca: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); /* Ensure that the generating polynomial is odd */ if ((Pol & (uint32_t)(0x1U)) == 0U) - 8001fc0: 68bb ldr r3, [r7, #8] - 8001fc2: f003 0301 and.w r3, r3, #1 - 8001fc6: 2b00 cmp r3, #0 - 8001fc8: d102 bne.n 8001fd0 + 8001dcc: 68bb ldr r3, [r7, #8] + 8001dce: f003 0301 and.w r3, r3, #1 + 8001dd2: 2b00 cmp r3, #0 + 8001dd4: d102 bne.n 8001ddc { status = HAL_ERROR; - 8001fca: 2301 movs r3, #1 - 8001fcc: 75fb strb r3, [r7, #23] - 8001fce: e063 b.n 8002098 + 8001dd6: 2301 movs r3, #1 + 8001dd8: 75fb strb r3, [r7, #23] + 8001dda: e063 b.n 8001ea4 * definition. HAL_ERROR is reported if Pol degree is * larger than that indicated by PolyLength. * Look for MSB position: msb will contain the degree of * the second to the largest polynomial member. E.g., for * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) - 8001fd0: bf00 nop - 8001fd2: 693b ldr r3, [r7, #16] - 8001fd4: 1e5a subs r2, r3, #1 - 8001fd6: 613a str r2, [r7, #16] - 8001fd8: 2b00 cmp r3, #0 - 8001fda: d009 beq.n 8001ff0 - 8001fdc: 693b ldr r3, [r7, #16] - 8001fde: f003 031f and.w r3, r3, #31 - 8001fe2: 68ba ldr r2, [r7, #8] - 8001fe4: fa22 f303 lsr.w r3, r2, r3 - 8001fe8: f003 0301 and.w r3, r3, #1 - 8001fec: 2b00 cmp r3, #0 - 8001fee: d0f0 beq.n 8001fd2 + 8001ddc: bf00 nop + 8001dde: 693b ldr r3, [r7, #16] + 8001de0: 1e5a subs r2, r3, #1 + 8001de2: 613a str r2, [r7, #16] + 8001de4: 2b00 cmp r3, #0 + 8001de6: d009 beq.n 8001dfc + 8001de8: 693b ldr r3, [r7, #16] + 8001dea: f003 031f and.w r3, r3, #31 + 8001dee: 68ba ldr r2, [r7, #8] + 8001df0: fa22 f303 lsr.w r3, r2, r3 + 8001df4: f003 0301 and.w r3, r3, #1 + 8001df8: 2b00 cmp r3, #0 + 8001dfa: d0f0 beq.n 8001dde { } switch (PolyLength) - 8001ff0: 687b ldr r3, [r7, #4] - 8001ff2: 2b18 cmp r3, #24 - 8001ff4: d846 bhi.n 8002084 - 8001ff6: a201 add r2, pc, #4 ; (adr r2, 8001ffc ) - 8001ff8: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8001ffc: 0800208b .word 0x0800208b - 8002000: 08002085 .word 0x08002085 - 8002004: 08002085 .word 0x08002085 - 8002008: 08002085 .word 0x08002085 - 800200c: 08002085 .word 0x08002085 - 8002010: 08002085 .word 0x08002085 - 8002014: 08002085 .word 0x08002085 - 8002018: 08002085 .word 0x08002085 - 800201c: 08002079 .word 0x08002079 - 8002020: 08002085 .word 0x08002085 - 8002024: 08002085 .word 0x08002085 - 8002028: 08002085 .word 0x08002085 - 800202c: 08002085 .word 0x08002085 - 8002030: 08002085 .word 0x08002085 - 8002034: 08002085 .word 0x08002085 - 8002038: 08002085 .word 0x08002085 - 800203c: 0800206d .word 0x0800206d - 8002040: 08002085 .word 0x08002085 - 8002044: 08002085 .word 0x08002085 - 8002048: 08002085 .word 0x08002085 - 800204c: 08002085 .word 0x08002085 - 8002050: 08002085 .word 0x08002085 - 8002054: 08002085 .word 0x08002085 - 8002058: 08002085 .word 0x08002085 - 800205c: 08002061 .word 0x08002061 + 8001dfc: 687b ldr r3, [r7, #4] + 8001dfe: 2b18 cmp r3, #24 + 8001e00: d846 bhi.n 8001e90 + 8001e02: a201 add r2, pc, #4 ; (adr r2, 8001e08 ) + 8001e04: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8001e08: 08001e97 .word 0x08001e97 + 8001e0c: 08001e91 .word 0x08001e91 + 8001e10: 08001e91 .word 0x08001e91 + 8001e14: 08001e91 .word 0x08001e91 + 8001e18: 08001e91 .word 0x08001e91 + 8001e1c: 08001e91 .word 0x08001e91 + 8001e20: 08001e91 .word 0x08001e91 + 8001e24: 08001e91 .word 0x08001e91 + 8001e28: 08001e85 .word 0x08001e85 + 8001e2c: 08001e91 .word 0x08001e91 + 8001e30: 08001e91 .word 0x08001e91 + 8001e34: 08001e91 .word 0x08001e91 + 8001e38: 08001e91 .word 0x08001e91 + 8001e3c: 08001e91 .word 0x08001e91 + 8001e40: 08001e91 .word 0x08001e91 + 8001e44: 08001e91 .word 0x08001e91 + 8001e48: 08001e79 .word 0x08001e79 + 8001e4c: 08001e91 .word 0x08001e91 + 8001e50: 08001e91 .word 0x08001e91 + 8001e54: 08001e91 .word 0x08001e91 + 8001e58: 08001e91 .word 0x08001e91 + 8001e5c: 08001e91 .word 0x08001e91 + 8001e60: 08001e91 .word 0x08001e91 + 8001e64: 08001e91 .word 0x08001e91 + 8001e68: 08001e6d .word 0x08001e6d { case CRC_POLYLENGTH_7B: if (msb >= HAL_CRC_LENGTH_7B) - 8002060: 693b ldr r3, [r7, #16] - 8002062: 2b06 cmp r3, #6 - 8002064: d913 bls.n 800208e + 8001e6c: 693b ldr r3, [r7, #16] + 8001e6e: 2b06 cmp r3, #6 + 8001e70: d913 bls.n 8001e9a { status = HAL_ERROR; - 8002066: 2301 movs r3, #1 - 8002068: 75fb strb r3, [r7, #23] + 8001e72: 2301 movs r3, #1 + 8001e74: 75fb strb r3, [r7, #23] } break; - 800206a: e010 b.n 800208e + 8001e76: e010 b.n 8001e9a case CRC_POLYLENGTH_8B: if (msb >= HAL_CRC_LENGTH_8B) - 800206c: 693b ldr r3, [r7, #16] - 800206e: 2b07 cmp r3, #7 - 8002070: d90f bls.n 8002092 + 8001e78: 693b ldr r3, [r7, #16] + 8001e7a: 2b07 cmp r3, #7 + 8001e7c: d90f bls.n 8001e9e { status = HAL_ERROR; - 8002072: 2301 movs r3, #1 - 8002074: 75fb strb r3, [r7, #23] + 8001e7e: 2301 movs r3, #1 + 8001e80: 75fb strb r3, [r7, #23] } break; - 8002076: e00c b.n 8002092 + 8001e82: e00c b.n 8001e9e case CRC_POLYLENGTH_16B: if (msb >= HAL_CRC_LENGTH_16B) - 8002078: 693b ldr r3, [r7, #16] - 800207a: 2b0f cmp r3, #15 - 800207c: d90b bls.n 8002096 + 8001e84: 693b ldr r3, [r7, #16] + 8001e86: 2b0f cmp r3, #15 + 8001e88: d90b bls.n 8001ea2 { status = HAL_ERROR; - 800207e: 2301 movs r3, #1 - 8002080: 75fb strb r3, [r7, #23] + 8001e8a: 2301 movs r3, #1 + 8001e8c: 75fb strb r3, [r7, #23] } break; - 8002082: e008 b.n 8002096 + 8001e8e: e008 b.n 8001ea2 case CRC_POLYLENGTH_32B: /* no polynomial definition vs. polynomial length issue possible */ break; default: status = HAL_ERROR; - 8002084: 2301 movs r3, #1 - 8002086: 75fb strb r3, [r7, #23] + 8001e90: 2301 movs r3, #1 + 8001e92: 75fb strb r3, [r7, #23] break; - 8002088: e006 b.n 8002098 + 8001e94: e006 b.n 8001ea4 break; - 800208a: bf00 nop - 800208c: e004 b.n 8002098 + 8001e96: bf00 nop + 8001e98: e004 b.n 8001ea4 break; - 800208e: bf00 nop - 8002090: e002 b.n 8002098 + 8001e9a: bf00 nop + 8001e9c: e002 b.n 8001ea4 break; - 8002092: bf00 nop - 8002094: e000 b.n 8002098 + 8001e9e: bf00 nop + 8001ea0: e000 b.n 8001ea4 break; - 8002096: bf00 nop + 8001ea2: bf00 nop } } if (status == HAL_OK) - 8002098: 7dfb ldrb r3, [r7, #23] - 800209a: 2b00 cmp r3, #0 - 800209c: d10d bne.n 80020ba + 8001ea4: 7dfb ldrb r3, [r7, #23] + 8001ea6: 2b00 cmp r3, #0 + 8001ea8: d10d bne.n 8001ec6 { /* set generating polynomial */ WRITE_REG(hcrc->Instance->POL, Pol); - 800209e: 68fb ldr r3, [r7, #12] - 80020a0: 681b ldr r3, [r3, #0] - 80020a2: 68ba ldr r2, [r7, #8] - 80020a4: 615a str r2, [r3, #20] + 8001eaa: 68fb ldr r3, [r7, #12] + 8001eac: 681b ldr r3, [r3, #0] + 8001eae: 68ba ldr r2, [r7, #8] + 8001eb0: 615a str r2, [r3, #20] /* set generating polynomial size */ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); - 80020a6: 68fb ldr r3, [r7, #12] - 80020a8: 681b ldr r3, [r3, #0] - 80020aa: 689b ldr r3, [r3, #8] - 80020ac: f023 0118 bic.w r1, r3, #24 - 80020b0: 68fb ldr r3, [r7, #12] - 80020b2: 681b ldr r3, [r3, #0] - 80020b4: 687a ldr r2, [r7, #4] - 80020b6: 430a orrs r2, r1 - 80020b8: 609a str r2, [r3, #8] + 8001eb2: 68fb ldr r3, [r7, #12] + 8001eb4: 681b ldr r3, [r3, #0] + 8001eb6: 689b ldr r3, [r3, #8] + 8001eb8: f023 0118 bic.w r1, r3, #24 + 8001ebc: 68fb ldr r3, [r7, #12] + 8001ebe: 681b ldr r3, [r3, #0] + 8001ec0: 687a ldr r2, [r7, #4] + 8001ec2: 430a orrs r2, r1 + 8001ec4: 609a str r2, [r3, #8] } /* Return function status */ return status; - 80020ba: 7dfb ldrb r3, [r7, #23] + 8001ec6: 7dfb ldrb r3, [r7, #23] } - 80020bc: 4618 mov r0, r3 - 80020be: 371c adds r7, #28 - 80020c0: 46bd mov sp, r7 - 80020c2: bc80 pop {r7} - 80020c4: 4770 bx lr - 80020c6: bf00 nop + 8001ec8: 4618 mov r0, r3 + 8001eca: 371c adds r7, #28 + 8001ecc: 46bd mov sp, r7 + 8001ece: bc80 pop {r7} + 8001ed0: 4770 bx lr + 8001ed2: bf00 nop -080020c8 : +08001ed4 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - 80020c8: b480 push {r7} - 80020ca: b087 sub sp, #28 - 80020cc: af00 add r7, sp, #0 - 80020ce: 6078 str r0, [r7, #4] - 80020d0: 6039 str r1, [r7, #0] + 8001ed4: b480 push {r7} + 8001ed6: b087 sub sp, #28 + 8001ed8: af00 add r7, sp, #0 + 8001eda: 6078 str r0, [r7, #4] + 8001edc: 6039 str r1, [r7, #0] uint32_t position = 0x00u; - 80020d2: 2300 movs r3, #0 - 80020d4: 617b str r3, [r7, #20] + 8001ede: 2300 movs r3, #0 + 8001ee0: 617b str r3, [r7, #20] assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) - 80020d6: e140 b.n 800235a + 8001ee2: e140 b.n 8002166 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); - 80020d8: 683b ldr r3, [r7, #0] - 80020da: 681a ldr r2, [r3, #0] - 80020dc: 2101 movs r1, #1 - 80020de: 697b ldr r3, [r7, #20] - 80020e0: fa01 f303 lsl.w r3, r1, r3 - 80020e4: 4013 ands r3, r2 - 80020e6: 60fb str r3, [r7, #12] + 8001ee4: 683b ldr r3, [r7, #0] + 8001ee6: 681a ldr r2, [r3, #0] + 8001ee8: 2101 movs r1, #1 + 8001eea: 697b ldr r3, [r7, #20] + 8001eec: fa01 f303 lsl.w r3, r1, r3 + 8001ef0: 4013 ands r3, r2 + 8001ef2: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) - 80020e8: 68fb ldr r3, [r7, #12] - 80020ea: 2b00 cmp r3, #0 - 80020ec: f000 8132 beq.w 8002354 + 8001ef4: 68fb ldr r3, [r7, #12] + 8001ef6: 2b00 cmp r3, #0 + 8001ef8: f000 8132 beq.w 8002160 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) - 80020f0: 683b ldr r3, [r7, #0] - 80020f2: 685b ldr r3, [r3, #4] - 80020f4: f003 0303 and.w r3, r3, #3 - 80020f8: 2b01 cmp r3, #1 - 80020fa: d005 beq.n 8002108 - 80020fc: 683b ldr r3, [r7, #0] - 80020fe: 685b ldr r3, [r3, #4] - 8002100: f003 0303 and.w r3, r3, #3 - 8002104: 2b02 cmp r3, #2 - 8002106: d130 bne.n 800216a + 8001efc: 683b ldr r3, [r7, #0] + 8001efe: 685b ldr r3, [r3, #4] + 8001f00: f003 0303 and.w r3, r3, #3 + 8001f04: 2b01 cmp r3, #1 + 8001f06: d005 beq.n 8001f14 + 8001f08: 683b ldr r3, [r7, #0] + 8001f0a: 685b ldr r3, [r3, #4] + 8001f0c: f003 0303 and.w r3, r3, #3 + 8001f10: 2b02 cmp r3, #2 + 8001f12: d130 bne.n 8001f76 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; - 8002108: 687b ldr r3, [r7, #4] - 800210a: 689b ldr r3, [r3, #8] - 800210c: 613b str r3, [r7, #16] + 8001f14: 687b ldr r3, [r7, #4] + 8001f16: 689b ldr r3, [r3, #8] + 8001f18: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); - 800210e: 697b ldr r3, [r7, #20] - 8002110: 005b lsls r3, r3, #1 - 8002112: 2203 movs r2, #3 - 8002114: fa02 f303 lsl.w r3, r2, r3 - 8002118: 43db mvns r3, r3 - 800211a: 693a ldr r2, [r7, #16] - 800211c: 4013 ands r3, r2 - 800211e: 613b str r3, [r7, #16] + 8001f1a: 697b ldr r3, [r7, #20] + 8001f1c: 005b lsls r3, r3, #1 + 8001f1e: 2203 movs r2, #3 + 8001f20: fa02 f303 lsl.w r3, r2, r3 + 8001f24: 43db mvns r3, r3 + 8001f26: 693a ldr r2, [r7, #16] + 8001f28: 4013 ands r3, r2 + 8001f2a: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2U)); - 8002120: 683b ldr r3, [r7, #0] - 8002122: 68da ldr r2, [r3, #12] - 8002124: 697b ldr r3, [r7, #20] - 8002126: 005b lsls r3, r3, #1 - 8002128: fa02 f303 lsl.w r3, r2, r3 - 800212c: 693a ldr r2, [r7, #16] - 800212e: 4313 orrs r3, r2 - 8002130: 613b str r3, [r7, #16] + 8001f2c: 683b ldr r3, [r7, #0] + 8001f2e: 68da ldr r2, [r3, #12] + 8001f30: 697b ldr r3, [r7, #20] + 8001f32: 005b lsls r3, r3, #1 + 8001f34: fa02 f303 lsl.w r3, r2, r3 + 8001f38: 693a ldr r2, [r7, #16] + 8001f3a: 4313 orrs r3, r2 + 8001f3c: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; - 8002132: 687b ldr r3, [r7, #4] - 8002134: 693a ldr r2, [r7, #16] - 8002136: 609a str r2, [r3, #8] + 8001f3e: 687b ldr r3, [r7, #4] + 8001f40: 693a ldr r2, [r7, #16] + 8001f42: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; - 8002138: 687b ldr r3, [r7, #4] - 800213a: 685b ldr r3, [r3, #4] - 800213c: 613b str r3, [r7, #16] + 8001f44: 687b ldr r3, [r7, #4] + 8001f46: 685b ldr r3, [r3, #4] + 8001f48: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT0 << position) ; - 800213e: 2201 movs r2, #1 - 8002140: 697b ldr r3, [r7, #20] - 8002142: fa02 f303 lsl.w r3, r2, r3 - 8002146: 43db mvns r3, r3 - 8002148: 693a ldr r2, [r7, #16] - 800214a: 4013 ands r3, r2 - 800214c: 613b str r3, [r7, #16] + 8001f4a: 2201 movs r2, #1 + 8001f4c: 697b ldr r3, [r7, #20] + 8001f4e: fa02 f303 lsl.w r3, r2, r3 + 8001f52: 43db mvns r3, r3 + 8001f54: 693a ldr r2, [r7, #16] + 8001f56: 4013 ands r3, r2 + 8001f58: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); - 800214e: 683b ldr r3, [r7, #0] - 8002150: 685b ldr r3, [r3, #4] - 8002152: 091b lsrs r3, r3, #4 - 8002154: f003 0201 and.w r2, r3, #1 - 8002158: 697b ldr r3, [r7, #20] - 800215a: fa02 f303 lsl.w r3, r2, r3 - 800215e: 693a ldr r2, [r7, #16] - 8002160: 4313 orrs r3, r2 - 8002162: 613b str r3, [r7, #16] + 8001f5a: 683b ldr r3, [r7, #0] + 8001f5c: 685b ldr r3, [r3, #4] + 8001f5e: 091b lsrs r3, r3, #4 + 8001f60: f003 0201 and.w r2, r3, #1 + 8001f64: 697b ldr r3, [r7, #20] + 8001f66: fa02 f303 lsl.w r3, r2, r3 + 8001f6a: 693a ldr r2, [r7, #16] + 8001f6c: 4313 orrs r3, r2 + 8001f6e: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; - 8002164: 687b ldr r3, [r7, #4] - 8002166: 693a ldr r2, [r7, #16] - 8002168: 605a str r2, [r3, #4] + 8001f70: 687b ldr r3, [r7, #4] + 8001f72: 693a ldr r2, [r7, #16] + 8001f74: 605a str r2, [r3, #4] } /* Activate the Pull-up or Pull down resistor for the current IO */ if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) - 800216a: 683b ldr r3, [r7, #0] - 800216c: 685b ldr r3, [r3, #4] - 800216e: f003 0303 and.w r3, r3, #3 - 8002172: 2b03 cmp r3, #3 - 8002174: d017 beq.n 80021a6 + 8001f76: 683b ldr r3, [r7, #0] + 8001f78: 685b ldr r3, [r3, #4] + 8001f7a: f003 0303 and.w r3, r3, #3 + 8001f7e: 2b03 cmp r3, #3 + 8001f80: d017 beq.n 8001fb2 { temp = GPIOx->PUPDR; - 8002176: 687b ldr r3, [r7, #4] - 8002178: 68db ldr r3, [r3, #12] - 800217a: 613b str r3, [r7, #16] + 8001f82: 687b ldr r3, [r7, #4] + 8001f84: 68db ldr r3, [r3, #12] + 8001f86: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); - 800217c: 697b ldr r3, [r7, #20] - 800217e: 005b lsls r3, r3, #1 - 8002180: 2203 movs r2, #3 - 8002182: fa02 f303 lsl.w r3, r2, r3 - 8002186: 43db mvns r3, r3 - 8002188: 693a ldr r2, [r7, #16] - 800218a: 4013 ands r3, r2 - 800218c: 613b str r3, [r7, #16] + 8001f88: 697b ldr r3, [r7, #20] + 8001f8a: 005b lsls r3, r3, #1 + 8001f8c: 2203 movs r2, #3 + 8001f8e: fa02 f303 lsl.w r3, r2, r3 + 8001f92: 43db mvns r3, r3 + 8001f94: 693a ldr r2, [r7, #16] + 8001f96: 4013 ands r3, r2 + 8001f98: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2U)); - 800218e: 683b ldr r3, [r7, #0] - 8002190: 689a ldr r2, [r3, #8] - 8002192: 697b ldr r3, [r7, #20] - 8002194: 005b lsls r3, r3, #1 - 8002196: fa02 f303 lsl.w r3, r2, r3 - 800219a: 693a ldr r2, [r7, #16] - 800219c: 4313 orrs r3, r2 - 800219e: 613b str r3, [r7, #16] + 8001f9a: 683b ldr r3, [r7, #0] + 8001f9c: 689a ldr r2, [r3, #8] + 8001f9e: 697b ldr r3, [r7, #20] + 8001fa0: 005b lsls r3, r3, #1 + 8001fa2: fa02 f303 lsl.w r3, r2, r3 + 8001fa6: 693a ldr r2, [r7, #16] + 8001fa8: 4313 orrs r3, r2 + 8001faa: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; - 80021a0: 687b ldr r3, [r7, #4] - 80021a2: 693a ldr r2, [r7, #16] - 80021a4: 60da str r2, [r3, #12] + 8001fac: 687b ldr r3, [r7, #4] + 8001fae: 693a ldr r2, [r7, #16] + 8001fb0: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) - 80021a6: 683b ldr r3, [r7, #0] - 80021a8: 685b ldr r3, [r3, #4] - 80021aa: f003 0303 and.w r3, r3, #3 - 80021ae: 2b02 cmp r3, #2 - 80021b0: d123 bne.n 80021fa + 8001fb2: 683b ldr r3, [r7, #0] + 8001fb4: 685b ldr r3, [r3, #4] + 8001fb6: f003 0303 and.w r3, r3, #3 + 8001fba: 2b02 cmp r3, #2 + 8001fbc: d123 bne.n 8002006 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; - 80021b2: 697b ldr r3, [r7, #20] - 80021b4: 08da lsrs r2, r3, #3 - 80021b6: 687b ldr r3, [r7, #4] - 80021b8: 3208 adds r2, #8 - 80021ba: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 80021be: 613b str r3, [r7, #16] + 8001fbe: 697b ldr r3, [r7, #20] + 8001fc0: 08da lsrs r2, r3, #3 + 8001fc2: 687b ldr r3, [r7, #4] + 8001fc4: 3208 adds r2, #8 + 8001fc6: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8001fca: 613b str r3, [r7, #16] temp &= ~(0xFU << ((position & 0x07U) * 4U)); - 80021c0: 697b ldr r3, [r7, #20] - 80021c2: f003 0307 and.w r3, r3, #7 - 80021c6: 009b lsls r3, r3, #2 - 80021c8: 220f movs r2, #15 - 80021ca: fa02 f303 lsl.w r3, r2, r3 - 80021ce: 43db mvns r3, r3 - 80021d0: 693a ldr r2, [r7, #16] - 80021d2: 4013 ands r3, r2 - 80021d4: 613b str r3, [r7, #16] + 8001fcc: 697b ldr r3, [r7, #20] + 8001fce: f003 0307 and.w r3, r3, #7 + 8001fd2: 009b lsls r3, r3, #2 + 8001fd4: 220f movs r2, #15 + 8001fd6: fa02 f303 lsl.w r3, r2, r3 + 8001fda: 43db mvns r3, r3 + 8001fdc: 693a ldr r2, [r7, #16] + 8001fde: 4013 ands r3, r2 + 8001fe0: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); - 80021d6: 683b ldr r3, [r7, #0] - 80021d8: 691a ldr r2, [r3, #16] - 80021da: 697b ldr r3, [r7, #20] - 80021dc: f003 0307 and.w r3, r3, #7 - 80021e0: 009b lsls r3, r3, #2 - 80021e2: fa02 f303 lsl.w r3, r2, r3 - 80021e6: 693a ldr r2, [r7, #16] - 80021e8: 4313 orrs r3, r2 - 80021ea: 613b str r3, [r7, #16] + 8001fe2: 683b ldr r3, [r7, #0] + 8001fe4: 691a ldr r2, [r3, #16] + 8001fe6: 697b ldr r3, [r7, #20] + 8001fe8: f003 0307 and.w r3, r3, #7 + 8001fec: 009b lsls r3, r3, #2 + 8001fee: fa02 f303 lsl.w r3, r2, r3 + 8001ff2: 693a ldr r2, [r7, #16] + 8001ff4: 4313 orrs r3, r2 + 8001ff6: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; - 80021ec: 697b ldr r3, [r7, #20] - 80021ee: 08da lsrs r2, r3, #3 - 80021f0: 687b ldr r3, [r7, #4] - 80021f2: 3208 adds r2, #8 - 80021f4: 6939 ldr r1, [r7, #16] - 80021f6: f843 1022 str.w r1, [r3, r2, lsl #2] + 8001ff8: 697b ldr r3, [r7, #20] + 8001ffa: 08da lsrs r2, r3, #3 + 8001ffc: 687b ldr r3, [r7, #4] + 8001ffe: 3208 adds r2, #8 + 8002000: 6939 ldr r1, [r7, #16] + 8002002: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - 80021fa: 687b ldr r3, [r7, #4] - 80021fc: 681b ldr r3, [r3, #0] - 80021fe: 613b str r3, [r7, #16] + 8002006: 687b ldr r3, [r7, #4] + 8002008: 681b ldr r3, [r3, #0] + 800200a: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); - 8002200: 697b ldr r3, [r7, #20] - 8002202: 005b lsls r3, r3, #1 - 8002204: 2203 movs r2, #3 - 8002206: fa02 f303 lsl.w r3, r2, r3 - 800220a: 43db mvns r3, r3 - 800220c: 693a ldr r2, [r7, #16] - 800220e: 4013 ands r3, r2 - 8002210: 613b str r3, [r7, #16] + 800200c: 697b ldr r3, [r7, #20] + 800200e: 005b lsls r3, r3, #1 + 8002010: 2203 movs r2, #3 + 8002012: fa02 f303 lsl.w r3, r2, r3 + 8002016: 43db mvns r3, r3 + 8002018: 693a ldr r2, [r7, #16] + 800201a: 4013 ands r3, r2 + 800201c: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); - 8002212: 683b ldr r3, [r7, #0] - 8002214: 685b ldr r3, [r3, #4] - 8002216: f003 0203 and.w r2, r3, #3 - 800221a: 697b ldr r3, [r7, #20] - 800221c: 005b lsls r3, r3, #1 - 800221e: fa02 f303 lsl.w r3, r2, r3 - 8002222: 693a ldr r2, [r7, #16] - 8002224: 4313 orrs r3, r2 - 8002226: 613b str r3, [r7, #16] + 800201e: 683b ldr r3, [r7, #0] + 8002020: 685b ldr r3, [r3, #4] + 8002022: f003 0203 and.w r2, r3, #3 + 8002026: 697b ldr r3, [r7, #20] + 8002028: 005b lsls r3, r3, #1 + 800202a: fa02 f303 lsl.w r3, r2, r3 + 800202e: 693a ldr r2, [r7, #16] + 8002030: 4313 orrs r3, r2 + 8002032: 613b str r3, [r7, #16] GPIOx->MODER = temp; - 8002228: 687b ldr r3, [r7, #4] - 800222a: 693a ldr r2, [r7, #16] - 800222c: 601a str r2, [r3, #0] + 8002034: 687b ldr r3, [r7, #4] + 8002036: 693a ldr r2, [r7, #16] + 8002038: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) - 800222e: 683b ldr r3, [r7, #0] - 8002230: 685b ldr r3, [r3, #4] - 8002232: f403 3340 and.w r3, r3, #196608 ; 0x30000 - 8002236: 2b00 cmp r3, #0 - 8002238: f000 808c beq.w 8002354 + 800203a: 683b ldr r3, [r7, #0] + 800203c: 685b ldr r3, [r3, #4] + 800203e: f403 3340 and.w r3, r3, #196608 ; 0x30000 + 8002042: 2b00 cmp r3, #0 + 8002044: f000 808c beq.w 8002160 { temp = SYSCFG->EXTICR[position >> 2u]; - 800223c: 4a4e ldr r2, [pc, #312] ; (8002378 ) - 800223e: 697b ldr r3, [r7, #20] - 8002240: 089b lsrs r3, r3, #2 - 8002242: 3302 adds r3, #2 - 8002244: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8002248: 613b str r3, [r7, #16] + 8002048: 4a4e ldr r2, [pc, #312] ; (8002184 ) + 800204a: 697b ldr r3, [r7, #20] + 800204c: 089b lsrs r3, r3, #2 + 800204e: 3302 adds r3, #2 + 8002050: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8002054: 613b str r3, [r7, #16] temp &= ~(0x07uL << (4U * (position & 0x03U))); - 800224a: 697b ldr r3, [r7, #20] - 800224c: f003 0303 and.w r3, r3, #3 - 8002250: 009b lsls r3, r3, #2 - 8002252: 2207 movs r2, #7 - 8002254: fa02 f303 lsl.w r3, r2, r3 - 8002258: 43db mvns r3, r3 - 800225a: 693a ldr r2, [r7, #16] - 800225c: 4013 ands r3, r2 - 800225e: 613b str r3, [r7, #16] + 8002056: 697b ldr r3, [r7, #20] + 8002058: f003 0303 and.w r3, r3, #3 + 800205c: 009b lsls r3, r3, #2 + 800205e: 2207 movs r2, #7 + 8002060: fa02 f303 lsl.w r3, r2, r3 + 8002064: 43db mvns r3, r3 + 8002066: 693a ldr r2, [r7, #16] + 8002068: 4013 ands r3, r2 + 800206a: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); - 8002260: 687b ldr r3, [r7, #4] - 8002262: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000 - 8002266: d00d beq.n 8002284 - 8002268: 687b ldr r3, [r7, #4] - 800226a: 4a44 ldr r2, [pc, #272] ; (800237c ) - 800226c: 4293 cmp r3, r2 - 800226e: d007 beq.n 8002280 - 8002270: 687b ldr r3, [r7, #4] - 8002272: 4a43 ldr r2, [pc, #268] ; (8002380 ) - 8002274: 4293 cmp r3, r2 - 8002276: d101 bne.n 800227c - 8002278: 2302 movs r3, #2 - 800227a: e004 b.n 8002286 - 800227c: 2307 movs r3, #7 - 800227e: e002 b.n 8002286 - 8002280: 2301 movs r3, #1 - 8002282: e000 b.n 8002286 - 8002284: 2300 movs r3, #0 - 8002286: 697a ldr r2, [r7, #20] - 8002288: f002 0203 and.w r2, r2, #3 - 800228c: 0092 lsls r2, r2, #2 - 800228e: 4093 lsls r3, r2 - 8002290: 693a ldr r2, [r7, #16] - 8002292: 4313 orrs r3, r2 - 8002294: 613b str r3, [r7, #16] + 800206c: 687b ldr r3, [r7, #4] + 800206e: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000 + 8002072: d00d beq.n 8002090 + 8002074: 687b ldr r3, [r7, #4] + 8002076: 4a44 ldr r2, [pc, #272] ; (8002188 ) + 8002078: 4293 cmp r3, r2 + 800207a: d007 beq.n 800208c + 800207c: 687b ldr r3, [r7, #4] + 800207e: 4a43 ldr r2, [pc, #268] ; (800218c ) + 8002080: 4293 cmp r3, r2 + 8002082: d101 bne.n 8002088 + 8002084: 2302 movs r3, #2 + 8002086: e004 b.n 8002092 + 8002088: 2307 movs r3, #7 + 800208a: e002 b.n 8002092 + 800208c: 2301 movs r3, #1 + 800208e: e000 b.n 8002092 + 8002090: 2300 movs r3, #0 + 8002092: 697a ldr r2, [r7, #20] + 8002094: f002 0203 and.w r2, r2, #3 + 8002098: 0092 lsls r2, r2, #2 + 800209a: 4093 lsls r3, r2 + 800209c: 693a ldr r2, [r7, #16] + 800209e: 4313 orrs r3, r2 + 80020a0: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2u] = temp; - 8002296: 4938 ldr r1, [pc, #224] ; (8002378 ) - 8002298: 697b ldr r3, [r7, #20] - 800229a: 089b lsrs r3, r3, #2 - 800229c: 3302 adds r3, #2 - 800229e: 693a ldr r2, [r7, #16] - 80022a0: f841 2023 str.w r2, [r1, r3, lsl #2] + 80020a2: 4938 ldr r1, [pc, #224] ; (8002184 ) + 80020a4: 697b ldr r3, [r7, #20] + 80020a6: 089b lsrs r3, r3, #2 + 80020a8: 3302 adds r3, #2 + 80020aa: 693a ldr r2, [r7, #16] + 80020ac: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; - 80022a4: 4b37 ldr r3, [pc, #220] ; (8002384 ) - 80022a6: 681b ldr r3, [r3, #0] - 80022a8: 613b str r3, [r7, #16] + 80020b0: 4b37 ldr r3, [pc, #220] ; (8002190 ) + 80020b2: 681b ldr r3, [r3, #0] + 80020b4: 613b str r3, [r7, #16] temp &= ~(iocurrent); - 80022aa: 68fb ldr r3, [r7, #12] - 80022ac: 43db mvns r3, r3 - 80022ae: 693a ldr r2, [r7, #16] - 80022b0: 4013 ands r3, r2 - 80022b2: 613b str r3, [r7, #16] + 80020b6: 68fb ldr r3, [r7, #12] + 80020b8: 43db mvns r3, r3 + 80020ba: 693a ldr r2, [r7, #16] + 80020bc: 4013 ands r3, r2 + 80020be: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) - 80022b4: 683b ldr r3, [r7, #0] - 80022b6: 685b ldr r3, [r3, #4] - 80022b8: f403 1380 and.w r3, r3, #1048576 ; 0x100000 - 80022bc: 2b00 cmp r3, #0 - 80022be: d003 beq.n 80022c8 + 80020c0: 683b ldr r3, [r7, #0] + 80020c2: 685b ldr r3, [r3, #4] + 80020c4: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 80020c8: 2b00 cmp r3, #0 + 80020ca: d003 beq.n 80020d4 { temp |= iocurrent; - 80022c0: 693a ldr r2, [r7, #16] - 80022c2: 68fb ldr r3, [r7, #12] - 80022c4: 4313 orrs r3, r2 - 80022c6: 613b str r3, [r7, #16] + 80020cc: 693a ldr r2, [r7, #16] + 80020ce: 68fb ldr r3, [r7, #12] + 80020d0: 4313 orrs r3, r2 + 80020d2: 613b str r3, [r7, #16] } EXTI->RTSR1 = temp; - 80022c8: 4a2e ldr r2, [pc, #184] ; (8002384 ) - 80022ca: 693b ldr r3, [r7, #16] - 80022cc: 6013 str r3, [r2, #0] + 80020d4: 4a2e ldr r2, [pc, #184] ; (8002190 ) + 80020d6: 693b ldr r3, [r7, #16] + 80020d8: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; - 80022ce: 4b2d ldr r3, [pc, #180] ; (8002384 ) - 80022d0: 685b ldr r3, [r3, #4] - 80022d2: 613b str r3, [r7, #16] + 80020da: 4b2d ldr r3, [pc, #180] ; (8002190 ) + 80020dc: 685b ldr r3, [r3, #4] + 80020de: 613b str r3, [r7, #16] temp &= ~(iocurrent); - 80022d4: 68fb ldr r3, [r7, #12] - 80022d6: 43db mvns r3, r3 - 80022d8: 693a ldr r2, [r7, #16] - 80022da: 4013 ands r3, r2 - 80022dc: 613b str r3, [r7, #16] + 80020e0: 68fb ldr r3, [r7, #12] + 80020e2: 43db mvns r3, r3 + 80020e4: 693a ldr r2, [r7, #16] + 80020e6: 4013 ands r3, r2 + 80020e8: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) - 80022de: 683b ldr r3, [r7, #0] - 80022e0: 685b ldr r3, [r3, #4] - 80022e2: f403 1300 and.w r3, r3, #2097152 ; 0x200000 - 80022e6: 2b00 cmp r3, #0 - 80022e8: d003 beq.n 80022f2 + 80020ea: 683b ldr r3, [r7, #0] + 80020ec: 685b ldr r3, [r3, #4] + 80020ee: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 80020f2: 2b00 cmp r3, #0 + 80020f4: d003 beq.n 80020fe { temp |= iocurrent; - 80022ea: 693a ldr r2, [r7, #16] - 80022ec: 68fb ldr r3, [r7, #12] - 80022ee: 4313 orrs r3, r2 - 80022f0: 613b str r3, [r7, #16] + 80020f6: 693a ldr r2, [r7, #16] + 80020f8: 68fb ldr r3, [r7, #12] + 80020fa: 4313 orrs r3, r2 + 80020fc: 613b str r3, [r7, #16] } EXTI->FTSR1 = temp; - 80022f2: 4a24 ldr r2, [pc, #144] ; (8002384 ) - 80022f4: 693b ldr r3, [r7, #16] - 80022f6: 6053 str r3, [r2, #4] + 80020fe: 4a24 ldr r2, [pc, #144] ; (8002190 ) + 8002100: 693b ldr r3, [r7, #16] + 8002102: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ #ifdef CORE_CM0PLUS temp = EXTI->C2IMR1; #else temp = EXTI->IMR1; - 80022f8: 4b22 ldr r3, [pc, #136] ; (8002384 ) - 80022fa: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 - 80022fe: 613b str r3, [r7, #16] + 8002104: 4b22 ldr r3, [pc, #136] ; (8002190 ) + 8002106: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 800210a: 613b str r3, [r7, #16] #endif /* CORE_CM0PLUS */ temp &= ~(iocurrent); - 8002300: 68fb ldr r3, [r7, #12] - 8002302: 43db mvns r3, r3 - 8002304: 693a ldr r2, [r7, #16] - 8002306: 4013 ands r3, r2 - 8002308: 613b str r3, [r7, #16] + 800210c: 68fb ldr r3, [r7, #12] + 800210e: 43db mvns r3, r3 + 8002110: 693a ldr r2, [r7, #16] + 8002112: 4013 ands r3, r2 + 8002114: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) - 800230a: 683b ldr r3, [r7, #0] - 800230c: 685b ldr r3, [r3, #4] - 800230e: f403 3380 and.w r3, r3, #65536 ; 0x10000 - 8002312: 2b00 cmp r3, #0 - 8002314: d003 beq.n 800231e + 8002116: 683b ldr r3, [r7, #0] + 8002118: 685b ldr r3, [r3, #4] + 800211a: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 800211e: 2b00 cmp r3, #0 + 8002120: d003 beq.n 800212a { temp |= iocurrent; - 8002316: 693a ldr r2, [r7, #16] - 8002318: 68fb ldr r3, [r7, #12] - 800231a: 4313 orrs r3, r2 - 800231c: 613b str r3, [r7, #16] + 8002122: 693a ldr r2, [r7, #16] + 8002124: 68fb ldr r3, [r7, #12] + 8002126: 4313 orrs r3, r2 + 8002128: 613b str r3, [r7, #16] } #ifdef CORE_CM0PLUS EXTI->C2IMR1 = temp; #else EXTI->IMR1 = temp; - 800231e: 4a19 ldr r2, [pc, #100] ; (8002384 ) - 8002320: 693b ldr r3, [r7, #16] - 8002322: f8c2 3080 str.w r3, [r2, #128] ; 0x80 + 800212a: 4a19 ldr r2, [pc, #100] ; (8002190 ) + 800212c: 693b ldr r3, [r7, #16] + 800212e: f8c2 3080 str.w r3, [r2, #128] ; 0x80 #endif /* CORE_CM0PLUS */ #ifdef CORE_CM0PLUS temp = EXTI->C2EMR1; #else temp = EXTI->EMR1; - 8002326: 4b17 ldr r3, [pc, #92] ; (8002384 ) - 8002328: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 800232c: 613b str r3, [r7, #16] + 8002132: 4b17 ldr r3, [pc, #92] ; (8002190 ) + 8002134: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8002138: 613b str r3, [r7, #16] #endif /* CORE_CM0PLUS */ temp &= ~(iocurrent); - 800232e: 68fb ldr r3, [r7, #12] - 8002330: 43db mvns r3, r3 - 8002332: 693a ldr r2, [r7, #16] - 8002334: 4013 ands r3, r2 - 8002336: 613b str r3, [r7, #16] + 800213a: 68fb ldr r3, [r7, #12] + 800213c: 43db mvns r3, r3 + 800213e: 693a ldr r2, [r7, #16] + 8002140: 4013 ands r3, r2 + 8002142: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) - 8002338: 683b ldr r3, [r7, #0] - 800233a: 685b ldr r3, [r3, #4] - 800233c: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8002340: 2b00 cmp r3, #0 - 8002342: d003 beq.n 800234c + 8002144: 683b ldr r3, [r7, #0] + 8002146: 685b ldr r3, [r3, #4] + 8002148: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800214c: 2b00 cmp r3, #0 + 800214e: d003 beq.n 8002158 { temp |= iocurrent; - 8002344: 693a ldr r2, [r7, #16] - 8002346: 68fb ldr r3, [r7, #12] - 8002348: 4313 orrs r3, r2 - 800234a: 613b str r3, [r7, #16] + 8002150: 693a ldr r2, [r7, #16] + 8002152: 68fb ldr r3, [r7, #12] + 8002154: 4313 orrs r3, r2 + 8002156: 613b str r3, [r7, #16] } #ifdef CORE_CM0PLUS EXTI->C2EMR1 = temp; #else EXTI->EMR1 = temp; - 800234c: 4a0d ldr r2, [pc, #52] ; (8002384 ) - 800234e: 693b ldr r3, [r7, #16] - 8002350: f8c2 3084 str.w r3, [r2, #132] ; 0x84 + 8002158: 4a0d ldr r2, [pc, #52] ; (8002190 ) + 800215a: 693b ldr r3, [r7, #16] + 800215c: f8c2 3084 str.w r3, [r2, #132] ; 0x84 #endif /* CORE_CM0PLUS */ } } position++; - 8002354: 697b ldr r3, [r7, #20] - 8002356: 3301 adds r3, #1 - 8002358: 617b str r3, [r7, #20] + 8002160: 697b ldr r3, [r7, #20] + 8002162: 3301 adds r3, #1 + 8002164: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) - 800235a: 683b ldr r3, [r7, #0] - 800235c: 681a ldr r2, [r3, #0] - 800235e: 697b ldr r3, [r7, #20] - 8002360: fa22 f303 lsr.w r3, r2, r3 - 8002364: 2b00 cmp r3, #0 - 8002366: f47f aeb7 bne.w 80020d8 + 8002166: 683b ldr r3, [r7, #0] + 8002168: 681a ldr r2, [r3, #0] + 800216a: 697b ldr r3, [r7, #20] + 800216c: fa22 f303 lsr.w r3, r2, r3 + 8002170: 2b00 cmp r3, #0 + 8002172: f47f aeb7 bne.w 8001ee4 } } - 800236a: bf00 nop - 800236c: bf00 nop - 800236e: 371c adds r7, #28 - 8002370: 46bd mov sp, r7 - 8002372: bc80 pop {r7} - 8002374: 4770 bx lr - 8002376: bf00 nop - 8002378: 40010000 .word 0x40010000 - 800237c: 48000400 .word 0x48000400 - 8002380: 48000800 .word 0x48000800 - 8002384: 58000800 .word 0x58000800 - -08002388 : + 8002176: bf00 nop + 8002178: bf00 nop + 800217a: 371c adds r7, #28 + 800217c: 46bd mov sp, r7 + 800217e: bc80 pop {r7} + 8002180: 4770 bx lr + 8002182: bf00 nop + 8002184: 40010000 .word 0x40010000 + 8002188: 48000400 .word 0x48000400 + 800218c: 48000800 .word 0x48000800 + 8002190: 58000800 .word 0x58000800 + +08002194 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { - 8002388: b480 push {r7} - 800238a: b083 sub sp, #12 - 800238c: af00 add r7, sp, #0 - 800238e: 6078 str r0, [r7, #4] - 8002390: 460b mov r3, r1 - 8002392: 807b strh r3, [r7, #2] - 8002394: 4613 mov r3, r2 - 8002396: 707b strb r3, [r7, #1] + 8002194: b480 push {r7} + 8002196: b083 sub sp, #12 + 8002198: af00 add r7, sp, #0 + 800219a: 6078 str r0, [r7, #4] + 800219c: 460b mov r3, r1 + 800219e: 807b strh r3, [r7, #2] + 80021a0: 4613 mov r3, r2 + 80021a2: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) - 8002398: 787b ldrb r3, [r7, #1] - 800239a: 2b00 cmp r3, #0 - 800239c: d003 beq.n 80023a6 + 80021a4: 787b ldrb r3, [r7, #1] + 80021a6: 2b00 cmp r3, #0 + 80021a8: d003 beq.n 80021b2 { GPIOx->BSRR = (uint32_t)GPIO_Pin; - 800239e: 887a ldrh r2, [r7, #2] - 80023a0: 687b ldr r3, [r7, #4] - 80023a2: 619a str r2, [r3, #24] + 80021aa: 887a ldrh r2, [r7, #2] + 80021ac: 687b ldr r3, [r7, #4] + 80021ae: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } - 80023a4: e002 b.n 80023ac + 80021b0: e002 b.n 80021b8 GPIOx->BRR = (uint32_t)GPIO_Pin; - 80023a6: 887a ldrh r2, [r7, #2] - 80023a8: 687b ldr r3, [r7, #4] - 80023aa: 629a str r2, [r3, #40] ; 0x28 -} - 80023ac: bf00 nop - 80023ae: 370c adds r7, #12 - 80023b0: 46bd mov sp, r7 - 80023b2: bc80 pop {r7} - 80023b4: 4770 bx lr + 80021b2: 887a ldrh r2, [r7, #2] + 80021b4: 687b ldr r3, [r7, #4] + 80021b6: 629a str r2, [r3, #40] ; 0x28 +} + 80021b8: bf00 nop + 80021ba: 370c adds r7, #12 + 80021bc: 46bd mov sp, r7 + 80021be: bc80 pop {r7} + 80021c0: 4770 bx lr ... -080023b8 : +080021c4 : * @note LSEON bit that switches on and off the LSE crystal belongs as well to the * backup domain. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { - 80023b8: b480 push {r7} - 80023ba: af00 add r7, sp, #0 + 80021c4: b480 push {r7} + 80021c6: af00 add r7, sp, #0 SET_BIT(PWR->CR1, PWR_CR1_DBP); - 80023bc: 4b04 ldr r3, [pc, #16] ; (80023d0 ) - 80023be: 681b ldr r3, [r3, #0] - 80023c0: 4a03 ldr r2, [pc, #12] ; (80023d0 ) - 80023c2: f443 7380 orr.w r3, r3, #256 ; 0x100 - 80023c6: 6013 str r3, [r2, #0] -} - 80023c8: bf00 nop - 80023ca: 46bd mov sp, r7 - 80023cc: bc80 pop {r7} - 80023ce: 4770 bx lr - 80023d0: 58000400 .word 0x58000400 - -080023d4 : + 80021c8: 4b04 ldr r3, [pc, #16] ; (80021dc ) + 80021ca: 681b ldr r3, [r3, #0] + 80021cc: 4a03 ldr r2, [pc, #12] ; (80021dc ) + 80021ce: f443 7380 orr.w r3, r3, #256 ; 0x100 + 80021d2: 6013 str r3, [r2, #0] +} + 80021d4: bf00 nop + 80021d6: 46bd mov sp, r7 + 80021d8: bc80 pop {r7} + 80021da: 4770 bx lr + 80021dc: 58000400 .word 0x58000400 + +080021e0 : /** * @brief Return Voltage Scaling Range. * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWPWR_REGULATOR_VOLTAGE_SCALE2) */ uint32_t HAL_PWREx_GetVoltageRange(void) { - 80023d4: b480 push {r7} - 80023d6: af00 add r7, sp, #0 + 80021e0: b480 push {r7} + 80021e2: af00 add r7, sp, #0 return (PWR->CR1 & PWR_CR1_VOS); - 80023d8: 4b03 ldr r3, [pc, #12] ; (80023e8 ) - 80023da: 681b ldr r3, [r3, #0] - 80023dc: f403 63c0 and.w r3, r3, #1536 ; 0x600 + 80021e4: 4b03 ldr r3, [pc, #12] ; (80021f4 ) + 80021e6: 681b ldr r3, [r3, #0] + 80021e8: f403 63c0 and.w r3, r3, #1536 ; 0x600 } - 80023e0: 4618 mov r0, r3 - 80023e2: 46bd mov sp, r7 - 80023e4: bc80 pop {r7} - 80023e6: 4770 bx lr - 80023e8: 58000400 .word 0x58000400 + 80021ec: 4618 mov r0, r3 + 80021ee: 46bd mov sp, r7 + 80021f0: bc80 pop {r7} + 80021f2: 4770 bx lr + 80021f4: 58000400 .word 0x58000400 -080023ec : +080021f8 : * @brief Check if the backup domain is enabled * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) { - 80023ec: b480 push {r7} - 80023ee: af00 add r7, sp, #0 + 80021f8: b480 push {r7} + 80021fa: af00 add r7, sp, #0 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); - 80023f0: 4b06 ldr r3, [pc, #24] ; (800240c ) - 80023f2: 681b ldr r3, [r3, #0] - 80023f4: f403 7380 and.w r3, r3, #256 ; 0x100 - 80023f8: f5b3 7f80 cmp.w r3, #256 ; 0x100 - 80023fc: d101 bne.n 8002402 - 80023fe: 2301 movs r3, #1 - 8002400: e000 b.n 8002404 - 8002402: 2300 movs r3, #0 -} - 8002404: 4618 mov r0, r3 - 8002406: 46bd mov sp, r7 - 8002408: bc80 pop {r7} - 800240a: 4770 bx lr - 800240c: 58000400 .word 0x58000400 - -08002410 : -{ - 8002410: b480 push {r7} - 8002412: af00 add r7, sp, #0 + 80021fc: 4b06 ldr r3, [pc, #24] ; (8002218 ) + 80021fe: 681b ldr r3, [r3, #0] + 8002200: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002204: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8002208: d101 bne.n 800220e + 800220a: 2301 movs r3, #1 + 800220c: e000 b.n 8002210 + 800220e: 2300 movs r3, #0 +} + 8002210: 4618 mov r0, r3 + 8002212: 46bd mov sp, r7 + 8002214: bc80 pop {r7} + 8002216: 4770 bx lr + 8002218: 58000400 .word 0x58000400 + +0800221c : +{ + 800221c: b480 push {r7} + 800221e: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_HSEBYPPWR); - 8002414: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002418: 681b ldr r3, [r3, #0] - 800241a: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 800241e: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 - 8002422: 6013 str r3, [r2, #0] + 8002220: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002224: 681b ldr r3, [r3, #0] + 8002226: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 800222a: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 + 800222e: 6013 str r3, [r2, #0] } - 8002424: bf00 nop - 8002426: 46bd mov sp, r7 - 8002428: bc80 pop {r7} - 800242a: 4770 bx lr + 8002230: bf00 nop + 8002232: 46bd mov sp, r7 + 8002234: bc80 pop {r7} + 8002236: 4770 bx lr -0800242c : +08002238 : { - 800242c: b480 push {r7} - 800242e: af00 add r7, sp, #0 + 8002238: b480 push {r7} + 800223a: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYPPWR); - 8002430: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002434: 681b ldr r3, [r3, #0] - 8002436: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 800243a: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 - 800243e: 6013 str r3, [r2, #0] -} - 8002440: bf00 nop - 8002442: 46bd mov sp, r7 - 8002444: bc80 pop {r7} - 8002446: 4770 bx lr - -08002448 : + 800223c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002240: 681b ldr r3, [r3, #0] + 8002242: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8002246: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 + 800224a: 6013 str r3, [r2, #0] +} + 800224c: bf00 nop + 800224e: 46bd mov sp, r7 + 8002250: bc80 pop {r7} + 8002252: 4770 bx lr + +08002254 : * @brief Get HSE sysclk and pll prescaler division by 2 * @rmtoll CR HSEPRE LL_RCC_HSE_IsEnabledDiv2 * @retval None */ __STATIC_INLINE uint32_t LL_RCC_HSE_IsEnabledDiv2(void) { - 8002448: b480 push {r7} - 800244a: af00 add r7, sp, #0 + 8002254: b480 push {r7} + 8002256: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL); - 800244c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002450: 681b ldr r3, [r3, #0] - 8002452: f403 1380 and.w r3, r3, #1048576 ; 0x100000 - 8002456: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 - 800245a: d101 bne.n 8002460 - 800245c: 2301 movs r3, #1 - 800245e: e000 b.n 8002462 - 8002460: 2300 movs r3, #0 -} - 8002462: 4618 mov r0, r3 - 8002464: 46bd mov sp, r7 - 8002466: bc80 pop {r7} - 8002468: 4770 bx lr - -0800246a : + 8002258: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800225c: 681b ldr r3, [r3, #0] + 800225e: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8002262: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 8002266: d101 bne.n 800226c + 8002268: 2301 movs r3, #1 + 800226a: e000 b.n 800226e + 800226c: 2300 movs r3, #0 +} + 800226e: 4618 mov r0, r3 + 8002270: 46bd mov sp, r7 + 8002272: bc80 pop {r7} + 8002274: 4770 bx lr + +08002276 : * @brief Enable HSE crystal oscillator (HSE ON) * @rmtoll CR HSEON LL_RCC_HSE_Enable * @retval None */ __STATIC_INLINE void LL_RCC_HSE_Enable(void) { - 800246a: b480 push {r7} - 800246c: af00 add r7, sp, #0 + 8002276: b480 push {r7} + 8002278: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_HSEON); - 800246e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002472: 681b ldr r3, [r3, #0] - 8002474: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 8002478: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 800247c: 6013 str r3, [r2, #0] -} - 800247e: bf00 nop - 8002480: 46bd mov sp, r7 - 8002482: bc80 pop {r7} - 8002484: 4770 bx lr - -08002486 : + 800227a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800227e: 681b ldr r3, [r3, #0] + 8002280: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8002284: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8002288: 6013 str r3, [r2, #0] +} + 800228a: bf00 nop + 800228c: 46bd mov sp, r7 + 800228e: bc80 pop {r7} + 8002290: 4770 bx lr + +08002292 : * @brief Disable HSE crystal oscillator (HSE ON) * @rmtoll CR HSEON LL_RCC_HSE_Disable * @retval None */ __STATIC_INLINE void LL_RCC_HSE_Disable(void) { - 8002486: b480 push {r7} - 8002488: af00 add r7, sp, #0 + 8002292: b480 push {r7} + 8002294: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); - 800248a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800248e: 681b ldr r3, [r3, #0] - 8002490: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 8002494: f423 3380 bic.w r3, r3, #65536 ; 0x10000 - 8002498: 6013 str r3, [r2, #0] -} - 800249a: bf00 nop - 800249c: 46bd mov sp, r7 - 800249e: bc80 pop {r7} - 80024a0: 4770 bx lr - -080024a2 : + 8002296: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800229a: 681b ldr r3, [r3, #0] + 800229c: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 80022a0: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 80022a4: 6013 str r3, [r2, #0] +} + 80022a6: bf00 nop + 80022a8: 46bd mov sp, r7 + 80022aa: bc80 pop {r7} + 80022ac: 4770 bx lr + +080022ae : * @brief Check if HSE oscillator Ready * @rmtoll CR HSERDY LL_RCC_HSE_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) { - 80024a2: b480 push {r7} - 80024a4: af00 add r7, sp, #0 + 80022ae: b480 push {r7} + 80022b0: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); - 80024a6: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80024aa: 681b ldr r3, [r3, #0] - 80024ac: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 80024b0: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 - 80024b4: d101 bne.n 80024ba - 80024b6: 2301 movs r3, #1 - 80024b8: e000 b.n 80024bc - 80024ba: 2300 movs r3, #0 -} - 80024bc: 4618 mov r0, r3 - 80024be: 46bd mov sp, r7 - 80024c0: bc80 pop {r7} - 80024c2: 4770 bx lr - -080024c4 : + 80022b2: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80022b6: 681b ldr r3, [r3, #0] + 80022b8: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80022bc: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 + 80022c0: d101 bne.n 80022c6 + 80022c2: 2301 movs r3, #1 + 80022c4: e000 b.n 80022c8 + 80022c6: 2300 movs r3, #0 +} + 80022c8: 4618 mov r0, r3 + 80022ca: 46bd mov sp, r7 + 80022cc: bc80 pop {r7} + 80022ce: 4770 bx lr + +080022d0 : * @brief Enable HSI oscillator * @rmtoll CR HSION LL_RCC_HSI_Enable * @retval None */ __STATIC_INLINE void LL_RCC_HSI_Enable(void) { - 80024c4: b480 push {r7} - 80024c6: af00 add r7, sp, #0 + 80022d0: b480 push {r7} + 80022d2: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_HSION); - 80024c8: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80024cc: 681b ldr r3, [r3, #0] - 80024ce: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 80024d2: f443 7380 orr.w r3, r3, #256 ; 0x100 - 80024d6: 6013 str r3, [r2, #0] -} - 80024d8: bf00 nop - 80024da: 46bd mov sp, r7 - 80024dc: bc80 pop {r7} - 80024de: 4770 bx lr - -080024e0 : + 80022d4: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80022d8: 681b ldr r3, [r3, #0] + 80022da: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 80022de: f443 7380 orr.w r3, r3, #256 ; 0x100 + 80022e2: 6013 str r3, [r2, #0] +} + 80022e4: bf00 nop + 80022e6: 46bd mov sp, r7 + 80022e8: bc80 pop {r7} + 80022ea: 4770 bx lr + +080022ec : * @brief Disable HSI oscillator * @rmtoll CR HSION LL_RCC_HSI_Disable * @retval None */ __STATIC_INLINE void LL_RCC_HSI_Disable(void) { - 80024e0: b480 push {r7} - 80024e2: af00 add r7, sp, #0 + 80022ec: b480 push {r7} + 80022ee: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_HSION); - 80024e4: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80024e8: 681b ldr r3, [r3, #0] - 80024ea: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 80024ee: f423 7380 bic.w r3, r3, #256 ; 0x100 - 80024f2: 6013 str r3, [r2, #0] -} - 80024f4: bf00 nop - 80024f6: 46bd mov sp, r7 - 80024f8: bc80 pop {r7} - 80024fa: 4770 bx lr - -080024fc : + 80022f0: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80022f4: 681b ldr r3, [r3, #0] + 80022f6: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 80022fa: f423 7380 bic.w r3, r3, #256 ; 0x100 + 80022fe: 6013 str r3, [r2, #0] +} + 8002300: bf00 nop + 8002302: 46bd mov sp, r7 + 8002304: bc80 pop {r7} + 8002306: 4770 bx lr + +08002308 : * @brief Check if HSI clock is ready * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) { - 80024fc: b480 push {r7} - 80024fe: af00 add r7, sp, #0 + 8002308: b480 push {r7} + 800230a: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); - 8002500: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002504: 681b ldr r3, [r3, #0] - 8002506: f403 6380 and.w r3, r3, #1024 ; 0x400 - 800250a: f5b3 6f80 cmp.w r3, #1024 ; 0x400 - 800250e: d101 bne.n 8002514 - 8002510: 2301 movs r3, #1 - 8002512: e000 b.n 8002516 - 8002514: 2300 movs r3, #0 -} - 8002516: 4618 mov r0, r3 - 8002518: 46bd mov sp, r7 - 800251a: bc80 pop {r7} - 800251c: 4770 bx lr - -0800251e : + 800230c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002310: 681b ldr r3, [r3, #0] + 8002312: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8002316: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 800231a: d101 bne.n 8002320 + 800231c: 2301 movs r3, #1 + 800231e: e000 b.n 8002322 + 8002320: 2300 movs r3, #0 +} + 8002322: 4618 mov r0, r3 + 8002324: 46bd mov sp, r7 + 8002326: bc80 pop {r7} + 8002328: 4770 bx lr + +0800232a : * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming * @param Value Between Min_Data = 0 and Max_Data = 127 * @retval None */ __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) { - 800251e: b480 push {r7} - 8002520: b083 sub sp, #12 - 8002522: af00 add r7, sp, #0 - 8002524: 6078 str r0, [r7, #4] + 800232a: b480 push {r7} + 800232c: b083 sub sp, #12 + 800232e: af00 add r7, sp, #0 + 8002330: 6078 str r0, [r7, #4] MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); - 8002526: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800252a: 685b ldr r3, [r3, #4] - 800252c: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000 - 8002530: 687b ldr r3, [r7, #4] - 8002532: 061b lsls r3, r3, #24 - 8002534: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 8002538: 4313 orrs r3, r2 - 800253a: 604b str r3, [r1, #4] -} - 800253c: bf00 nop - 800253e: 370c adds r7, #12 - 8002540: 46bd mov sp, r7 - 8002542: bc80 pop {r7} - 8002544: 4770 bx lr - -08002546 : + 8002332: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002336: 685b ldr r3, [r3, #4] + 8002338: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000 + 800233c: 687b ldr r3, [r7, #4] + 800233e: 061b lsls r3, r3, #24 + 8002340: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8002344: 4313 orrs r3, r2 + 8002346: 604b str r3, [r1, #4] +} + 8002348: bf00 nop + 800234a: 370c adds r7, #12 + 800234c: 46bd mov sp, r7 + 800234e: bc80 pop {r7} + 8002350: 4770 bx lr + +08002352 : * @brief Check if LSE oscillator Ready * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) { - 8002546: b480 push {r7} - 8002548: af00 add r7, sp, #0 + 8002352: b480 push {r7} + 8002354: af00 add r7, sp, #0 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); - 800254a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800254e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002552: f003 0302 and.w r3, r3, #2 - 8002556: 2b02 cmp r3, #2 - 8002558: d101 bne.n 800255e - 800255a: 2301 movs r3, #1 - 800255c: e000 b.n 8002560 - 800255e: 2300 movs r3, #0 -} - 8002560: 4618 mov r0, r3 - 8002562: 46bd mov sp, r7 - 8002564: bc80 pop {r7} - 8002566: 4770 bx lr - -08002568 : + 8002356: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800235a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800235e: f003 0302 and.w r3, r3, #2 + 8002362: 2b02 cmp r3, #2 + 8002364: d101 bne.n 800236a + 8002366: 2301 movs r3, #1 + 8002368: e000 b.n 800236c + 800236a: 2300 movs r3, #0 +} + 800236c: 4618 mov r0, r3 + 800236e: 46bd mov sp, r7 + 8002370: bc80 pop {r7} + 8002372: 4770 bx lr + +08002374 : * @brief Enable LSI Oscillator * @rmtoll CSR LSION LL_RCC_LSI_Enable * @retval None */ __STATIC_INLINE void LL_RCC_LSI_Enable(void) { - 8002568: b480 push {r7} - 800256a: af00 add r7, sp, #0 + 8002374: b480 push {r7} + 8002376: af00 add r7, sp, #0 SET_BIT(RCC->CSR, RCC_CSR_LSION); - 800256c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002570: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 - 8002574: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 8002578: f043 0301 orr.w r3, r3, #1 - 800257c: f8c2 3094 str.w r3, [r2, #148] ; 0x94 -} - 8002580: bf00 nop - 8002582: 46bd mov sp, r7 - 8002584: bc80 pop {r7} - 8002586: 4770 bx lr - -08002588 : + 8002378: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800237c: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 8002380: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8002384: f043 0301 orr.w r3, r3, #1 + 8002388: f8c2 3094 str.w r3, [r2, #148] ; 0x94 +} + 800238c: bf00 nop + 800238e: 46bd mov sp, r7 + 8002390: bc80 pop {r7} + 8002392: 4770 bx lr + +08002394 : * @brief Disable LSI Oscillator * @rmtoll CSR LSION LL_RCC_LSI_Disable * @retval None */ __STATIC_INLINE void LL_RCC_LSI_Disable(void) { - 8002588: b480 push {r7} - 800258a: af00 add r7, sp, #0 + 8002394: b480 push {r7} + 8002396: af00 add r7, sp, #0 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); - 800258c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002590: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 - 8002594: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 8002598: f023 0301 bic.w r3, r3, #1 - 800259c: f8c2 3094 str.w r3, [r2, #148] ; 0x94 -} - 80025a0: bf00 nop - 80025a2: 46bd mov sp, r7 - 80025a4: bc80 pop {r7} - 80025a6: 4770 bx lr - -080025a8 : + 8002398: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800239c: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 80023a0: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 80023a4: f023 0301 bic.w r3, r3, #1 + 80023a8: f8c2 3094 str.w r3, [r2, #148] ; 0x94 +} + 80023ac: bf00 nop + 80023ae: 46bd mov sp, r7 + 80023b0: bc80 pop {r7} + 80023b2: 4770 bx lr + +080023b4 : * @brief Check if LSI is Ready * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) { - 80025a8: b480 push {r7} - 80025aa: af00 add r7, sp, #0 + 80023b4: b480 push {r7} + 80023b6: af00 add r7, sp, #0 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL); - 80025ac: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80025b0: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 - 80025b4: f003 0302 and.w r3, r3, #2 - 80025b8: 2b02 cmp r3, #2 - 80025ba: d101 bne.n 80025c0 - 80025bc: 2301 movs r3, #1 - 80025be: e000 b.n 80025c2 - 80025c0: 2300 movs r3, #0 -} - 80025c2: 4618 mov r0, r3 - 80025c4: 46bd mov sp, r7 - 80025c6: bc80 pop {r7} - 80025c8: 4770 bx lr - -080025ca : + 80023b8: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80023bc: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 80023c0: f003 0302 and.w r3, r3, #2 + 80023c4: 2b02 cmp r3, #2 + 80023c6: d101 bne.n 80023cc + 80023c8: 2301 movs r3, #1 + 80023ca: e000 b.n 80023ce + 80023cc: 2300 movs r3, #0 +} + 80023ce: 4618 mov r0, r3 + 80023d0: 46bd mov sp, r7 + 80023d2: bc80 pop {r7} + 80023d4: 4770 bx lr + +080023d6 : * @brief Enable MSI oscillator * @rmtoll CR MSION LL_RCC_MSI_Enable * @retval None */ __STATIC_INLINE void LL_RCC_MSI_Enable(void) { - 80025ca: b480 push {r7} - 80025cc: af00 add r7, sp, #0 + 80023d6: b480 push {r7} + 80023d8: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_MSION); - 80025ce: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80025d2: 681b ldr r3, [r3, #0] - 80025d4: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 80025d8: f043 0301 orr.w r3, r3, #1 - 80025dc: 6013 str r3, [r2, #0] -} - 80025de: bf00 nop - 80025e0: 46bd mov sp, r7 - 80025e2: bc80 pop {r7} - 80025e4: 4770 bx lr - -080025e6 : + 80023da: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80023de: 681b ldr r3, [r3, #0] + 80023e0: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 80023e4: f043 0301 orr.w r3, r3, #1 + 80023e8: 6013 str r3, [r2, #0] +} + 80023ea: bf00 nop + 80023ec: 46bd mov sp, r7 + 80023ee: bc80 pop {r7} + 80023f0: 4770 bx lr + +080023f2 : * @brief Disable MSI oscillator * @rmtoll CR MSION LL_RCC_MSI_Disable * @retval None */ __STATIC_INLINE void LL_RCC_MSI_Disable(void) { - 80025e6: b480 push {r7} - 80025e8: af00 add r7, sp, #0 + 80023f2: b480 push {r7} + 80023f4: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_MSION); - 80025ea: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80025ee: 681b ldr r3, [r3, #0] - 80025f0: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 80025f4: f023 0301 bic.w r3, r3, #1 - 80025f8: 6013 str r3, [r2, #0] -} - 80025fa: bf00 nop - 80025fc: 46bd mov sp, r7 - 80025fe: bc80 pop {r7} - 8002600: 4770 bx lr - -08002602 : + 80023f6: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80023fa: 681b ldr r3, [r3, #0] + 80023fc: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8002400: f023 0301 bic.w r3, r3, #1 + 8002404: 6013 str r3, [r2, #0] +} + 8002406: bf00 nop + 8002408: 46bd mov sp, r7 + 800240a: bc80 pop {r7} + 800240c: 4770 bx lr + +0800240e : * @brief Check if MSI oscillator Ready * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void) { - 8002602: b480 push {r7} - 8002604: af00 add r7, sp, #0 + 800240e: b480 push {r7} + 8002410: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)) ? 1UL : 0UL); - 8002606: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800260a: 681b ldr r3, [r3, #0] - 800260c: f003 0302 and.w r3, r3, #2 - 8002610: 2b02 cmp r3, #2 - 8002612: d101 bne.n 8002618 - 8002614: 2301 movs r3, #1 - 8002616: e000 b.n 800261a - 8002618: 2300 movs r3, #0 -} - 800261a: 4618 mov r0, r3 - 800261c: 46bd mov sp, r7 - 800261e: bc80 pop {r7} - 8002620: 4770 bx lr - -08002622 : + 8002412: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002416: 681b ldr r3, [r3, #0] + 8002418: f003 0302 and.w r3, r3, #2 + 800241c: 2b02 cmp r3, #2 + 800241e: d101 bne.n 8002424 + 8002420: 2301 movs r3, #1 + 8002422: e000 b.n 8002426 + 8002424: 2300 movs r3, #0 +} + 8002426: 4618 mov r0, r3 + 8002428: 46bd mov sp, r7 + 800242a: bc80 pop {r7} + 800242c: 4770 bx lr + +0800242e : * @brief Check if MSI clock range is selected with MSIRANGE register * @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void) { - 8002622: b480 push {r7} - 8002624: af00 add r7, sp, #0 + 800242e: b480 push {r7} + 8002430: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL)) ? 1UL : 0UL); - 8002626: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800262a: 681b ldr r3, [r3, #0] - 800262c: f003 0308 and.w r3, r3, #8 - 8002630: 2b08 cmp r3, #8 - 8002632: d101 bne.n 8002638 - 8002634: 2301 movs r3, #1 - 8002636: e000 b.n 800263a - 8002638: 2300 movs r3, #0 -} - 800263a: 4618 mov r0, r3 - 800263c: 46bd mov sp, r7 - 800263e: bc80 pop {r7} - 8002640: 4770 bx lr - -08002642 : + 8002432: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002436: 681b ldr r3, [r3, #0] + 8002438: f003 0308 and.w r3, r3, #8 + 800243c: 2b08 cmp r3, #8 + 800243e: d101 bne.n 8002444 + 8002440: 2301 movs r3, #1 + 8002442: e000 b.n 8002446 + 8002444: 2300 movs r3, #0 +} + 8002446: 4618 mov r0, r3 + 8002448: 46bd mov sp, r7 + 800244a: bc80 pop {r7} + 800244c: 4770 bx lr + +0800244e : * @arg @ref LL_RCC_MSIRANGE_9 * @arg @ref LL_RCC_MSIRANGE_10 * @arg @ref LL_RCC_MSIRANGE_11 */ __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void) { - 8002642: b480 push {r7} - 8002644: af00 add r7, sp, #0 + 800244e: b480 push {r7} + 8002450: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)); - 8002646: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800264a: 681b ldr r3, [r3, #0] - 800264c: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 8002452: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002456: 681b ldr r3, [r3, #0] + 8002458: f003 03f0 and.w r3, r3, #240 ; 0xf0 } - 8002650: 4618 mov r0, r3 - 8002652: 46bd mov sp, r7 - 8002654: bc80 pop {r7} - 8002656: 4770 bx lr + 800245c: 4618 mov r0, r3 + 800245e: 46bd mov sp, r7 + 8002460: bc80 pop {r7} + 8002462: 4770 bx lr -08002658 : +08002464 : * @arg @ref LL_RCC_MSISRANGE_5 * @arg @ref LL_RCC_MSISRANGE_6 * @arg @ref LL_RCC_MSISRANGE_7 */ __STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void) { - 8002658: b480 push {r7} - 800265a: af00 add r7, sp, #0 + 8002464: b480 push {r7} + 8002466: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE)); - 800265c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002660: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 - 8002664: f403 6370 and.w r3, r3, #3840 ; 0xf00 + 8002468: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800246c: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 8002470: f403 6370 and.w r3, r3, #3840 ; 0xf00 } - 8002668: 4618 mov r0, r3 - 800266a: 46bd mov sp, r7 - 800266c: bc80 pop {r7} - 800266e: 4770 bx lr + 8002474: 4618 mov r0, r3 + 8002476: 46bd mov sp, r7 + 8002478: bc80 pop {r7} + 800247a: 4770 bx lr -08002670 : +0800247c : * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming * @param Value Between Min_Data = 0 and Max_Data = 255 * @retval None */ __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value) { - 8002670: b480 push {r7} - 8002672: b083 sub sp, #12 - 8002674: af00 add r7, sp, #0 - 8002676: 6078 str r0, [r7, #4] + 800247c: b480 push {r7} + 800247e: b083 sub sp, #12 + 8002480: af00 add r7, sp, #0 + 8002482: 6078 str r0, [r7, #4] MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos); - 8002678: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800267c: 685b ldr r3, [r3, #4] - 800267e: f423 427f bic.w r2, r3, #65280 ; 0xff00 - 8002682: 687b ldr r3, [r7, #4] - 8002684: 021b lsls r3, r3, #8 - 8002686: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 800268a: 4313 orrs r3, r2 - 800268c: 604b str r3, [r1, #4] -} - 800268e: bf00 nop - 8002690: 370c adds r7, #12 - 8002692: 46bd mov sp, r7 - 8002694: bc80 pop {r7} - 8002696: 4770 bx lr - -08002698 : + 8002484: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002488: 685b ldr r3, [r3, #4] + 800248a: f423 427f bic.w r2, r3, #65280 ; 0xff00 + 800248e: 687b ldr r3, [r7, #4] + 8002490: 021b lsls r3, r3, #8 + 8002492: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8002496: 4313 orrs r3, r2 + 8002498: 604b str r3, [r1, #4] +} + 800249a: bf00 nop + 800249c: 370c adds r7, #12 + 800249e: 46bd mov sp, r7 + 80024a0: bc80 pop {r7} + 80024a2: 4770 bx lr + +080024a4 : * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL * @retval None */ __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) { - 8002698: b480 push {r7} - 800269a: b083 sub sp, #12 - 800269c: af00 add r7, sp, #0 - 800269e: 6078 str r0, [r7, #4] + 80024a4: b480 push {r7} + 80024a6: b083 sub sp, #12 + 80024a8: af00 add r7, sp, #0 + 80024aa: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); - 80026a0: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80026a4: 689b ldr r3, [r3, #8] - 80026a6: f023 0203 bic.w r2, r3, #3 - 80026aa: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 80026ae: 687b ldr r3, [r7, #4] - 80026b0: 4313 orrs r3, r2 - 80026b2: 608b str r3, [r1, #8] -} - 80026b4: bf00 nop - 80026b6: 370c adds r7, #12 - 80026b8: 46bd mov sp, r7 - 80026ba: bc80 pop {r7} - 80026bc: 4770 bx lr - -080026be : + 80024ac: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80024b0: 689b ldr r3, [r3, #8] + 80024b2: f023 0203 bic.w r2, r3, #3 + 80024b6: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80024ba: 687b ldr r3, [r7, #4] + 80024bc: 4313 orrs r3, r2 + 80024be: 608b str r3, [r1, #8] +} + 80024c0: bf00 nop + 80024c2: 370c adds r7, #12 + 80024c4: 46bd mov sp, r7 + 80024c6: bc80 pop {r7} + 80024c8: 4770 bx lr + +080024ca : * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL */ __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) { - 80026be: b480 push {r7} - 80026c0: af00 add r7, sp, #0 + 80024ca: b480 push {r7} + 80024cc: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); - 80026c2: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80026c6: 689b ldr r3, [r3, #8] - 80026c8: f003 030c and.w r3, r3, #12 + 80024ce: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80024d2: 689b ldr r3, [r3, #8] + 80024d4: f003 030c and.w r3, r3, #12 } - 80026cc: 4618 mov r0, r3 - 80026ce: 46bd mov sp, r7 - 80026d0: bc80 pop {r7} - 80026d2: 4770 bx lr + 80024d8: 4618 mov r0, r3 + 80024da: 46bd mov sp, r7 + 80024dc: bc80 pop {r7} + 80024de: 4770 bx lr -080026d4 : +080024e0 : * @arg @ref LL_RCC_SYSCLK_DIV_256 * @arg @ref LL_RCC_SYSCLK_DIV_512 * @retval None */ __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) { - 80026d4: b480 push {r7} - 80026d6: b083 sub sp, #12 - 80026d8: af00 add r7, sp, #0 - 80026da: 6078 str r0, [r7, #4] + 80024e0: b480 push {r7} + 80024e2: b083 sub sp, #12 + 80024e4: af00 add r7, sp, #0 + 80024e6: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); - 80026dc: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80026e0: 689b ldr r3, [r3, #8] - 80026e2: f023 02f0 bic.w r2, r3, #240 ; 0xf0 - 80026e6: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 80026ea: 687b ldr r3, [r7, #4] - 80026ec: 4313 orrs r3, r2 - 80026ee: 608b str r3, [r1, #8] -} - 80026f0: bf00 nop - 80026f2: 370c adds r7, #12 - 80026f4: 46bd mov sp, r7 - 80026f6: bc80 pop {r7} - 80026f8: 4770 bx lr - -080026fa : + 80024e8: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80024ec: 689b ldr r3, [r3, #8] + 80024ee: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 80024f2: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80024f6: 687b ldr r3, [r7, #4] + 80024f8: 4313 orrs r3, r2 + 80024fa: 608b str r3, [r1, #8] +} + 80024fc: bf00 nop + 80024fe: 370c adds r7, #12 + 8002500: 46bd mov sp, r7 + 8002502: bc80 pop {r7} + 8002504: 4770 bx lr + +08002506 : * @arg @ref LL_RCC_SYSCLK_DIV_256 * @arg @ref LL_RCC_SYSCLK_DIV_512 * @retval None */ __STATIC_INLINE void LL_RCC_SetAHB3Prescaler(uint32_t Prescaler) { - 80026fa: b480 push {r7} - 80026fc: b083 sub sp, #12 - 80026fe: af00 add r7, sp, #0 - 8002700: 6078 str r0, [r7, #4] + 8002506: b480 push {r7} + 8002508: b083 sub sp, #12 + 800250a: af00 add r7, sp, #0 + 800250c: 6078 str r0, [r7, #4] MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE, Prescaler >> 4); - 8002702: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002706: f8d3 3108 ldr.w r3, [r3, #264] ; 0x108 - 800270a: f023 020f bic.w r2, r3, #15 - 800270e: 687b ldr r3, [r7, #4] - 8002710: 091b lsrs r3, r3, #4 - 8002712: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 8002716: 4313 orrs r3, r2 - 8002718: f8c1 3108 str.w r3, [r1, #264] ; 0x108 -} - 800271c: bf00 nop - 800271e: 370c adds r7, #12 - 8002720: 46bd mov sp, r7 - 8002722: bc80 pop {r7} - 8002724: 4770 bx lr - -08002726 : + 800250e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002512: f8d3 3108 ldr.w r3, [r3, #264] ; 0x108 + 8002516: f023 020f bic.w r2, r3, #15 + 800251a: 687b ldr r3, [r7, #4] + 800251c: 091b lsrs r3, r3, #4 + 800251e: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8002522: 4313 orrs r3, r2 + 8002524: f8c1 3108 str.w r3, [r1, #264] ; 0x108 +} + 8002528: bf00 nop + 800252a: 370c adds r7, #12 + 800252c: 46bd mov sp, r7 + 800252e: bc80 pop {r7} + 8002530: 4770 bx lr + +08002532 : * @arg @ref LL_RCC_APB1_DIV_8 * @arg @ref LL_RCC_APB1_DIV_16 * @retval None */ __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) { - 8002726: b480 push {r7} - 8002728: b083 sub sp, #12 - 800272a: af00 add r7, sp, #0 - 800272c: 6078 str r0, [r7, #4] + 8002532: b480 push {r7} + 8002534: b083 sub sp, #12 + 8002536: af00 add r7, sp, #0 + 8002538: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); - 800272e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002732: 689b ldr r3, [r3, #8] - 8002734: f423 62e0 bic.w r2, r3, #1792 ; 0x700 - 8002738: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 800273c: 687b ldr r3, [r7, #4] - 800273e: 4313 orrs r3, r2 - 8002740: 608b str r3, [r1, #8] -} - 8002742: bf00 nop - 8002744: 370c adds r7, #12 - 8002746: 46bd mov sp, r7 - 8002748: bc80 pop {r7} - 800274a: 4770 bx lr - -0800274c : + 800253a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800253e: 689b ldr r3, [r3, #8] + 8002540: f423 62e0 bic.w r2, r3, #1792 ; 0x700 + 8002544: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8002548: 687b ldr r3, [r7, #4] + 800254a: 4313 orrs r3, r2 + 800254c: 608b str r3, [r1, #8] +} + 800254e: bf00 nop + 8002550: 370c adds r7, #12 + 8002552: 46bd mov sp, r7 + 8002554: bc80 pop {r7} + 8002556: 4770 bx lr + +08002558 : * @arg @ref LL_RCC_APB2_DIV_8 * @arg @ref LL_RCC_APB2_DIV_16 * @retval None */ __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) { - 800274c: b480 push {r7} - 800274e: b083 sub sp, #12 - 8002750: af00 add r7, sp, #0 - 8002752: 6078 str r0, [r7, #4] + 8002558: b480 push {r7} + 800255a: b083 sub sp, #12 + 800255c: af00 add r7, sp, #0 + 800255e: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); - 8002754: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002758: 689b ldr r3, [r3, #8] - 800275a: f423 5260 bic.w r2, r3, #14336 ; 0x3800 - 800275e: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 8002762: 687b ldr r3, [r7, #4] - 8002764: 4313 orrs r3, r2 - 8002766: 608b str r3, [r1, #8] -} - 8002768: bf00 nop - 800276a: 370c adds r7, #12 - 800276c: 46bd mov sp, r7 - 800276e: bc80 pop {r7} - 8002770: 4770 bx lr - -08002772 : + 8002560: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002564: 689b ldr r3, [r3, #8] + 8002566: f423 5260 bic.w r2, r3, #14336 ; 0x3800 + 800256a: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 800256e: 687b ldr r3, [r7, #4] + 8002570: 4313 orrs r3, r2 + 8002572: 608b str r3, [r1, #8] +} + 8002574: bf00 nop + 8002576: 370c adds r7, #12 + 8002578: 46bd mov sp, r7 + 800257a: bc80 pop {r7} + 800257c: 4770 bx lr + +0800257e : * @arg @ref LL_RCC_SYSCLK_DIV_128 * @arg @ref LL_RCC_SYSCLK_DIV_256 * @arg @ref LL_RCC_SYSCLK_DIV_512 */ __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) { - 8002772: b480 push {r7} - 8002774: af00 add r7, sp, #0 + 800257e: b480 push {r7} + 8002580: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); - 8002776: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800277a: 689b ldr r3, [r3, #8] - 800277c: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 8002582: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002586: 689b ldr r3, [r3, #8] + 8002588: f003 03f0 and.w r3, r3, #240 ; 0xf0 } - 8002780: 4618 mov r0, r3 - 8002782: 46bd mov sp, r7 - 8002784: bc80 pop {r7} - 8002786: 4770 bx lr + 800258c: 4618 mov r0, r3 + 800258e: 46bd mov sp, r7 + 8002590: bc80 pop {r7} + 8002592: 4770 bx lr -08002788 : +08002594 : * @arg @ref LL_RCC_SYSCLK_DIV_128 * @arg @ref LL_RCC_SYSCLK_DIV_256 * @arg @ref LL_RCC_SYSCLK_DIV_512 */ __STATIC_INLINE uint32_t LL_RCC_GetAHB3Prescaler(void) { - 8002788: b480 push {r7} - 800278a: af00 add r7, sp, #0 + 8002594: b480 push {r7} + 8002596: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE) << 4); - 800278c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002790: f8d3 3108 ldr.w r3, [r3, #264] ; 0x108 - 8002794: 011b lsls r3, r3, #4 - 8002796: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 8002598: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800259c: f8d3 3108 ldr.w r3, [r3, #264] ; 0x108 + 80025a0: 011b lsls r3, r3, #4 + 80025a2: f003 03f0 and.w r3, r3, #240 ; 0xf0 } - 800279a: 4618 mov r0, r3 - 800279c: 46bd mov sp, r7 - 800279e: bc80 pop {r7} - 80027a0: 4770 bx lr + 80025a6: 4618 mov r0, r3 + 80025a8: 46bd mov sp, r7 + 80025aa: bc80 pop {r7} + 80025ac: 4770 bx lr -080027a2 : +080025ae : * @arg @ref LL_RCC_APB1_DIV_4 * @arg @ref LL_RCC_APB1_DIV_8 * @arg @ref LL_RCC_APB1_DIV_16 */ __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) { - 80027a2: b480 push {r7} - 80027a4: af00 add r7, sp, #0 + 80025ae: b480 push {r7} + 80025b0: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); - 80027a6: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80027aa: 689b ldr r3, [r3, #8] - 80027ac: f403 63e0 and.w r3, r3, #1792 ; 0x700 + 80025b2: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80025b6: 689b ldr r3, [r3, #8] + 80025b8: f403 63e0 and.w r3, r3, #1792 ; 0x700 } - 80027b0: 4618 mov r0, r3 - 80027b2: 46bd mov sp, r7 - 80027b4: bc80 pop {r7} - 80027b6: 4770 bx lr + 80025bc: 4618 mov r0, r3 + 80025be: 46bd mov sp, r7 + 80025c0: bc80 pop {r7} + 80025c2: 4770 bx lr -080027b8 : +080025c4 : * @arg @ref LL_RCC_APB2_DIV_4 * @arg @ref LL_RCC_APB2_DIV_8 * @arg @ref LL_RCC_APB2_DIV_16 */ __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) { - 80027b8: b480 push {r7} - 80027ba: af00 add r7, sp, #0 + 80025c4: b480 push {r7} + 80025c6: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); - 80027bc: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80027c0: 689b ldr r3, [r3, #8] - 80027c2: f403 5360 and.w r3, r3, #14336 ; 0x3800 + 80025c8: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80025cc: 689b ldr r3, [r3, #8] + 80025ce: f403 5360 and.w r3, r3, #14336 ; 0x3800 } - 80027c6: 4618 mov r0, r3 - 80027c8: 46bd mov sp, r7 - 80027ca: bc80 pop {r7} - 80027cc: 4770 bx lr + 80025d2: 4618 mov r0, r3 + 80025d4: 46bd mov sp, r7 + 80025d6: bc80 pop {r7} + 80025d8: 4770 bx lr -080027ce : +080025da : * @brief Enable PLL * @rmtoll CR PLLON LL_RCC_PLL_Enable * @retval None */ __STATIC_INLINE void LL_RCC_PLL_Enable(void) { - 80027ce: b480 push {r7} - 80027d0: af00 add r7, sp, #0 + 80025da: b480 push {r7} + 80025dc: af00 add r7, sp, #0 SET_BIT(RCC->CR, RCC_CR_PLLON); - 80027d2: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80027d6: 681b ldr r3, [r3, #0] - 80027d8: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 80027dc: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 - 80027e0: 6013 str r3, [r2, #0] -} - 80027e2: bf00 nop - 80027e4: 46bd mov sp, r7 - 80027e6: bc80 pop {r7} - 80027e8: 4770 bx lr - -080027ea : + 80025de: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80025e2: 681b ldr r3, [r3, #0] + 80025e4: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 80025e8: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 80025ec: 6013 str r3, [r2, #0] +} + 80025ee: bf00 nop + 80025f0: 46bd mov sp, r7 + 80025f2: bc80 pop {r7} + 80025f4: 4770 bx lr + +080025f6 : * @note Cannot be disabled if the PLL clock is used as the system clock * @rmtoll CR PLLON LL_RCC_PLL_Disable * @retval None */ __STATIC_INLINE void LL_RCC_PLL_Disable(void) { - 80027ea: b480 push {r7} - 80027ec: af00 add r7, sp, #0 + 80025f6: b480 push {r7} + 80025f8: af00 add r7, sp, #0 CLEAR_BIT(RCC->CR, RCC_CR_PLLON); - 80027ee: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80027f2: 681b ldr r3, [r3, #0] - 80027f4: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 80027f8: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 - 80027fc: 6013 str r3, [r2, #0] -} - 80027fe: bf00 nop - 8002800: 46bd mov sp, r7 - 8002802: bc80 pop {r7} - 8002804: 4770 bx lr - -08002806 : + 80025fa: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80025fe: 681b ldr r3, [r3, #0] + 8002600: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8002604: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 8002608: 6013 str r3, [r2, #0] +} + 800260a: bf00 nop + 800260c: 46bd mov sp, r7 + 800260e: bc80 pop {r7} + 8002610: 4770 bx lr + +08002612 : * @brief Check if PLL Ready * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) { - 8002806: b480 push {r7} - 8002808: af00 add r7, sp, #0 + 8002612: b480 push {r7} + 8002614: af00 add r7, sp, #0 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL); - 800280a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800280e: 681b ldr r3, [r3, #0] - 8002810: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8002814: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 - 8002818: d101 bne.n 800281e - 800281a: 2301 movs r3, #1 - 800281c: e000 b.n 8002820 - 800281e: 2300 movs r3, #0 -} - 8002820: 4618 mov r0, r3 - 8002822: 46bd mov sp, r7 - 8002824: bc80 pop {r7} - 8002826: 4770 bx lr - -08002828 : + 8002616: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800261a: 681b ldr r3, [r3, #0] + 800261c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8002620: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 + 8002624: d101 bne.n 800262a + 8002626: 2301 movs r3, #1 + 8002628: e000 b.n 800262c + 800262a: 2300 movs r3, #0 +} + 800262c: 4618 mov r0, r3 + 800262e: 46bd mov sp, r7 + 8002630: bc80 pop {r7} + 8002632: 4770 bx lr + +08002634 : * @brief Get Main PLL multiplication factor for VCO * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN * @retval Between 6 and 127 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) { - 8002828: b480 push {r7} - 800282a: af00 add r7, sp, #0 + 8002634: b480 push {r7} + 8002636: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - 800282c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002830: 68db ldr r3, [r3, #12] - 8002832: 0a1b lsrs r3, r3, #8 - 8002834: f003 037f and.w r3, r3, #127 ; 0x7f + 8002638: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800263c: 68db ldr r3, [r3, #12] + 800263e: 0a1b lsrs r3, r3, #8 + 8002640: f003 037f and.w r3, r3, #127 ; 0x7f } - 8002838: 4618 mov r0, r3 - 800283a: 46bd mov sp, r7 - 800283c: bc80 pop {r7} - 800283e: 4770 bx lr + 8002644: 4618 mov r0, r3 + 8002646: 46bd mov sp, r7 + 8002648: bc80 pop {r7} + 800264a: 4770 bx lr -08002840 : +0800264c : * @arg @ref LL_RCC_PLLR_DIV_6 * @arg @ref LL_RCC_PLLR_DIV_7 * @arg @ref LL_RCC_PLLR_DIV_8 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) { - 8002840: b480 push {r7} - 8002842: af00 add r7, sp, #0 + 800264c: b480 push {r7} + 800264e: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); - 8002844: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002848: 68db ldr r3, [r3, #12] - 800284a: f003 4360 and.w r3, r3, #3758096384 ; 0xe0000000 + 8002650: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002654: 68db ldr r3, [r3, #12] + 8002656: f003 4360 and.w r3, r3, #3758096384 ; 0xe0000000 } - 800284e: 4618 mov r0, r3 - 8002850: 46bd mov sp, r7 - 8002852: bc80 pop {r7} - 8002854: 4770 bx lr + 800265a: 4618 mov r0, r3 + 800265c: 46bd mov sp, r7 + 800265e: bc80 pop {r7} + 8002660: 4770 bx lr -08002856 : +08002662 : * @arg @ref LL_RCC_PLLM_DIV_6 * @arg @ref LL_RCC_PLLM_DIV_7 * @arg @ref LL_RCC_PLLM_DIV_8 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) { - 8002856: b480 push {r7} - 8002858: af00 add r7, sp, #0 + 8002662: b480 push {r7} + 8002664: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); - 800285a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800285e: 68db ldr r3, [r3, #12] - 8002860: f003 0370 and.w r3, r3, #112 ; 0x70 + 8002666: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800266a: 68db ldr r3, [r3, #12] + 800266c: f003 0370 and.w r3, r3, #112 ; 0x70 } - 8002864: 4618 mov r0, r3 - 8002866: 46bd mov sp, r7 - 8002868: bc80 pop {r7} - 800286a: 4770 bx lr + 8002670: 4618 mov r0, r3 + 8002672: 46bd mov sp, r7 + 8002674: bc80 pop {r7} + 8002676: 4770 bx lr -0800286c : +08002678 : * @arg @ref LL_RCC_PLLSOURCE_MSI * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) { - 800286c: b480 push {r7} - 800286e: af00 add r7, sp, #0 + 8002678: b480 push {r7} + 800267a: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); - 8002870: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002874: 68db ldr r3, [r3, #12] - 8002876: f003 0303 and.w r3, r3, #3 + 800267c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002680: 68db ldr r3, [r3, #12] + 8002682: f003 0303 and.w r3, r3, #3 } - 800287a: 4618 mov r0, r3 - 800287c: 46bd mov sp, r7 - 800287e: bc80 pop {r7} - 8002880: 4770 bx lr + 8002686: 4618 mov r0, r3 + 8002688: 46bd mov sp, r7 + 800268a: bc80 pop {r7} + 800268c: 4770 bx lr -08002882 : +0800268e : * @brief Check if HCLK1 prescaler flag value has been applied or not * @rmtoll CFGR HPREF LL_RCC_IsActiveFlag_HPRE * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE(void) { - 8002882: b480 push {r7} - 8002884: af00 add r7, sp, #0 + 800268e: b480 push {r7} + 8002690: af00 add r7, sp, #0 return ((READ_BIT(RCC->CFGR, RCC_CFGR_HPREF) == (RCC_CFGR_HPREF)) ? 1UL : 0UL); - 8002886: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800288a: 689b ldr r3, [r3, #8] - 800288c: f403 3380 and.w r3, r3, #65536 ; 0x10000 - 8002890: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 - 8002894: d101 bne.n 800289a - 8002896: 2301 movs r3, #1 - 8002898: e000 b.n 800289c - 800289a: 2300 movs r3, #0 -} - 800289c: 4618 mov r0, r3 - 800289e: 46bd mov sp, r7 - 80028a0: bc80 pop {r7} - 80028a2: 4770 bx lr - -080028a4 : + 8002692: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002696: 689b ldr r3, [r3, #8] + 8002698: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 800269c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 80026a0: d101 bne.n 80026a6 + 80026a2: 2301 movs r3, #1 + 80026a4: e000 b.n 80026a8 + 80026a6: 2300 movs r3, #0 +} + 80026a8: 4618 mov r0, r3 + 80026aa: 46bd mov sp, r7 + 80026ac: bc80 pop {r7} + 80026ae: 4770 bx lr + +080026b0 : * @brief Check if HCLK3 prescaler flag value has been applied or not * @rmtoll EXTCFGR SHDHPREF LL_RCC_IsActiveFlag_SHDHPRE * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE(void) { - 80028a4: b480 push {r7} - 80028a6: af00 add r7, sp, #0 + 80026b0: b480 push {r7} + 80026b2: af00 add r7, sp, #0 return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPREF) == (RCC_EXTCFGR_SHDHPREF)) ? 1UL : 0UL); - 80028a8: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80028ac: f8d3 3108 ldr.w r3, [r3, #264] ; 0x108 - 80028b0: f403 3380 and.w r3, r3, #65536 ; 0x10000 - 80028b4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 - 80028b8: d101 bne.n 80028be - 80028ba: 2301 movs r3, #1 - 80028bc: e000 b.n 80028c0 - 80028be: 2300 movs r3, #0 -} - 80028c0: 4618 mov r0, r3 - 80028c2: 46bd mov sp, r7 - 80028c4: bc80 pop {r7} - 80028c6: 4770 bx lr - -080028c8 : + 80026b4: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80026b8: f8d3 3108 ldr.w r3, [r3, #264] ; 0x108 + 80026bc: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 80026c0: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 80026c4: d101 bne.n 80026ca + 80026c6: 2301 movs r3, #1 + 80026c8: e000 b.n 80026cc + 80026ca: 2300 movs r3, #0 +} + 80026cc: 4618 mov r0, r3 + 80026ce: 46bd mov sp, r7 + 80026d0: bc80 pop {r7} + 80026d2: 4770 bx lr + +080026d4 : * @brief Check if PLCK1 prescaler flag value has been applied or not * @rmtoll CFGR PPRE1F LL_RCC_IsActiveFlag_PPRE1 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1(void) { - 80028c8: b480 push {r7} - 80028ca: af00 add r7, sp, #0 + 80026d4: b480 push {r7} + 80026d6: af00 add r7, sp, #0 return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1F) == (RCC_CFGR_PPRE1F)) ? 1UL : 0UL); - 80028cc: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80028d0: 689b ldr r3, [r3, #8] - 80028d2: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 80028d6: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 - 80028da: d101 bne.n 80028e0 - 80028dc: 2301 movs r3, #1 - 80028de: e000 b.n 80028e2 - 80028e0: 2300 movs r3, #0 -} - 80028e2: 4618 mov r0, r3 - 80028e4: 46bd mov sp, r7 - 80028e6: bc80 pop {r7} - 80028e8: 4770 bx lr - -080028ea : + 80026d8: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80026dc: 689b ldr r3, [r3, #8] + 80026de: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80026e2: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 + 80026e6: d101 bne.n 80026ec + 80026e8: 2301 movs r3, #1 + 80026ea: e000 b.n 80026ee + 80026ec: 2300 movs r3, #0 +} + 80026ee: 4618 mov r0, r3 + 80026f0: 46bd mov sp, r7 + 80026f2: bc80 pop {r7} + 80026f4: 4770 bx lr + +080026f6 : * @brief Check if PLCK2 prescaler flag value has been applied or not * @rmtoll CFGR PPRE2F LL_RCC_IsActiveFlag_PPRE2 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2(void) { - 80028ea: b480 push {r7} - 80028ec: af00 add r7, sp, #0 + 80026f6: b480 push {r7} + 80026f8: af00 add r7, sp, #0 return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2F) == (RCC_CFGR_PPRE2F)) ? 1UL : 0UL); - 80028ee: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80028f2: 689b ldr r3, [r3, #8] - 80028f4: f403 2380 and.w r3, r3, #262144 ; 0x40000 - 80028f8: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 - 80028fc: d101 bne.n 8002902 - 80028fe: 2301 movs r3, #1 - 8002900: e000 b.n 8002904 - 8002902: 2300 movs r3, #0 -} - 8002904: 4618 mov r0, r3 - 8002906: 46bd mov sp, r7 - 8002908: bc80 pop {r7} - 800290a: 4770 bx lr - -0800290c : + 80026fa: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80026fe: 689b ldr r3, [r3, #8] + 8002700: f403 2380 and.w r3, r3, #262144 ; 0x40000 + 8002704: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 + 8002708: d101 bne.n 800270e + 800270a: 2301 movs r3, #1 + 800270c: e000 b.n 8002710 + 800270e: 2300 movs r3, #0 +} + 8002710: 4618 mov r0, r3 + 8002712: 46bd mov sp, r7 + 8002714: bc80 pop {r7} + 8002716: 4770 bx lr + +08002718 : * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - 800290c: b580 push {r7, lr} - 800290e: b088 sub sp, #32 - 8002910: af00 add r7, sp, #0 - 8002912: 6078 str r0, [r7, #4] + 8002718: b580 push {r7, lr} + 800271a: b088 sub sp, #32 + 800271c: af00 add r7, sp, #0 + 800271e: 6078 str r0, [r7, #4] uint32_t sysclk_source; uint32_t pll_config; HAL_StatusTypeDef status; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) - 8002914: 687b ldr r3, [r7, #4] - 8002916: 2b00 cmp r3, #0 - 8002918: d101 bne.n 800291e + 8002720: 687b ldr r3, [r7, #4] + 8002722: 2b00 cmp r3, #0 + 8002724: d101 bne.n 800272a { return HAL_ERROR; - 800291a: 2301 movs r3, #1 - 800291c: e36f b.n 8002ffe + 8002726: 2301 movs r3, #1 + 8002728: e36f b.n 8002e0a } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); - 800291e: f7ff fece bl 80026be - 8002922: 61f8 str r0, [r7, #28] + 800272a: f7ff fece bl 80024ca + 800272e: 61f8 str r0, [r7, #28] pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); - 8002924: f7ff ffa2 bl 800286c - 8002928: 61b8 str r0, [r7, #24] + 8002730: f7ff ffa2 bl 8002678 + 8002734: 61b8 str r0, [r7, #24] /*----------------------------- MSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) - 800292a: 687b ldr r3, [r7, #4] - 800292c: 681b ldr r3, [r3, #0] - 800292e: f003 0320 and.w r3, r3, #32 - 8002932: 2b00 cmp r3, #0 - 8002934: f000 80c4 beq.w 8002ac0 + 8002736: 687b ldr r3, [r7, #4] + 8002738: 681b ldr r3, [r3, #0] + 800273a: f003 0320 and.w r3, r3, #32 + 800273e: 2b00 cmp r3, #0 + 8002740: f000 80c4 beq.w 80028cc assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); assert_param(IS_RCC_MSI_CALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); /* When the MSI is used as system clock it will not be disabled */ if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || - 8002938: 69fb ldr r3, [r7, #28] - 800293a: 2b00 cmp r3, #0 - 800293c: d005 beq.n 800294a - 800293e: 69fb ldr r3, [r7, #28] - 8002940: 2b0c cmp r3, #12 - 8002942: d176 bne.n 8002a32 + 8002744: 69fb ldr r3, [r7, #28] + 8002746: 2b00 cmp r3, #0 + 8002748: d005 beq.n 8002756 + 800274a: 69fb ldr r3, [r7, #28] + 800274c: 2b0c cmp r3, #12 + 800274e: d176 bne.n 800283e ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI))) - 8002944: 69bb ldr r3, [r7, #24] - 8002946: 2b01 cmp r3, #1 - 8002948: d173 bne.n 8002a32 + 8002750: 69bb ldr r3, [r7, #24] + 8002752: 2b01 cmp r3, #1 + 8002754: d173 bne.n 800283e { if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) - 800294a: 687b ldr r3, [r7, #4] - 800294c: 6a1b ldr r3, [r3, #32] - 800294e: 2b00 cmp r3, #0 - 8002950: d101 bne.n 8002956 + 8002756: 687b ldr r3, [r7, #4] + 8002758: 6a1b ldr r3, [r3, #32] + 800275a: 2b00 cmp r3, #0 + 800275c: d101 bne.n 8002762 { return HAL_ERROR; - 8002952: 2301 movs r3, #1 - 8002954: e353 b.n 8002ffe + 800275e: 2301 movs r3, #1 + 8002760: e353 b.n 8002e0a else { /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the AHB3 clock and the supply voltage of the device. */ if (RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) - 8002956: 687b ldr r3, [r7, #4] - 8002958: 6a9a ldr r2, [r3, #40] ; 0x28 - 800295a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800295e: 681b ldr r3, [r3, #0] - 8002960: f003 0308 and.w r3, r3, #8 - 8002964: 2b00 cmp r3, #0 - 8002966: d005 beq.n 8002974 - 8002968: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800296c: 681b ldr r3, [r3, #0] - 800296e: f003 03f0 and.w r3, r3, #240 ; 0xf0 - 8002972: e006 b.n 8002982 - 8002974: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002978: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 - 800297c: 091b lsrs r3, r3, #4 - 800297e: f003 03f0 and.w r3, r3, #240 ; 0xf0 - 8002982: 4293 cmp r3, r2 - 8002984: d222 bcs.n 80029cc + 8002762: 687b ldr r3, [r7, #4] + 8002764: 6a9a ldr r2, [r3, #40] ; 0x28 + 8002766: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800276a: 681b ldr r3, [r3, #0] + 800276c: f003 0308 and.w r3, r3, #8 + 8002770: 2b00 cmp r3, #0 + 8002772: d005 beq.n 8002780 + 8002774: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002778: 681b ldr r3, [r3, #0] + 800277a: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 800277e: e006 b.n 800278e + 8002780: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002784: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 8002788: 091b lsrs r3, r3, #4 + 800278a: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 800278e: 4293 cmp r3, r2 + 8002790: d222 bcs.n 80027d8 { /* First increase number of wait states update if necessary */ if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) - 8002986: 687b ldr r3, [r7, #4] - 8002988: 6a9b ldr r3, [r3, #40] ; 0x28 - 800298a: 4618 mov r0, r3 - 800298c: f000 fd3c bl 8003408 - 8002990: 4603 mov r3, r0 - 8002992: 2b00 cmp r3, #0 - 8002994: d001 beq.n 800299a + 8002792: 687b ldr r3, [r7, #4] + 8002794: 6a9b ldr r3, [r3, #40] ; 0x28 + 8002796: 4618 mov r0, r3 + 8002798: f000 fd3c bl 8003214 + 800279c: 4603 mov r3, r0 + 800279e: 2b00 cmp r3, #0 + 80027a0: d001 beq.n 80027a6 { return HAL_ERROR; - 8002996: 2301 movs r3, #1 - 8002998: e331 b.n 8002ffe + 80027a2: 2301 movs r3, #1 + 80027a4: e331 b.n 8002e0a } /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - 800299a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800299e: 681b ldr r3, [r3, #0] - 80029a0: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 80029a4: f043 0308 orr.w r3, r3, #8 - 80029a8: 6013 str r3, [r2, #0] - 80029aa: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80029ae: 681b ldr r3, [r3, #0] - 80029b0: f023 02f0 bic.w r2, r3, #240 ; 0xf0 - 80029b4: 687b ldr r3, [r7, #4] - 80029b6: 6a9b ldr r3, [r3, #40] ; 0x28 - 80029b8: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 80029bc: 4313 orrs r3, r2 - 80029be: 600b str r3, [r1, #0] + 80027a6: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80027aa: 681b ldr r3, [r3, #0] + 80027ac: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 80027b0: f043 0308 orr.w r3, r3, #8 + 80027b4: 6013 str r3, [r2, #0] + 80027b6: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80027ba: 681b ldr r3, [r3, #0] + 80027bc: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 80027c0: 687b ldr r3, [r7, #4] + 80027c2: 6a9b ldr r3, [r3, #40] ; 0x28 + 80027c4: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80027c8: 4313 orrs r3, r2 + 80027ca: 600b str r3, [r1, #0] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - 80029c0: 687b ldr r3, [r7, #4] - 80029c2: 6a5b ldr r3, [r3, #36] ; 0x24 - 80029c4: 4618 mov r0, r3 - 80029c6: f7ff fe53 bl 8002670 - 80029ca: e021 b.n 8002a10 + 80027cc: 687b ldr r3, [r7, #4] + 80027ce: 6a5b ldr r3, [r3, #36] ; 0x24 + 80027d0: 4618 mov r0, r3 + 80027d2: f7ff fe53 bl 800247c + 80027d6: e021 b.n 800281c } else { /* Else, keep current flash latency while decreasing applies */ /* Selects the Multiple Speed oscillator (MSI) clock range. */ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - 80029cc: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80029d0: 681b ldr r3, [r3, #0] - 80029d2: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 80029d6: f043 0308 orr.w r3, r3, #8 - 80029da: 6013 str r3, [r2, #0] - 80029dc: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80029e0: 681b ldr r3, [r3, #0] - 80029e2: f023 02f0 bic.w r2, r3, #240 ; 0xf0 - 80029e6: 687b ldr r3, [r7, #4] - 80029e8: 6a9b ldr r3, [r3, #40] ; 0x28 - 80029ea: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 80029ee: 4313 orrs r3, r2 - 80029f0: 600b str r3, [r1, #0] + 80027d8: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80027dc: 681b ldr r3, [r3, #0] + 80027de: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 80027e2: f043 0308 orr.w r3, r3, #8 + 80027e6: 6013 str r3, [r2, #0] + 80027e8: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80027ec: 681b ldr r3, [r3, #0] + 80027ee: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 80027f2: 687b ldr r3, [r7, #4] + 80027f4: 6a9b ldr r3, [r3, #40] ; 0x28 + 80027f6: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80027fa: 4313 orrs r3, r2 + 80027fc: 600b str r3, [r1, #0] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - 80029f2: 687b ldr r3, [r7, #4] - 80029f4: 6a5b ldr r3, [r3, #36] ; 0x24 - 80029f6: 4618 mov r0, r3 - 80029f8: f7ff fe3a bl 8002670 + 80027fe: 687b ldr r3, [r7, #4] + 8002800: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002802: 4618 mov r0, r3 + 8002804: f7ff fe3a bl 800247c /* Decrease number of wait states update if necessary */ if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) - 80029fc: 687b ldr r3, [r7, #4] - 80029fe: 6a9b ldr r3, [r3, #40] ; 0x28 - 8002a00: 4618 mov r0, r3 - 8002a02: f000 fd01 bl 8003408 - 8002a06: 4603 mov r3, r0 - 8002a08: 2b00 cmp r3, #0 - 8002a0a: d001 beq.n 8002a10 + 8002808: 687b ldr r3, [r7, #4] + 800280a: 6a9b ldr r3, [r3, #40] ; 0x28 + 800280c: 4618 mov r0, r3 + 800280e: f000 fd01 bl 8003214 + 8002812: 4603 mov r3, r0 + 8002814: 2b00 cmp r3, #0 + 8002816: d001 beq.n 800281c { return HAL_ERROR; - 8002a0c: 2301 movs r3, #1 - 8002a0e: e2f6 b.n 8002ffe + 8002818: 2301 movs r3, #1 + 800281a: e2f6 b.n 8002e0a } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetHCLKFreq(); - 8002a10: f000 fcc2 bl 8003398 - 8002a14: 4603 mov r3, r0 - 8002a16: 4aa7 ldr r2, [pc, #668] ; (8002cb4 ) - 8002a18: 6013 str r3, [r2, #0] + 800281c: f000 fcc2 bl 80031a4 + 8002820: 4603 mov r3, r0 + 8002822: 4aa7 ldr r2, [pc, #668] ; (8002ac0 ) + 8002824: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ status = HAL_InitTick(uwTickPrio); - 8002a1a: 4ba7 ldr r3, [pc, #668] ; (8002cb8 ) - 8002a1c: 681b ldr r3, [r3, #0] - 8002a1e: 4618 mov r0, r3 - 8002a20: f7fe fef0 bl 8001804 - 8002a24: 4603 mov r3, r0 - 8002a26: 74fb strb r3, [r7, #19] + 8002826: 4ba7 ldr r3, [pc, #668] ; (8002ac4 ) + 8002828: 681b ldr r3, [r3, #0] + 800282a: 4618 mov r0, r3 + 800282c: f7fe fef0 bl 8001610 + 8002830: 4603 mov r3, r0 + 8002832: 74fb strb r3, [r7, #19] if (status != HAL_OK) - 8002a28: 7cfb ldrb r3, [r7, #19] - 8002a2a: 2b00 cmp r3, #0 - 8002a2c: d047 beq.n 8002abe + 8002834: 7cfb ldrb r3, [r7, #19] + 8002836: 2b00 cmp r3, #0 + 8002838: d047 beq.n 80028ca { return status; - 8002a2e: 7cfb ldrb r3, [r7, #19] - 8002a30: e2e5 b.n 8002ffe + 800283a: 7cfb ldrb r3, [r7, #19] + 800283c: e2e5 b.n 8002e0a } } else { /* Check the MSI State */ if (RCC_OscInitStruct->MSIState != RCC_MSI_OFF) - 8002a32: 687b ldr r3, [r7, #4] - 8002a34: 6a1b ldr r3, [r3, #32] - 8002a36: 2b00 cmp r3, #0 - 8002a38: d02c beq.n 8002a94 + 800283e: 687b ldr r3, [r7, #4] + 8002840: 6a1b ldr r3, [r3, #32] + 8002842: 2b00 cmp r3, #0 + 8002844: d02c beq.n 80028a0 { /* Enable the Internal High Speed oscillator (MSI). */ __HAL_RCC_MSI_ENABLE(); - 8002a3a: f7ff fdc6 bl 80025ca + 8002846: f7ff fdc6 bl 80023d6 /* Get timeout */ tickstart = HAL_GetTick(); - 8002a3e: f7fe ff2d bl 800189c - 8002a42: 6178 str r0, [r7, #20] + 800284a: f7fe ff2d bl 80016a8 + 800284e: 6178 str r0, [r7, #20] /* Wait till MSI is ready */ while (LL_RCC_MSI_IsReady() == 0U) - 8002a44: e008 b.n 8002a58 + 8002850: e008 b.n 8002864 { if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - 8002a46: f7fe ff29 bl 800189c - 8002a4a: 4602 mov r2, r0 - 8002a4c: 697b ldr r3, [r7, #20] - 8002a4e: 1ad3 subs r3, r2, r3 - 8002a50: 2b02 cmp r3, #2 - 8002a52: d901 bls.n 8002a58 + 8002852: f7fe ff29 bl 80016a8 + 8002856: 4602 mov r2, r0 + 8002858: 697b ldr r3, [r7, #20] + 800285a: 1ad3 subs r3, r2, r3 + 800285c: 2b02 cmp r3, #2 + 800285e: d901 bls.n 8002864 { return HAL_TIMEOUT; - 8002a54: 2303 movs r3, #3 - 8002a56: e2d2 b.n 8002ffe + 8002860: 2303 movs r3, #3 + 8002862: e2d2 b.n 8002e0a while (LL_RCC_MSI_IsReady() == 0U) - 8002a58: f7ff fdd3 bl 8002602 - 8002a5c: 4603 mov r3, r0 - 8002a5e: 2b00 cmp r3, #0 - 8002a60: d0f1 beq.n 8002a46 + 8002864: f7ff fdd3 bl 800240e + 8002868: 4603 mov r3, r0 + 800286a: 2b00 cmp r3, #0 + 800286c: d0f1 beq.n 8002852 } } /* Selects the Multiple Speed oscillator (MSI) clock range. */ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - 8002a62: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002a66: 681b ldr r3, [r3, #0] - 8002a68: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 8002a6c: f043 0308 orr.w r3, r3, #8 - 8002a70: 6013 str r3, [r2, #0] - 8002a72: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002a76: 681b ldr r3, [r3, #0] - 8002a78: f023 02f0 bic.w r2, r3, #240 ; 0xf0 - 8002a7c: 687b ldr r3, [r7, #4] - 8002a7e: 6a9b ldr r3, [r3, #40] ; 0x28 - 8002a80: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 8002a84: 4313 orrs r3, r2 - 8002a86: 600b str r3, [r1, #0] + 800286e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002872: 681b ldr r3, [r3, #0] + 8002874: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8002878: f043 0308 orr.w r3, r3, #8 + 800287c: 6013 str r3, [r2, #0] + 800287e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002882: 681b ldr r3, [r3, #0] + 8002884: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 8002888: 687b ldr r3, [r7, #4] + 800288a: 6a9b ldr r3, [r3, #40] ; 0x28 + 800288c: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8002890: 4313 orrs r3, r2 + 8002892: 600b str r3, [r1, #0] /* Adjusts the Multiple Speed oscillator (MSI) calibration value. */ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - 8002a88: 687b ldr r3, [r7, #4] - 8002a8a: 6a5b ldr r3, [r3, #36] ; 0x24 - 8002a8c: 4618 mov r0, r3 - 8002a8e: f7ff fdef bl 8002670 - 8002a92: e015 b.n 8002ac0 + 8002894: 687b ldr r3, [r7, #4] + 8002896: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002898: 4618 mov r0, r3 + 800289a: f7ff fdef bl 800247c + 800289e: e015 b.n 80028cc } else { /* Disable the Internal High Speed oscillator (MSI). */ __HAL_RCC_MSI_DISABLE(); - 8002a94: f7ff fda7 bl 80025e6 + 80028a0: f7ff fda7 bl 80023f2 /* Get timeout */ tickstart = HAL_GetTick(); - 8002a98: f7fe ff00 bl 800189c - 8002a9c: 6178 str r0, [r7, #20] + 80028a4: f7fe ff00 bl 80016a8 + 80028a8: 6178 str r0, [r7, #20] /* Wait till MSI is disabled */ while (LL_RCC_MSI_IsReady() != 0U) - 8002a9e: e008 b.n 8002ab2 + 80028aa: e008 b.n 80028be { if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - 8002aa0: f7fe fefc bl 800189c - 8002aa4: 4602 mov r2, r0 - 8002aa6: 697b ldr r3, [r7, #20] - 8002aa8: 1ad3 subs r3, r2, r3 - 8002aaa: 2b02 cmp r3, #2 - 8002aac: d901 bls.n 8002ab2 + 80028ac: f7fe fefc bl 80016a8 + 80028b0: 4602 mov r2, r0 + 80028b2: 697b ldr r3, [r7, #20] + 80028b4: 1ad3 subs r3, r2, r3 + 80028b6: 2b02 cmp r3, #2 + 80028b8: d901 bls.n 80028be { return HAL_TIMEOUT; - 8002aae: 2303 movs r3, #3 - 8002ab0: e2a5 b.n 8002ffe + 80028ba: 2303 movs r3, #3 + 80028bc: e2a5 b.n 8002e0a while (LL_RCC_MSI_IsReady() != 0U) - 8002ab2: f7ff fda6 bl 8002602 - 8002ab6: 4603 mov r3, r0 - 8002ab8: 2b00 cmp r3, #0 - 8002aba: d1f1 bne.n 8002aa0 - 8002abc: e000 b.n 8002ac0 + 80028be: f7ff fda6 bl 800240e + 80028c2: 4603 mov r3, r0 + 80028c4: 2b00 cmp r3, #0 + 80028c6: d1f1 bne.n 80028ac + 80028c8: e000 b.n 80028cc if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) - 8002abe: bf00 nop + 80028ca: bf00 nop } } } /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - 8002ac0: 687b ldr r3, [r7, #4] - 8002ac2: 681b ldr r3, [r3, #0] - 8002ac4: f003 0301 and.w r3, r3, #1 - 8002ac8: 2b00 cmp r3, #0 - 8002aca: d058 beq.n 8002b7e + 80028cc: 687b ldr r3, [r7, #4] + 80028ce: 681b ldr r3, [r3, #0] + 80028d0: f003 0301 and.w r3, r3, #1 + 80028d4: 2b00 cmp r3, #0 + 80028d6: d058 beq.n 800298a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) || - 8002acc: 69fb ldr r3, [r7, #28] - 8002ace: 2b08 cmp r3, #8 - 8002ad0: d005 beq.n 8002ade - 8002ad2: 69fb ldr r3, [r7, #28] - 8002ad4: 2b0c cmp r3, #12 - 8002ad6: d108 bne.n 8002aea + 80028d8: 69fb ldr r3, [r7, #28] + 80028da: 2b08 cmp r3, #8 + 80028dc: d005 beq.n 80028ea + 80028de: 69fb ldr r3, [r7, #28] + 80028e0: 2b0c cmp r3, #12 + 80028e2: d108 bne.n 80028f6 ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) - 8002ad8: 69bb ldr r3, [r7, #24] - 8002ada: 2b03 cmp r3, #3 - 8002adc: d105 bne.n 8002aea + 80028e4: 69bb ldr r3, [r7, #24] + 80028e6: 2b03 cmp r3, #3 + 80028e8: d105 bne.n 80028f6 { if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) - 8002ade: 687b ldr r3, [r7, #4] - 8002ae0: 685b ldr r3, [r3, #4] - 8002ae2: 2b00 cmp r3, #0 - 8002ae4: d14b bne.n 8002b7e + 80028ea: 687b ldr r3, [r7, #4] + 80028ec: 685b ldr r3, [r3, #4] + 80028ee: 2b00 cmp r3, #0 + 80028f0: d14b bne.n 800298a { return HAL_ERROR; - 8002ae6: 2301 movs r3, #1 - 8002ae8: e289 b.n 8002ffe + 80028f2: 2301 movs r3, #1 + 80028f4: e289 b.n 8002e0a /* Set the new HSE configuration ---------------------------------------*/ /* Check HSE division factor */ assert_param(IS_RCC_HSEDIV(RCC_OscInitStruct->HSEDiv)); /* Set HSE division factor */ MODIFY_REG(RCC->CR, RCC_CR_HSEPRE, RCC_OscInitStruct->HSEDiv); - 8002aea: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002aee: 681b ldr r3, [r3, #0] - 8002af0: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 - 8002af4: 687b ldr r3, [r7, #4] - 8002af6: 689b ldr r3, [r3, #8] - 8002af8: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 8002afc: 4313 orrs r3, r2 - 8002afe: 600b str r3, [r1, #0] + 80028f6: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80028fa: 681b ldr r3, [r3, #0] + 80028fc: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 + 8002900: 687b ldr r3, [r7, #4] + 8002902: 689b ldr r3, [r3, #8] + 8002904: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8002908: 4313 orrs r3, r2 + 800290a: 600b str r3, [r1, #0] __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - 8002b00: 687b ldr r3, [r7, #4] - 8002b02: 685b ldr r3, [r3, #4] - 8002b04: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 - 8002b08: d102 bne.n 8002b10 - 8002b0a: f7ff fcae bl 800246a - 8002b0e: e00d b.n 8002b2c - 8002b10: 687b ldr r3, [r7, #4] - 8002b12: 685b ldr r3, [r3, #4] - 8002b14: f5b3 1f04 cmp.w r3, #2162688 ; 0x210000 - 8002b18: d104 bne.n 8002b24 - 8002b1a: f7ff fc79 bl 8002410 - 8002b1e: f7ff fca4 bl 800246a - 8002b22: e003 b.n 8002b2c - 8002b24: f7ff fcaf bl 8002486 - 8002b28: f7ff fc80 bl 800242c + 800290c: 687b ldr r3, [r7, #4] + 800290e: 685b ldr r3, [r3, #4] + 8002910: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8002914: d102 bne.n 800291c + 8002916: f7ff fcae bl 8002276 + 800291a: e00d b.n 8002938 + 800291c: 687b ldr r3, [r7, #4] + 800291e: 685b ldr r3, [r3, #4] + 8002920: f5b3 1f04 cmp.w r3, #2162688 ; 0x210000 + 8002924: d104 bne.n 8002930 + 8002926: f7ff fc79 bl 800221c + 800292a: f7ff fca4 bl 8002276 + 800292e: e003 b.n 8002938 + 8002930: f7ff fcaf bl 8002292 + 8002934: f7ff fc80 bl 8002238 /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - 8002b2c: 687b ldr r3, [r7, #4] - 8002b2e: 685b ldr r3, [r3, #4] - 8002b30: 2b00 cmp r3, #0 - 8002b32: d012 beq.n 8002b5a + 8002938: 687b ldr r3, [r7, #4] + 800293a: 685b ldr r3, [r3, #4] + 800293c: 2b00 cmp r3, #0 + 800293e: d012 beq.n 8002966 { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8002b34: f7fe feb2 bl 800189c - 8002b38: 6178 str r0, [r7, #20] + 8002940: f7fe feb2 bl 80016a8 + 8002944: 6178 str r0, [r7, #20] /* Wait till HSE is ready */ while (LL_RCC_HSE_IsReady() == 0U) - 8002b3a: e008 b.n 8002b4e + 8002946: e008 b.n 800295a { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - 8002b3c: f7fe feae bl 800189c - 8002b40: 4602 mov r2, r0 - 8002b42: 697b ldr r3, [r7, #20] - 8002b44: 1ad3 subs r3, r2, r3 - 8002b46: 2b64 cmp r3, #100 ; 0x64 - 8002b48: d901 bls.n 8002b4e + 8002948: f7fe feae bl 80016a8 + 800294c: 4602 mov r2, r0 + 800294e: 697b ldr r3, [r7, #20] + 8002950: 1ad3 subs r3, r2, r3 + 8002952: 2b64 cmp r3, #100 ; 0x64 + 8002954: d901 bls.n 800295a { return HAL_TIMEOUT; - 8002b4a: 2303 movs r3, #3 - 8002b4c: e257 b.n 8002ffe + 8002956: 2303 movs r3, #3 + 8002958: e257 b.n 8002e0a while (LL_RCC_HSE_IsReady() == 0U) - 8002b4e: f7ff fca8 bl 80024a2 - 8002b52: 4603 mov r3, r0 - 8002b54: 2b00 cmp r3, #0 - 8002b56: d0f1 beq.n 8002b3c - 8002b58: e011 b.n 8002b7e + 800295a: f7ff fca8 bl 80022ae + 800295e: 4603 mov r3, r0 + 8002960: 2b00 cmp r3, #0 + 8002962: d0f1 beq.n 8002948 + 8002964: e011 b.n 800298a } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8002b5a: f7fe fe9f bl 800189c - 8002b5e: 6178 str r0, [r7, #20] + 8002966: f7fe fe9f bl 80016a8 + 800296a: 6178 str r0, [r7, #20] /* Wait till HSE is disabled */ while (LL_RCC_HSE_IsReady() != 0U) - 8002b60: e008 b.n 8002b74 + 800296c: e008 b.n 8002980 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - 8002b62: f7fe fe9b bl 800189c - 8002b66: 4602 mov r2, r0 - 8002b68: 697b ldr r3, [r7, #20] - 8002b6a: 1ad3 subs r3, r2, r3 - 8002b6c: 2b64 cmp r3, #100 ; 0x64 - 8002b6e: d901 bls.n 8002b74 + 800296e: f7fe fe9b bl 80016a8 + 8002972: 4602 mov r2, r0 + 8002974: 697b ldr r3, [r7, #20] + 8002976: 1ad3 subs r3, r2, r3 + 8002978: 2b64 cmp r3, #100 ; 0x64 + 800297a: d901 bls.n 8002980 { return HAL_TIMEOUT; - 8002b70: 2303 movs r3, #3 - 8002b72: e244 b.n 8002ffe + 800297c: 2303 movs r3, #3 + 800297e: e244 b.n 8002e0a while (LL_RCC_HSE_IsReady() != 0U) - 8002b74: f7ff fc95 bl 80024a2 - 8002b78: 4603 mov r3, r0 - 8002b7a: 2b00 cmp r3, #0 - 8002b7c: d1f1 bne.n 8002b62 + 8002980: f7ff fc95 bl 80022ae + 8002984: 4603 mov r3, r0 + 8002986: 2b00 cmp r3, #0 + 8002988: d1f1 bne.n 800296e } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - 8002b7e: 687b ldr r3, [r7, #4] - 8002b80: 681b ldr r3, [r3, #0] - 8002b82: f003 0302 and.w r3, r3, #2 - 8002b86: 2b00 cmp r3, #0 - 8002b88: d046 beq.n 8002c18 + 800298a: 687b ldr r3, [r7, #4] + 800298c: 681b ldr r3, [r3, #0] + 800298e: f003 0302 and.w r3, r3, #2 + 8002992: 2b00 cmp r3, #0 + 8002994: d046 beq.n 8002a24 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) || - 8002b8a: 69fb ldr r3, [r7, #28] - 8002b8c: 2b04 cmp r3, #4 - 8002b8e: d005 beq.n 8002b9c - 8002b90: 69fb ldr r3, [r7, #28] - 8002b92: 2b0c cmp r3, #12 - 8002b94: d10e bne.n 8002bb4 + 8002996: 69fb ldr r3, [r7, #28] + 8002998: 2b04 cmp r3, #4 + 800299a: d005 beq.n 80029a8 + 800299c: 69fb ldr r3, [r7, #28] + 800299e: 2b0c cmp r3, #12 + 80029a0: d10e bne.n 80029c0 ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) - 8002b96: 69bb ldr r3, [r7, #24] - 8002b98: 2b02 cmp r3, #2 - 8002b9a: d10b bne.n 8002bb4 + 80029a2: 69bb ldr r3, [r7, #24] + 80029a4: 2b02 cmp r3, #2 + 80029a6: d10b bne.n 80029c0 { /* When HSI is used as system clock it will not be disabled */ if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) - 8002b9c: 687b ldr r3, [r7, #4] - 8002b9e: 691b ldr r3, [r3, #16] - 8002ba0: 2b00 cmp r3, #0 - 8002ba2: d101 bne.n 8002ba8 + 80029a8: 687b ldr r3, [r7, #4] + 80029aa: 691b ldr r3, [r3, #16] + 80029ac: 2b00 cmp r3, #0 + 80029ae: d101 bne.n 80029b4 { return HAL_ERROR; - 8002ba4: 2301 movs r3, #1 - 8002ba6: e22a b.n 8002ffe + 80029b0: 2301 movs r3, #1 + 80029b2: e22a b.n 8002e0a } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8002ba8: 687b ldr r3, [r7, #4] - 8002baa: 695b ldr r3, [r3, #20] - 8002bac: 4618 mov r0, r3 - 8002bae: f7ff fcb6 bl 800251e + 80029b4: 687b ldr r3, [r7, #4] + 80029b6: 695b ldr r3, [r3, #20] + 80029b8: 4618 mov r0, r3 + 80029ba: f7ff fcb6 bl 800232a if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) - 8002bb2: e031 b.n 8002c18 + 80029be: e031 b.n 8002a24 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) - 8002bb4: 687b ldr r3, [r7, #4] - 8002bb6: 691b ldr r3, [r3, #16] - 8002bb8: 2b00 cmp r3, #0 - 8002bba: d019 beq.n 8002bf0 + 80029c0: 687b ldr r3, [r7, #4] + 80029c2: 691b ldr r3, [r3, #16] + 80029c4: 2b00 cmp r3, #0 + 80029c6: d019 beq.n 80029fc { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); - 8002bbc: f7ff fc82 bl 80024c4 + 80029c8: f7ff fc82 bl 80022d0 /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8002bc0: f7fe fe6c bl 800189c - 8002bc4: 6178 str r0, [r7, #20] + 80029cc: f7fe fe6c bl 80016a8 + 80029d0: 6178 str r0, [r7, #20] /* Wait till HSI is ready */ while (LL_RCC_HSI_IsReady() == 0U) - 8002bc6: e008 b.n 8002bda + 80029d2: e008 b.n 80029e6 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - 8002bc8: f7fe fe68 bl 800189c - 8002bcc: 4602 mov r2, r0 - 8002bce: 697b ldr r3, [r7, #20] - 8002bd0: 1ad3 subs r3, r2, r3 - 8002bd2: 2b02 cmp r3, #2 - 8002bd4: d901 bls.n 8002bda + 80029d4: f7fe fe68 bl 80016a8 + 80029d8: 4602 mov r2, r0 + 80029da: 697b ldr r3, [r7, #20] + 80029dc: 1ad3 subs r3, r2, r3 + 80029de: 2b02 cmp r3, #2 + 80029e0: d901 bls.n 80029e6 { return HAL_TIMEOUT; - 8002bd6: 2303 movs r3, #3 - 8002bd8: e211 b.n 8002ffe + 80029e2: 2303 movs r3, #3 + 80029e4: e211 b.n 8002e0a while (LL_RCC_HSI_IsReady() == 0U) - 8002bda: f7ff fc8f bl 80024fc - 8002bde: 4603 mov r3, r0 - 8002be0: 2b00 cmp r3, #0 - 8002be2: d0f1 beq.n 8002bc8 + 80029e6: f7ff fc8f bl 8002308 + 80029ea: 4603 mov r3, r0 + 80029ec: 2b00 cmp r3, #0 + 80029ee: d0f1 beq.n 80029d4 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8002be4: 687b ldr r3, [r7, #4] - 8002be6: 695b ldr r3, [r3, #20] - 8002be8: 4618 mov r0, r3 - 8002bea: f7ff fc98 bl 800251e - 8002bee: e013 b.n 8002c18 + 80029f0: 687b ldr r3, [r7, #4] + 80029f2: 695b ldr r3, [r3, #20] + 80029f4: 4618 mov r0, r3 + 80029f6: f7ff fc98 bl 800232a + 80029fa: e013 b.n 8002a24 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); - 8002bf0: f7ff fc76 bl 80024e0 + 80029fc: f7ff fc76 bl 80022ec /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8002bf4: f7fe fe52 bl 800189c - 8002bf8: 6178 str r0, [r7, #20] + 8002a00: f7fe fe52 bl 80016a8 + 8002a04: 6178 str r0, [r7, #20] /* Wait till HSI is disabled */ while (LL_RCC_HSI_IsReady() != 0U) - 8002bfa: e008 b.n 8002c0e + 8002a06: e008 b.n 8002a1a { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - 8002bfc: f7fe fe4e bl 800189c - 8002c00: 4602 mov r2, r0 - 8002c02: 697b ldr r3, [r7, #20] - 8002c04: 1ad3 subs r3, r2, r3 - 8002c06: 2b02 cmp r3, #2 - 8002c08: d901 bls.n 8002c0e + 8002a08: f7fe fe4e bl 80016a8 + 8002a0c: 4602 mov r2, r0 + 8002a0e: 697b ldr r3, [r7, #20] + 8002a10: 1ad3 subs r3, r2, r3 + 8002a12: 2b02 cmp r3, #2 + 8002a14: d901 bls.n 8002a1a { return HAL_TIMEOUT; - 8002c0a: 2303 movs r3, #3 - 8002c0c: e1f7 b.n 8002ffe + 8002a16: 2303 movs r3, #3 + 8002a18: e1f7 b.n 8002e0a while (LL_RCC_HSI_IsReady() != 0U) - 8002c0e: f7ff fc75 bl 80024fc - 8002c12: 4603 mov r3, r0 - 8002c14: 2b00 cmp r3, #0 - 8002c16: d1f1 bne.n 8002bfc + 8002a1a: f7ff fc75 bl 8002308 + 8002a1e: 4603 mov r3, r0 + 8002a20: 2b00 cmp r3, #0 + 8002a22: d1f1 bne.n 8002a08 } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - 8002c18: 687b ldr r3, [r7, #4] - 8002c1a: 681b ldr r3, [r3, #0] - 8002c1c: f003 0308 and.w r3, r3, #8 - 8002c20: 2b00 cmp r3, #0 - 8002c22: d06e beq.n 8002d02 + 8002a24: 687b ldr r3, [r7, #4] + 8002a26: 681b ldr r3, [r3, #0] + 8002a28: f003 0308 and.w r3, r3, #8 + 8002a2c: 2b00 cmp r3, #0 + 8002a2e: d06e beq.n 8002b0e { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) - 8002c24: 687b ldr r3, [r7, #4] - 8002c26: 699b ldr r3, [r3, #24] - 8002c28: 2b00 cmp r3, #0 - 8002c2a: d056 beq.n 8002cda + 8002a30: 687b ldr r3, [r7, #4] + 8002a32: 699b ldr r3, [r3, #24] + 8002a34: 2b00 cmp r3, #0 + 8002a36: d056 beq.n 8002ae6 { uint32_t csr_temp = RCC->CSR; - 8002c2c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002c30: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 - 8002c34: 60fb str r3, [r7, #12] + 8002a38: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002a3c: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 8002a40: 60fb str r3, [r7, #12] /* Check LSI division factor */ assert_param(IS_RCC_LSIDIV(RCC_OscInitStruct->LSIDiv)); if (RCC_OscInitStruct->LSIDiv != (csr_temp & RCC_CSR_LSIPRE)) - 8002c36: 687b ldr r3, [r7, #4] - 8002c38: 69da ldr r2, [r3, #28] - 8002c3a: 68fb ldr r3, [r7, #12] - 8002c3c: f003 0310 and.w r3, r3, #16 - 8002c40: 429a cmp r2, r3 - 8002c42: d031 beq.n 8002ca8 + 8002a42: 687b ldr r3, [r7, #4] + 8002a44: 69da ldr r2, [r3, #28] + 8002a46: 68fb ldr r3, [r7, #12] + 8002a48: f003 0310 and.w r3, r3, #16 + 8002a4c: 429a cmp r2, r3 + 8002a4e: d031 beq.n 8002ab4 { if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \ - 8002c44: 68fb ldr r3, [r7, #12] - 8002c46: f003 0302 and.w r3, r3, #2 - 8002c4a: 2b00 cmp r3, #0 - 8002c4c: d006 beq.n 8002c5c + 8002a50: 68fb ldr r3, [r7, #12] + 8002a52: f003 0302 and.w r3, r3, #2 + 8002a56: 2b00 cmp r3, #0 + 8002a58: d006 beq.n 8002a68 ((csr_temp & RCC_CSR_LSION) != RCC_CSR_LSION)) - 8002c4e: 68fb ldr r3, [r7, #12] - 8002c50: f003 0301 and.w r3, r3, #1 + 8002a5a: 68fb ldr r3, [r7, #12] + 8002a5c: f003 0301 and.w r3, r3, #1 if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \ - 8002c54: 2b00 cmp r3, #0 - 8002c56: d101 bne.n 8002c5c + 8002a60: 2b00 cmp r3, #0 + 8002a62: d101 bne.n 8002a68 { /* If LSIRDY is set while LSION is not enabled, LSIPRE can't be updated */ return HAL_ERROR; - 8002c58: 2301 movs r3, #1 - 8002c5a: e1d0 b.n 8002ffe + 8002a64: 2301 movs r3, #1 + 8002a66: e1d0 b.n 8002e0a } /* Turn off LSI before changing RCC_CSR_LSIPRE */ if ((csr_temp & RCC_CSR_LSION) == RCC_CSR_LSION) - 8002c5c: 68fb ldr r3, [r7, #12] - 8002c5e: f003 0301 and.w r3, r3, #1 - 8002c62: 2b00 cmp r3, #0 - 8002c64: d013 beq.n 8002c8e + 8002a68: 68fb ldr r3, [r7, #12] + 8002a6a: f003 0301 and.w r3, r3, #1 + 8002a6e: 2b00 cmp r3, #0 + 8002a70: d013 beq.n 8002a9a { __HAL_RCC_LSI_DISABLE(); - 8002c66: f7ff fc8f bl 8002588 + 8002a72: f7ff fc8f bl 8002394 /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8002c6a: f7fe fe17 bl 800189c - 8002c6e: 6178 str r0, [r7, #20] + 8002a76: f7fe fe17 bl 80016a8 + 8002a7a: 6178 str r0, [r7, #20] /* Wait till LSI is disabled */ while (LL_RCC_LSI_IsReady() != 0U) - 8002c70: e008 b.n 8002c84 + 8002a7c: e008 b.n 8002a90 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - 8002c72: f7fe fe13 bl 800189c - 8002c76: 4602 mov r2, r0 - 8002c78: 697b ldr r3, [r7, #20] - 8002c7a: 1ad3 subs r3, r2, r3 - 8002c7c: 2b11 cmp r3, #17 - 8002c7e: d901 bls.n 8002c84 + 8002a7e: f7fe fe13 bl 80016a8 + 8002a82: 4602 mov r2, r0 + 8002a84: 697b ldr r3, [r7, #20] + 8002a86: 1ad3 subs r3, r2, r3 + 8002a88: 2b11 cmp r3, #17 + 8002a8a: d901 bls.n 8002a90 { return HAL_TIMEOUT; - 8002c80: 2303 movs r3, #3 - 8002c82: e1bc b.n 8002ffe + 8002a8c: 2303 movs r3, #3 + 8002a8e: e1bc b.n 8002e0a while (LL_RCC_LSI_IsReady() != 0U) - 8002c84: f7ff fc90 bl 80025a8 - 8002c88: 4603 mov r3, r0 - 8002c8a: 2b00 cmp r3, #0 - 8002c8c: d1f1 bne.n 8002c72 + 8002a90: f7ff fc90 bl 80023b4 + 8002a94: 4603 mov r3, r0 + 8002a96: 2b00 cmp r3, #0 + 8002a98: d1f1 bne.n 8002a7e } } } /* Set LSI division factor */ MODIFY_REG(RCC->CSR, RCC_CSR_LSIPRE, RCC_OscInitStruct->LSIDiv); - 8002c8e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002c92: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 - 8002c96: f023 0210 bic.w r2, r3, #16 - 8002c9a: 687b ldr r3, [r7, #4] - 8002c9c: 69db ldr r3, [r3, #28] - 8002c9e: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 8002ca2: 4313 orrs r3, r2 - 8002ca4: f8c1 3094 str.w r3, [r1, #148] ; 0x94 + 8002a9a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002a9e: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 8002aa2: f023 0210 bic.w r2, r3, #16 + 8002aa6: 687b ldr r3, [r7, #4] + 8002aa8: 69db ldr r3, [r3, #28] + 8002aaa: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8002aae: 4313 orrs r3, r2 + 8002ab0: f8c1 3094 str.w r3, [r1, #148] ; 0x94 } /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - 8002ca8: f7ff fc5e bl 8002568 + 8002ab4: f7ff fc5e bl 8002374 /* Get Start Tick */ tickstart = HAL_GetTick(); - 8002cac: f7fe fdf6 bl 800189c - 8002cb0: 6178 str r0, [r7, #20] + 8002ab8: f7fe fdf6 bl 80016a8 + 8002abc: 6178 str r0, [r7, #20] /* Wait till LSI is ready */ while (LL_RCC_LSI_IsReady() == 0U) - 8002cb2: e00c b.n 8002cce - 8002cb4: 20000008 .word 0x20000008 - 8002cb8: 2000000c .word 0x2000000c + 8002abe: e00c b.n 8002ada + 8002ac0: 20000000 .word 0x20000000 + 8002ac4: 20000004 .word 0x20000004 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - 8002cbc: f7fe fdee bl 800189c - 8002cc0: 4602 mov r2, r0 - 8002cc2: 697b ldr r3, [r7, #20] - 8002cc4: 1ad3 subs r3, r2, r3 - 8002cc6: 2b11 cmp r3, #17 - 8002cc8: d901 bls.n 8002cce + 8002ac8: f7fe fdee bl 80016a8 + 8002acc: 4602 mov r2, r0 + 8002ace: 697b ldr r3, [r7, #20] + 8002ad0: 1ad3 subs r3, r2, r3 + 8002ad2: 2b11 cmp r3, #17 + 8002ad4: d901 bls.n 8002ada { return HAL_TIMEOUT; - 8002cca: 2303 movs r3, #3 - 8002ccc: e197 b.n 8002ffe + 8002ad6: 2303 movs r3, #3 + 8002ad8: e197 b.n 8002e0a while (LL_RCC_LSI_IsReady() == 0U) - 8002cce: f7ff fc6b bl 80025a8 - 8002cd2: 4603 mov r3, r0 - 8002cd4: 2b00 cmp r3, #0 - 8002cd6: d0f1 beq.n 8002cbc - 8002cd8: e013 b.n 8002d02 + 8002ada: f7ff fc6b bl 80023b4 + 8002ade: 4603 mov r3, r0 + 8002ae0: 2b00 cmp r3, #0 + 8002ae2: d0f1 beq.n 8002ac8 + 8002ae4: e013 b.n 8002b0e } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - 8002cda: f7ff fc55 bl 8002588 + 8002ae6: f7ff fc55 bl 8002394 /* Get Start Tick */ tickstart = HAL_GetTick(); - 8002cde: f7fe fddd bl 800189c - 8002ce2: 6178 str r0, [r7, #20] + 8002aea: f7fe fddd bl 80016a8 + 8002aee: 6178 str r0, [r7, #20] /* Wait till LSI is disabled */ while (LL_RCC_LSI_IsReady() != 0U) - 8002ce4: e008 b.n 8002cf8 + 8002af0: e008 b.n 8002b04 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - 8002ce6: f7fe fdd9 bl 800189c - 8002cea: 4602 mov r2, r0 - 8002cec: 697b ldr r3, [r7, #20] - 8002cee: 1ad3 subs r3, r2, r3 - 8002cf0: 2b11 cmp r3, #17 - 8002cf2: d901 bls.n 8002cf8 + 8002af2: f7fe fdd9 bl 80016a8 + 8002af6: 4602 mov r2, r0 + 8002af8: 697b ldr r3, [r7, #20] + 8002afa: 1ad3 subs r3, r2, r3 + 8002afc: 2b11 cmp r3, #17 + 8002afe: d901 bls.n 8002b04 { return HAL_TIMEOUT; - 8002cf4: 2303 movs r3, #3 - 8002cf6: e182 b.n 8002ffe + 8002b00: 2303 movs r3, #3 + 8002b02: e182 b.n 8002e0a while (LL_RCC_LSI_IsReady() != 0U) - 8002cf8: f7ff fc56 bl 80025a8 - 8002cfc: 4603 mov r3, r0 - 8002cfe: 2b00 cmp r3, #0 - 8002d00: d1f1 bne.n 8002ce6 + 8002b04: f7ff fc56 bl 80023b4 + 8002b08: 4603 mov r3, r0 + 8002b0a: 2b00 cmp r3, #0 + 8002b0c: d1f1 bne.n 8002af2 } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - 8002d02: 687b ldr r3, [r7, #4] - 8002d04: 681b ldr r3, [r3, #0] - 8002d06: f003 0304 and.w r3, r3, #4 - 8002d0a: 2b00 cmp r3, #0 - 8002d0c: f000 80d8 beq.w 8002ec0 + 8002b0e: 687b ldr r3, [r7, #4] + 8002b10: 681b ldr r3, [r3, #0] + 8002b12: f003 0304 and.w r3, r3, #4 + 8002b16: 2b00 cmp r3, #0 + 8002b18: f000 80d8 beq.w 8002ccc assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (LL_PWR_IsEnabledBkUpAccess() == 0U) - 8002d10: f7ff fb6c bl 80023ec - 8002d14: 4603 mov r3, r0 - 8002d16: 2b00 cmp r3, #0 - 8002d18: d113 bne.n 8002d42 + 8002b1c: f7ff fb6c bl 80021f8 + 8002b20: 4603 mov r3, r0 + 8002b22: 2b00 cmp r3, #0 + 8002b24: d113 bne.n 8002b4e { /* Enable write access to Backup domain */ HAL_PWR_EnableBkUpAccess(); - 8002d1a: f7ff fb4d bl 80023b8 + 8002b26: f7ff fb4d bl 80021c4 /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - 8002d1e: f7fe fdbd bl 800189c - 8002d22: 6178 str r0, [r7, #20] + 8002b2a: f7fe fdbd bl 80016a8 + 8002b2e: 6178 str r0, [r7, #20] while (LL_PWR_IsEnabledBkUpAccess() == 0U) - 8002d24: e008 b.n 8002d38 + 8002b30: e008 b.n 8002b44 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 8002d26: f7fe fdb9 bl 800189c - 8002d2a: 4602 mov r2, r0 - 8002d2c: 697b ldr r3, [r7, #20] - 8002d2e: 1ad3 subs r3, r2, r3 - 8002d30: 2b02 cmp r3, #2 - 8002d32: d901 bls.n 8002d38 + 8002b32: f7fe fdb9 bl 80016a8 + 8002b36: 4602 mov r2, r0 + 8002b38: 697b ldr r3, [r7, #20] + 8002b3a: 1ad3 subs r3, r2, r3 + 8002b3c: 2b02 cmp r3, #2 + 8002b3e: d901 bls.n 8002b44 { return HAL_TIMEOUT; - 8002d34: 2303 movs r3, #3 - 8002d36: e162 b.n 8002ffe + 8002b40: 2303 movs r3, #3 + 8002b42: e162 b.n 8002e0a while (LL_PWR_IsEnabledBkUpAccess() == 0U) - 8002d38: f7ff fb58 bl 80023ec - 8002d3c: 4603 mov r3, r0 - 8002d3e: 2b00 cmp r3, #0 - 8002d40: d0f1 beq.n 8002d26 + 8002b44: f7ff fb58 bl 80021f8 + 8002b48: 4603 mov r3, r0 + 8002b4a: 2b00 cmp r3, #0 + 8002b4c: d0f1 beq.n 8002b32 } } } /* Set the new LSE configuration -----------------------------------------*/ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) - 8002d42: 687b ldr r3, [r7, #4] - 8002d44: 68db ldr r3, [r3, #12] - 8002d46: 2b00 cmp r3, #0 - 8002d48: d07b beq.n 8002e42 + 8002b4e: 687b ldr r3, [r7, #4] + 8002b50: 68db ldr r3, [r3, #12] + 8002b52: 2b00 cmp r3, #0 + 8002b54: d07b beq.n 8002c4e { /* Enable LSE bypasss (if requested) */ if ((RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS) - 8002d4a: 687b ldr r3, [r7, #4] - 8002d4c: 68db ldr r3, [r3, #12] - 8002d4e: 2b85 cmp r3, #133 ; 0x85 - 8002d50: d003 beq.n 8002d5a + 8002b56: 687b ldr r3, [r7, #4] + 8002b58: 68db ldr r3, [r3, #12] + 8002b5a: 2b85 cmp r3, #133 ; 0x85 + 8002b5c: d003 beq.n 8002b66 || (RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS_RTC_ONLY)) - 8002d52: 687b ldr r3, [r7, #4] - 8002d54: 68db ldr r3, [r3, #12] - 8002d56: 2b05 cmp r3, #5 - 8002d58: d109 bne.n 8002d6e + 8002b5e: 687b ldr r3, [r7, #4] + 8002b60: 68db ldr r3, [r3, #12] + 8002b62: 2b05 cmp r3, #5 + 8002b64: d109 bne.n 8002b7a { /* LSE oscillator bypass enable */ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); - 8002d5a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002d5e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002d62: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 8002d66: f043 0304 orr.w r3, r3, #4 - 8002d6a: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + 8002b66: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002b6a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002b6e: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8002b72: f043 0304 orr.w r3, r3, #4 + 8002b76: f8c2 3090 str.w r3, [r2, #144] ; 0x90 } /* Get Start Tick */ tickstart = HAL_GetTick(); - 8002d6e: f7fe fd95 bl 800189c - 8002d72: 6178 str r0, [r7, #20] + 8002b7a: f7fe fd95 bl 80016a8 + 8002b7e: 6178 str r0, [r7, #20] /* LSE oscillator enable */ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); - 8002d74: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002d78: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002d7c: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 8002d80: f043 0301 orr.w r3, r3, #1 - 8002d84: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + 8002b80: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002b84: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002b88: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8002b8c: f043 0301 orr.w r3, r3, #1 + 8002b90: f8c2 3090 str.w r3, [r2, #144] ; 0x90 /* Wait till LSE is ready */ while (LL_RCC_LSE_IsReady() == 0U) - 8002d88: e00a b.n 8002da0 + 8002b94: e00a b.n 8002bac { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8002d8a: f7fe fd87 bl 800189c - 8002d8e: 4602 mov r2, r0 - 8002d90: 697b ldr r3, [r7, #20] - 8002d92: 1ad3 subs r3, r2, r3 - 8002d94: f241 3288 movw r2, #5000 ; 0x1388 - 8002d98: 4293 cmp r3, r2 - 8002d9a: d901 bls.n 8002da0 + 8002b96: f7fe fd87 bl 80016a8 + 8002b9a: 4602 mov r2, r0 + 8002b9c: 697b ldr r3, [r7, #20] + 8002b9e: 1ad3 subs r3, r2, r3 + 8002ba0: f241 3288 movw r2, #5000 ; 0x1388 + 8002ba4: 4293 cmp r3, r2 + 8002ba6: d901 bls.n 8002bac { return HAL_TIMEOUT; - 8002d9c: 2303 movs r3, #3 - 8002d9e: e12e b.n 8002ffe + 8002ba8: 2303 movs r3, #3 + 8002baa: e12e b.n 8002e0a while (LL_RCC_LSE_IsReady() == 0U) - 8002da0: f7ff fbd1 bl 8002546 - 8002da4: 4603 mov r3, r0 - 8002da6: 2b00 cmp r3, #0 - 8002da8: d0ef beq.n 8002d8a + 8002bac: f7ff fbd1 bl 8002352 + 8002bb0: 4603 mov r3, r0 + 8002bb2: 2b00 cmp r3, #0 + 8002bb4: d0ef beq.n 8002b96 } } /* Enable LSE system clock (if requested) */ if ((RCC_OscInitStruct->LSEState == RCC_LSE_ON) - 8002daa: 687b ldr r3, [r7, #4] - 8002dac: 68db ldr r3, [r3, #12] - 8002dae: 2b81 cmp r3, #129 ; 0x81 - 8002db0: d003 beq.n 8002dba + 8002bb6: 687b ldr r3, [r7, #4] + 8002bb8: 68db ldr r3, [r3, #12] + 8002bba: 2b81 cmp r3, #129 ; 0x81 + 8002bbc: d003 beq.n 8002bc6 || (RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS)) - 8002db2: 687b ldr r3, [r7, #4] - 8002db4: 68db ldr r3, [r3, #12] - 8002db6: 2b85 cmp r3, #133 ; 0x85 - 8002db8: d121 bne.n 8002dfe + 8002bbe: 687b ldr r3, [r7, #4] + 8002bc0: 68db ldr r3, [r3, #12] + 8002bc2: 2b85 cmp r3, #133 ; 0x85 + 8002bc4: d121 bne.n 8002c0a { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8002dba: f7fe fd6f bl 800189c - 8002dbe: 6178 str r0, [r7, #20] + 8002bc6: f7fe fd6f bl 80016a8 + 8002bca: 6178 str r0, [r7, #20] SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); - 8002dc0: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002dc4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002dc8: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 8002dcc: f043 0380 orr.w r3, r3, #128 ; 0x80 - 8002dd0: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + 8002bcc: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002bd0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002bd4: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8002bd8: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8002bdc: f8c2 3090 str.w r3, [r2, #144] ; 0x90 /* Wait till LSESYS is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U) - 8002dd4: e00a b.n 8002dec + 8002be0: e00a b.n 8002bf8 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8002dd6: f7fe fd61 bl 800189c - 8002dda: 4602 mov r2, r0 - 8002ddc: 697b ldr r3, [r7, #20] - 8002dde: 1ad3 subs r3, r2, r3 - 8002de0: f241 3288 movw r2, #5000 ; 0x1388 - 8002de4: 4293 cmp r3, r2 - 8002de6: d901 bls.n 8002dec + 8002be2: f7fe fd61 bl 80016a8 + 8002be6: 4602 mov r2, r0 + 8002be8: 697b ldr r3, [r7, #20] + 8002bea: 1ad3 subs r3, r2, r3 + 8002bec: f241 3288 movw r2, #5000 ; 0x1388 + 8002bf0: 4293 cmp r3, r2 + 8002bf2: d901 bls.n 8002bf8 { return HAL_TIMEOUT; - 8002de8: 2303 movs r3, #3 - 8002dea: e108 b.n 8002ffe + 8002bf4: 2303 movs r3, #3 + 8002bf6: e108 b.n 8002e0a while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U) - 8002dec: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002df0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002df4: f403 6300 and.w r3, r3, #2048 ; 0x800 - 8002df8: 2b00 cmp r3, #0 - 8002dfa: d0ec beq.n 8002dd6 + 8002bf8: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002bfc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002c00: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8002c04: 2b00 cmp r3, #0 + 8002c06: d0ec beq.n 8002be2 if ((RCC_OscInitStruct->LSEState == RCC_LSE_ON) - 8002dfc: e060 b.n 8002ec0 + 8002c08: e060 b.n 8002ccc } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8002dfe: f7fe fd4d bl 800189c - 8002e02: 6178 str r0, [r7, #20] + 8002c0a: f7fe fd4d bl 80016a8 + 8002c0e: 6178 str r0, [r7, #20] CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); - 8002e04: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002e08: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002e0c: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 8002e10: f023 0380 bic.w r3, r3, #128 ; 0x80 - 8002e14: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + 8002c10: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002c14: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002c18: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8002c1c: f023 0380 bic.w r3, r3, #128 ; 0x80 + 8002c20: f8c2 3090 str.w r3, [r2, #144] ; 0x90 /* Wait till LSESYSRDY is cleared */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) - 8002e18: e00a b.n 8002e30 + 8002c24: e00a b.n 8002c3c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8002e1a: f7fe fd3f bl 800189c - 8002e1e: 4602 mov r2, r0 - 8002e20: 697b ldr r3, [r7, #20] - 8002e22: 1ad3 subs r3, r2, r3 - 8002e24: f241 3288 movw r2, #5000 ; 0x1388 - 8002e28: 4293 cmp r3, r2 - 8002e2a: d901 bls.n 8002e30 + 8002c26: f7fe fd3f bl 80016a8 + 8002c2a: 4602 mov r2, r0 + 8002c2c: 697b ldr r3, [r7, #20] + 8002c2e: 1ad3 subs r3, r2, r3 + 8002c30: f241 3288 movw r2, #5000 ; 0x1388 + 8002c34: 4293 cmp r3, r2 + 8002c36: d901 bls.n 8002c3c { return HAL_TIMEOUT; - 8002e2c: 2303 movs r3, #3 - 8002e2e: e0e6 b.n 8002ffe + 8002c38: 2303 movs r3, #3 + 8002c3a: e0e6 b.n 8002e0a while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) - 8002e30: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002e34: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002e38: f403 6300 and.w r3, r3, #2048 ; 0x800 - 8002e3c: 2b00 cmp r3, #0 - 8002e3e: d1ec bne.n 8002e1a - 8002e40: e03e b.n 8002ec0 + 8002c3c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002c40: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002c44: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8002c48: 2b00 cmp r3, #0 + 8002c4a: d1ec bne.n 8002c26 + 8002c4c: e03e b.n 8002ccc } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8002e42: f7fe fd2b bl 800189c - 8002e46: 6178 str r0, [r7, #20] + 8002c4e: f7fe fd2b bl 80016a8 + 8002c52: 6178 str r0, [r7, #20] CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); - 8002e48: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002e4c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002e50: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 8002e54: f023 0380 bic.w r3, r3, #128 ; 0x80 - 8002e58: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + 8002c54: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002c58: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002c5c: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8002c60: f023 0380 bic.w r3, r3, #128 ; 0x80 + 8002c64: f8c2 3090 str.w r3, [r2, #144] ; 0x90 /* Wait till LSESYSRDY is cleared */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) - 8002e5c: e00a b.n 8002e74 + 8002c68: e00a b.n 8002c80 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8002e5e: f7fe fd1d bl 800189c - 8002e62: 4602 mov r2, r0 - 8002e64: 697b ldr r3, [r7, #20] - 8002e66: 1ad3 subs r3, r2, r3 - 8002e68: f241 3288 movw r2, #5000 ; 0x1388 - 8002e6c: 4293 cmp r3, r2 - 8002e6e: d901 bls.n 8002e74 + 8002c6a: f7fe fd1d bl 80016a8 + 8002c6e: 4602 mov r2, r0 + 8002c70: 697b ldr r3, [r7, #20] + 8002c72: 1ad3 subs r3, r2, r3 + 8002c74: f241 3288 movw r2, #5000 ; 0x1388 + 8002c78: 4293 cmp r3, r2 + 8002c7a: d901 bls.n 8002c80 { return HAL_TIMEOUT; - 8002e70: 2303 movs r3, #3 - 8002e72: e0c4 b.n 8002ffe + 8002c7c: 2303 movs r3, #3 + 8002c7e: e0c4 b.n 8002e0a while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) - 8002e74: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002e78: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002e7c: f403 6300 and.w r3, r3, #2048 ; 0x800 - 8002e80: 2b00 cmp r3, #0 - 8002e82: d1ec bne.n 8002e5e + 8002c80: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002c84: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002c88: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8002c8c: 2b00 cmp r3, #0 + 8002c8e: d1ec bne.n 8002c6a } } /* Get Start Tick */ tickstart = HAL_GetTick(); - 8002e84: f7fe fd0a bl 800189c - 8002e88: 6178 str r0, [r7, #20] + 8002c90: f7fe fd0a bl 80016a8 + 8002c94: 6178 str r0, [r7, #20] /* LSE oscillator disable */ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); - 8002e8a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002e8e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002e92: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 8002e96: f023 0301 bic.w r3, r3, #1 - 8002e9a: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + 8002c96: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002c9a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002c9e: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8002ca2: f023 0301 bic.w r3, r3, #1 + 8002ca6: f8c2 3090 str.w r3, [r2, #144] ; 0x90 /* Wait till LSE is disabled */ while (LL_RCC_LSE_IsReady() != 0U) - 8002e9e: e00a b.n 8002eb6 + 8002caa: e00a b.n 8002cc2 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8002ea0: f7fe fcfc bl 800189c - 8002ea4: 4602 mov r2, r0 - 8002ea6: 697b ldr r3, [r7, #20] - 8002ea8: 1ad3 subs r3, r2, r3 - 8002eaa: f241 3288 movw r2, #5000 ; 0x1388 - 8002eae: 4293 cmp r3, r2 - 8002eb0: d901 bls.n 8002eb6 + 8002cac: f7fe fcfc bl 80016a8 + 8002cb0: 4602 mov r2, r0 + 8002cb2: 697b ldr r3, [r7, #20] + 8002cb4: 1ad3 subs r3, r2, r3 + 8002cb6: f241 3288 movw r2, #5000 ; 0x1388 + 8002cba: 4293 cmp r3, r2 + 8002cbc: d901 bls.n 8002cc2 { return HAL_TIMEOUT; - 8002eb2: 2303 movs r3, #3 - 8002eb4: e0a3 b.n 8002ffe + 8002cbe: 2303 movs r3, #3 + 8002cc0: e0a3 b.n 8002e0a while (LL_RCC_LSE_IsReady() != 0U) - 8002eb6: f7ff fb46 bl 8002546 - 8002eba: 4603 mov r3, r0 - 8002ebc: 2b00 cmp r3, #0 - 8002ebe: d1ef bne.n 8002ea0 + 8002cc2: f7ff fb46 bl 8002352 + 8002cc6: 4603 mov r3, r0 + 8002cc8: 2b00 cmp r3, #0 + 8002cca: d1ef bne.n 8002cac /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) - 8002ec0: 687b ldr r3, [r7, #4] - 8002ec2: 6adb ldr r3, [r3, #44] ; 0x2c - 8002ec4: 2b00 cmp r3, #0 - 8002ec6: f000 8099 beq.w 8002ffc + 8002ccc: 687b ldr r3, [r7, #4] + 8002cce: 6adb ldr r3, [r3, #44] ; 0x2c + 8002cd0: 2b00 cmp r3, #0 + 8002cd2: f000 8099 beq.w 8002e08 { /* Check if the PLL is used as system clock or not */ if (sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - 8002eca: 69fb ldr r3, [r7, #28] - 8002ecc: 2b0c cmp r3, #12 - 8002ece: d06c beq.n 8002faa + 8002cd6: 69fb ldr r3, [r7, #28] + 8002cd8: 2b0c cmp r3, #12 + 8002cda: d06c beq.n 8002db6 { if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) - 8002ed0: 687b ldr r3, [r7, #4] - 8002ed2: 6adb ldr r3, [r3, #44] ; 0x2c - 8002ed4: 2b02 cmp r3, #2 - 8002ed6: d14b bne.n 8002f70 + 8002cdc: 687b ldr r3, [r7, #4] + 8002cde: 6adb ldr r3, [r3, #44] ; 0x2c + 8002ce0: 2b02 cmp r3, #2 + 8002ce2: d14b bne.n 8002d7c assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 8002ed8: f7ff fc87 bl 80027ea + 8002ce4: f7ff fc87 bl 80025f6 /* Get Start Tick */ tickstart = HAL_GetTick(); - 8002edc: f7fe fcde bl 800189c - 8002ee0: 6178 str r0, [r7, #20] + 8002ce8: f7fe fcde bl 80016a8 + 8002cec: 6178 str r0, [r7, #20] /* Wait till PLL is ready */ while (LL_RCC_PLL_IsReady() != 0U) - 8002ee2: e008 b.n 8002ef6 + 8002cee: e008 b.n 8002d02 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 8002ee4: f7fe fcda bl 800189c - 8002ee8: 4602 mov r2, r0 - 8002eea: 697b ldr r3, [r7, #20] - 8002eec: 1ad3 subs r3, r2, r3 - 8002eee: 2b0a cmp r3, #10 - 8002ef0: d901 bls.n 8002ef6 + 8002cf0: f7fe fcda bl 80016a8 + 8002cf4: 4602 mov r2, r0 + 8002cf6: 697b ldr r3, [r7, #20] + 8002cf8: 1ad3 subs r3, r2, r3 + 8002cfa: 2b0a cmp r3, #10 + 8002cfc: d901 bls.n 8002d02 { return HAL_TIMEOUT; - 8002ef2: 2303 movs r3, #3 - 8002ef4: e083 b.n 8002ffe + 8002cfe: 2303 movs r3, #3 + 8002d00: e083 b.n 8002e0a while (LL_RCC_PLL_IsReady() != 0U) - 8002ef6: f7ff fc86 bl 8002806 - 8002efa: 4603 mov r3, r0 - 8002efc: 2b00 cmp r3, #0 - 8002efe: d1f1 bne.n 8002ee4 + 8002d02: f7ff fc86 bl 8002612 + 8002d06: 4603 mov r3, r0 + 8002d08: 2b00 cmp r3, #0 + 8002d0a: d1f1 bne.n 8002cf0 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - 8002f00: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002f04: 68da ldr r2, [r3, #12] - 8002f06: 4b40 ldr r3, [pc, #256] ; (8003008 ) - 8002f08: 4013 ands r3, r2 - 8002f0a: 687a ldr r2, [r7, #4] - 8002f0c: 6b11 ldr r1, [r2, #48] ; 0x30 - 8002f0e: 687a ldr r2, [r7, #4] - 8002f10: 6b52 ldr r2, [r2, #52] ; 0x34 - 8002f12: 4311 orrs r1, r2 - 8002f14: 687a ldr r2, [r7, #4] - 8002f16: 6b92 ldr r2, [r2, #56] ; 0x38 - 8002f18: 0212 lsls r2, r2, #8 - 8002f1a: 4311 orrs r1, r2 - 8002f1c: 687a ldr r2, [r7, #4] - 8002f1e: 6bd2 ldr r2, [r2, #60] ; 0x3c - 8002f20: 4311 orrs r1, r2 - 8002f22: 687a ldr r2, [r7, #4] - 8002f24: 6c12 ldr r2, [r2, #64] ; 0x40 - 8002f26: 4311 orrs r1, r2 - 8002f28: 687a ldr r2, [r7, #4] - 8002f2a: 6c52 ldr r2, [r2, #68] ; 0x44 - 8002f2c: 430a orrs r2, r1 - 8002f2e: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 8002f32: 4313 orrs r3, r2 - 8002f34: 60cb str r3, [r1, #12] + 8002d0c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002d10: 68da ldr r2, [r3, #12] + 8002d12: 4b40 ldr r3, [pc, #256] ; (8002e14 ) + 8002d14: 4013 ands r3, r2 + 8002d16: 687a ldr r2, [r7, #4] + 8002d18: 6b11 ldr r1, [r2, #48] ; 0x30 + 8002d1a: 687a ldr r2, [r7, #4] + 8002d1c: 6b52 ldr r2, [r2, #52] ; 0x34 + 8002d1e: 4311 orrs r1, r2 + 8002d20: 687a ldr r2, [r7, #4] + 8002d22: 6b92 ldr r2, [r2, #56] ; 0x38 + 8002d24: 0212 lsls r2, r2, #8 + 8002d26: 4311 orrs r1, r2 + 8002d28: 687a ldr r2, [r7, #4] + 8002d2a: 6bd2 ldr r2, [r2, #60] ; 0x3c + 8002d2c: 4311 orrs r1, r2 + 8002d2e: 687a ldr r2, [r7, #4] + 8002d30: 6c12 ldr r2, [r2, #64] ; 0x40 + 8002d32: 4311 orrs r1, r2 + 8002d34: 687a ldr r2, [r7, #4] + 8002d36: 6c52 ldr r2, [r2, #68] ; 0x44 + 8002d38: 430a orrs r2, r1 + 8002d3a: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8002d3e: 4313 orrs r3, r2 + 8002d40: 60cb str r3, [r1, #12] RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); - 8002f36: f7ff fc4a bl 80027ce + 8002d42: f7ff fc4a bl 80025da /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); - 8002f3a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002f3e: 68db ldr r3, [r3, #12] - 8002f40: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 8002f44: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 8002f48: 60d3 str r3, [r2, #12] + 8002d46: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002d4a: 68db ldr r3, [r3, #12] + 8002d4c: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8002d50: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8002d54: 60d3 str r3, [r2, #12] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8002f4a: f7fe fca7 bl 800189c - 8002f4e: 6178 str r0, [r7, #20] + 8002d56: f7fe fca7 bl 80016a8 + 8002d5a: 6178 str r0, [r7, #20] /* Wait till PLL is ready */ while (LL_RCC_PLL_IsReady() == 0U) - 8002f50: e008 b.n 8002f64 + 8002d5c: e008 b.n 8002d70 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 8002f52: f7fe fca3 bl 800189c - 8002f56: 4602 mov r2, r0 - 8002f58: 697b ldr r3, [r7, #20] - 8002f5a: 1ad3 subs r3, r2, r3 - 8002f5c: 2b0a cmp r3, #10 - 8002f5e: d901 bls.n 8002f64 + 8002d5e: f7fe fca3 bl 80016a8 + 8002d62: 4602 mov r2, r0 + 8002d64: 697b ldr r3, [r7, #20] + 8002d66: 1ad3 subs r3, r2, r3 + 8002d68: 2b0a cmp r3, #10 + 8002d6a: d901 bls.n 8002d70 { return HAL_TIMEOUT; - 8002f60: 2303 movs r3, #3 - 8002f62: e04c b.n 8002ffe + 8002d6c: 2303 movs r3, #3 + 8002d6e: e04c b.n 8002e0a while (LL_RCC_PLL_IsReady() == 0U) - 8002f64: f7ff fc4f bl 8002806 - 8002f68: 4603 mov r3, r0 - 8002f6a: 2b00 cmp r3, #0 - 8002f6c: d0f1 beq.n 8002f52 - 8002f6e: e045 b.n 8002ffc + 8002d70: f7ff fc4f bl 8002612 + 8002d74: 4603 mov r3, r0 + 8002d76: 2b00 cmp r3, #0 + 8002d78: d0f1 beq.n 8002d5e + 8002d7a: e045 b.n 8002e08 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 8002f70: f7ff fc3b bl 80027ea + 8002d7c: f7ff fc3b bl 80025f6 /* Get Start Tick */ tickstart = HAL_GetTick(); - 8002f74: f7fe fc92 bl 800189c - 8002f78: 6178 str r0, [r7, #20] + 8002d80: f7fe fc92 bl 80016a8 + 8002d84: 6178 str r0, [r7, #20] /* Wait till PLL is disabled */ while (LL_RCC_PLL_IsReady() != 0U) - 8002f7a: e008 b.n 8002f8e + 8002d86: e008 b.n 8002d9a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 8002f7c: f7fe fc8e bl 800189c - 8002f80: 4602 mov r2, r0 - 8002f82: 697b ldr r3, [r7, #20] - 8002f84: 1ad3 subs r3, r2, r3 - 8002f86: 2b0a cmp r3, #10 - 8002f88: d901 bls.n 8002f8e + 8002d88: f7fe fc8e bl 80016a8 + 8002d8c: 4602 mov r2, r0 + 8002d8e: 697b ldr r3, [r7, #20] + 8002d90: 1ad3 subs r3, r2, r3 + 8002d92: 2b0a cmp r3, #10 + 8002d94: d901 bls.n 8002d9a { return HAL_TIMEOUT; - 8002f8a: 2303 movs r3, #3 - 8002f8c: e037 b.n 8002ffe + 8002d96: 2303 movs r3, #3 + 8002d98: e037 b.n 8002e0a while (LL_RCC_PLL_IsReady() != 0U) - 8002f8e: f7ff fc3a bl 8002806 - 8002f92: 4603 mov r3, r0 - 8002f94: 2b00 cmp r3, #0 - 8002f96: d1f1 bne.n 8002f7c + 8002d9a: f7ff fc3a bl 8002612 + 8002d9e: 4603 mov r3, r0 + 8002da0: 2b00 cmp r3, #0 + 8002da2: d1f1 bne.n 8002d88 } } /* Disable the PLL source and outputs to save power when PLL is off */ CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN)); - 8002f98: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002f9c: 68da ldr r2, [r3, #12] - 8002f9e: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 8002fa2: 4b1a ldr r3, [pc, #104] ; (800300c ) - 8002fa4: 4013 ands r3, r2 - 8002fa6: 60cb str r3, [r1, #12] - 8002fa8: e028 b.n 8002ffc + 8002da4: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002da8: 68da ldr r2, [r3, #12] + 8002daa: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8002dae: 4b1a ldr r3, [pc, #104] ; (8002e18 ) + 8002db0: 4013 ands r3, r2 + 8002db2: 60cb str r3, [r1, #12] + 8002db4: e028 b.n 8002e08 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) - 8002faa: 687b ldr r3, [r7, #4] - 8002fac: 6adb ldr r3, [r3, #44] ; 0x2c - 8002fae: 2b01 cmp r3, #1 - 8002fb0: d101 bne.n 8002fb6 + 8002db6: 687b ldr r3, [r7, #4] + 8002db8: 6adb ldr r3, [r3, #44] ; 0x2c + 8002dba: 2b01 cmp r3, #1 + 8002dbc: d101 bne.n 8002dc2 { return HAL_ERROR; - 8002fb2: 2301 movs r3, #1 - 8002fb4: e023 b.n 8002ffe + 8002dbe: 2301 movs r3, #1 + 8002dc0: e023 b.n 8002e0a } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; - 8002fb6: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8002fba: 68db ldr r3, [r3, #12] - 8002fbc: 61bb str r3, [r7, #24] + 8002dc2: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002dc6: 68db ldr r3, [r3, #12] + 8002dc8: 61bb str r3, [r7, #24] if ((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) - 8002fbe: 69bb ldr r3, [r7, #24] - 8002fc0: f003 0203 and.w r2, r3, #3 - 8002fc4: 687b ldr r3, [r7, #4] - 8002fc6: 6b1b ldr r3, [r3, #48] ; 0x30 - 8002fc8: 429a cmp r2, r3 - 8002fca: d115 bne.n 8002ff8 + 8002dca: 69bb ldr r3, [r7, #24] + 8002dcc: f003 0203 and.w r2, r3, #3 + 8002dd0: 687b ldr r3, [r7, #4] + 8002dd2: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002dd4: 429a cmp r2, r3 + 8002dd6: d115 bne.n 8002e04 || (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) - 8002fcc: 69bb ldr r3, [r7, #24] - 8002fce: f003 0270 and.w r2, r3, #112 ; 0x70 - 8002fd2: 687b ldr r3, [r7, #4] - 8002fd4: 6b5b ldr r3, [r3, #52] ; 0x34 - 8002fd6: 429a cmp r2, r3 - 8002fd8: d10e bne.n 8002ff8 + 8002dd8: 69bb ldr r3, [r7, #24] + 8002dda: f003 0270 and.w r2, r3, #112 ; 0x70 + 8002dde: 687b ldr r3, [r7, #4] + 8002de0: 6b5b ldr r3, [r3, #52] ; 0x34 + 8002de2: 429a cmp r2, r3 + 8002de4: d10e bne.n 8002e04 || (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) - 8002fda: 69bb ldr r3, [r7, #24] - 8002fdc: f403 42fe and.w r2, r3, #32512 ; 0x7f00 - 8002fe0: 687b ldr r3, [r7, #4] - 8002fe2: 6b9b ldr r3, [r3, #56] ; 0x38 - 8002fe4: 021b lsls r3, r3, #8 - 8002fe6: 429a cmp r2, r3 - 8002fe8: d106 bne.n 8002ff8 + 8002de6: 69bb ldr r3, [r7, #24] + 8002de8: f403 42fe and.w r2, r3, #32512 ; 0x7f00 + 8002dec: 687b ldr r3, [r7, #4] + 8002dee: 6b9b ldr r3, [r3, #56] ; 0x38 + 8002df0: 021b lsls r3, r3, #8 + 8002df2: 429a cmp r2, r3 + 8002df4: d106 bne.n 8002e04 || (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) - 8002fea: 69bb ldr r3, [r7, #24] - 8002fec: f003 4260 and.w r2, r3, #3758096384 ; 0xe0000000 - 8002ff0: 687b ldr r3, [r7, #4] - 8002ff2: 6c5b ldr r3, [r3, #68] ; 0x44 - 8002ff4: 429a cmp r2, r3 - 8002ff6: d001 beq.n 8002ffc + 8002df6: 69bb ldr r3, [r7, #24] + 8002df8: f003 4260 and.w r2, r3, #3758096384 ; 0xe0000000 + 8002dfc: 687b ldr r3, [r7, #4] + 8002dfe: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002e00: 429a cmp r2, r3 + 8002e02: d001 beq.n 8002e08 { return HAL_ERROR; - 8002ff8: 2301 movs r3, #1 - 8002ffa: e000 b.n 8002ffe + 8002e04: 2301 movs r3, #1 + 8002e06: e000 b.n 8002e0a } } } } return HAL_OK; - 8002ffc: 2300 movs r3, #0 + 8002e08: 2300 movs r3, #0 } - 8002ffe: 4618 mov r0, r3 - 8003000: 3720 adds r7, #32 - 8003002: 46bd mov sp, r7 - 8003004: bd80 pop {r7, pc} - 8003006: bf00 nop - 8003008: 11c1808c .word 0x11c1808c - 800300c: eefefffc .word 0xeefefffc + 8002e0a: 4618 mov r0, r3 + 8002e0c: 3720 adds r7, #32 + 8002e0e: 46bd mov sp, r7 + 8002e10: bd80 pop {r7, pc} + 8002e12: bf00 nop + 8002e14: 11c1808c .word 0x11c1808c + 8002e18: eefefffc .word 0xeefefffc -08003010 : +08002e1c : * HPRE[3:0] bits to ensure that HCLK1 not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - 8003010: b580 push {r7, lr} - 8003012: b084 sub sp, #16 - 8003014: af00 add r7, sp, #0 - 8003016: 6078 str r0, [r7, #4] - 8003018: 6039 str r1, [r7, #0] + 8002e1c: b580 push {r7, lr} + 8002e1e: b084 sub sp, #16 + 8002e20: af00 add r7, sp, #0 + 8002e22: 6078 str r0, [r7, #4] + 8002e24: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) - 800301a: 687b ldr r3, [r7, #4] - 800301c: 2b00 cmp r3, #0 - 800301e: d101 bne.n 8003024 + 8002e26: 687b ldr r3, [r7, #4] + 8002e28: 2b00 cmp r3, #0 + 8002e2a: d101 bne.n 8002e30 { return HAL_ERROR; - 8003020: 2301 movs r3, #1 - 8003022: e10f b.n 8003244 + 8002e2c: 2301 movs r3, #1 + 8002e2e: e10f b.n 8003050 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the FLASH clock (HCLK3) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) - 8003024: 4b89 ldr r3, [pc, #548] ; (800324c ) - 8003026: 681b ldr r3, [r3, #0] - 8003028: f003 0307 and.w r3, r3, #7 - 800302c: 683a ldr r2, [r7, #0] - 800302e: 429a cmp r2, r3 - 8003030: d91b bls.n 800306a + 8002e30: 4b89 ldr r3, [pc, #548] ; (8003058 ) + 8002e32: 681b ldr r3, [r3, #0] + 8002e34: f003 0307 and.w r3, r3, #7 + 8002e38: 683a ldr r2, [r7, #0] + 8002e3a: 429a cmp r2, r3 + 8002e3c: d91b bls.n 8002e76 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 8003032: 4b86 ldr r3, [pc, #536] ; (800324c ) - 8003034: 681b ldr r3, [r3, #0] - 8003036: f023 0207 bic.w r2, r3, #7 - 800303a: 4984 ldr r1, [pc, #528] ; (800324c ) - 800303c: 683b ldr r3, [r7, #0] - 800303e: 4313 orrs r3, r2 - 8003040: 600b str r3, [r1, #0] + 8002e3e: 4b86 ldr r3, [pc, #536] ; (8003058 ) + 8002e40: 681b ldr r3, [r3, #0] + 8002e42: f023 0207 bic.w r2, r3, #7 + 8002e46: 4984 ldr r1, [pc, #528] ; (8003058 ) + 8002e48: 683b ldr r3, [r7, #0] + 8002e4a: 4313 orrs r3, r2 + 8002e4c: 600b str r3, [r1, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8003042: f7fe fc2b bl 800189c - 8003046: 60f8 str r0, [r7, #12] + 8002e4e: f7fe fc2b bl 80016a8 + 8002e52: 60f8 str r0, [r7, #12] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ while (__HAL_FLASH_GET_LATENCY() != FLatency) - 8003048: e008 b.n 800305c + 8002e54: e008 b.n 8002e68 { if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) - 800304a: f7fe fc27 bl 800189c - 800304e: 4602 mov r2, r0 - 8003050: 68fb ldr r3, [r7, #12] - 8003052: 1ad3 subs r3, r2, r3 - 8003054: 2b02 cmp r3, #2 - 8003056: d901 bls.n 800305c + 8002e56: f7fe fc27 bl 80016a8 + 8002e5a: 4602 mov r2, r0 + 8002e5c: 68fb ldr r3, [r7, #12] + 8002e5e: 1ad3 subs r3, r2, r3 + 8002e60: 2b02 cmp r3, #2 + 8002e62: d901 bls.n 8002e68 { return HAL_TIMEOUT; - 8003058: 2303 movs r3, #3 - 800305a: e0f3 b.n 8003244 + 8002e64: 2303 movs r3, #3 + 8002e66: e0f3 b.n 8003050 while (__HAL_FLASH_GET_LATENCY() != FLatency) - 800305c: 4b7b ldr r3, [pc, #492] ; (800324c ) - 800305e: 681b ldr r3, [r3, #0] - 8003060: f003 0307 and.w r3, r3, #7 - 8003064: 683a ldr r2, [r7, #0] - 8003066: 429a cmp r2, r3 - 8003068: d1ef bne.n 800304a + 8002e68: 4b7b ldr r3, [pc, #492] ; (8003058 ) + 8002e6a: 681b ldr r3, [r3, #0] + 8002e6c: f003 0307 and.w r3, r3, #7 + 8002e70: 683a ldr r2, [r7, #0] + 8002e72: 429a cmp r2, r3 + 8002e74: d1ef bne.n 8002e56 } } } /*-------------------------- HCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - 800306a: 687b ldr r3, [r7, #4] - 800306c: 681b ldr r3, [r3, #0] - 800306e: f003 0302 and.w r3, r3, #2 - 8003072: 2b00 cmp r3, #0 - 8003074: d016 beq.n 80030a4 + 8002e76: 687b ldr r3, [r7, #4] + 8002e78: 681b ldr r3, [r3, #0] + 8002e7a: f003 0302 and.w r3, r3, #2 + 8002e7e: 2b00 cmp r3, #0 + 8002e80: d016 beq.n 8002eb0 { assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLKDivider)); LL_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLKDivider); - 8003076: 687b ldr r3, [r7, #4] - 8003078: 689b ldr r3, [r3, #8] - 800307a: 4618 mov r0, r3 - 800307c: f7ff fb2a bl 80026d4 + 8002e82: 687b ldr r3, [r7, #4] + 8002e84: 689b ldr r3, [r3, #8] + 8002e86: 4618 mov r0, r3 + 8002e88: f7ff fb2a bl 80024e0 /* HCLK1 prescaler flag when value applied */ tickstart = HAL_GetTick(); - 8003080: f7fe fc0c bl 800189c - 8003084: 60f8 str r0, [r7, #12] + 8002e8c: f7fe fc0c bl 80016a8 + 8002e90: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_HPRE() == 0U) - 8003086: e008 b.n 800309a + 8002e92: e008 b.n 8002ea6 { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) - 8003088: f7fe fc08 bl 800189c - 800308c: 4602 mov r2, r0 - 800308e: 68fb ldr r3, [r7, #12] - 8003090: 1ad3 subs r3, r2, r3 - 8003092: 2b02 cmp r3, #2 - 8003094: d901 bls.n 800309a + 8002e94: f7fe fc08 bl 80016a8 + 8002e98: 4602 mov r2, r0 + 8002e9a: 68fb ldr r3, [r7, #12] + 8002e9c: 1ad3 subs r3, r2, r3 + 8002e9e: 2b02 cmp r3, #2 + 8002ea0: d901 bls.n 8002ea6 { return HAL_TIMEOUT; - 8003096: 2303 movs r3, #3 - 8003098: e0d4 b.n 8003244 + 8002ea2: 2303 movs r3, #3 + 8002ea4: e0d4 b.n 8003050 while (LL_RCC_IsActiveFlag_HPRE() == 0U) - 800309a: f7ff fbf2 bl 8002882 - 800309e: 4603 mov r3, r0 - 80030a0: 2b00 cmp r3, #0 - 80030a2: d0f1 beq.n 8003088 + 8002ea6: f7ff fbf2 bl 800268e + 8002eaa: 4603 mov r3, r0 + 8002eac: 2b00 cmp r3, #0 + 8002eae: d0f1 beq.n 8002e94 } } #endif /* DUAL_CORE */ /*-------------------------- HCLK3 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK3) == RCC_CLOCKTYPE_HCLK3) - 80030a4: 687b ldr r3, [r7, #4] - 80030a6: 681b ldr r3, [r3, #0] - 80030a8: f003 0340 and.w r3, r3, #64 ; 0x40 - 80030ac: 2b00 cmp r3, #0 - 80030ae: d016 beq.n 80030de + 8002eb0: 687b ldr r3, [r7, #4] + 8002eb2: 681b ldr r3, [r3, #0] + 8002eb4: f003 0340 and.w r3, r3, #64 ; 0x40 + 8002eb8: 2b00 cmp r3, #0 + 8002eba: d016 beq.n 8002eea { assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK3Divider)); LL_RCC_SetAHB3Prescaler(RCC_ClkInitStruct->AHBCLK3Divider); - 80030b0: 687b ldr r3, [r7, #4] - 80030b2: 695b ldr r3, [r3, #20] - 80030b4: 4618 mov r0, r3 - 80030b6: f7ff fb20 bl 80026fa + 8002ebc: 687b ldr r3, [r7, #4] + 8002ebe: 695b ldr r3, [r3, #20] + 8002ec0: 4618 mov r0, r3 + 8002ec2: f7ff fb20 bl 8002506 /* AHB shared prescaler flag when value applied */ tickstart = HAL_GetTick(); - 80030ba: f7fe fbef bl 800189c - 80030be: 60f8 str r0, [r7, #12] + 8002ec6: f7fe fbef bl 80016a8 + 8002eca: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) - 80030c0: e008 b.n 80030d4 + 8002ecc: e008 b.n 8002ee0 { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) - 80030c2: f7fe fbeb bl 800189c - 80030c6: 4602 mov r2, r0 - 80030c8: 68fb ldr r3, [r7, #12] - 80030ca: 1ad3 subs r3, r2, r3 - 80030cc: 2b02 cmp r3, #2 - 80030ce: d901 bls.n 80030d4 + 8002ece: f7fe fbeb bl 80016a8 + 8002ed2: 4602 mov r2, r0 + 8002ed4: 68fb ldr r3, [r7, #12] + 8002ed6: 1ad3 subs r3, r2, r3 + 8002ed8: 2b02 cmp r3, #2 + 8002eda: d901 bls.n 8002ee0 { return HAL_TIMEOUT; - 80030d0: 2303 movs r3, #3 - 80030d2: e0b7 b.n 8003244 + 8002edc: 2303 movs r3, #3 + 8002ede: e0b7 b.n 8003050 while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) - 80030d4: f7ff fbe6 bl 80028a4 - 80030d8: 4603 mov r3, r0 - 80030da: 2b00 cmp r3, #0 - 80030dc: d0f1 beq.n 80030c2 + 8002ee0: f7ff fbe6 bl 80026b0 + 8002ee4: 4603 mov r3, r0 + 8002ee6: 2b00 cmp r3, #0 + 8002ee8: d0f1 beq.n 8002ece } } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 80030de: 687b ldr r3, [r7, #4] - 80030e0: 681b ldr r3, [r3, #0] - 80030e2: f003 0304 and.w r3, r3, #4 - 80030e6: 2b00 cmp r3, #0 - 80030e8: d016 beq.n 8003118 + 8002eea: 687b ldr r3, [r7, #4] + 8002eec: 681b ldr r3, [r3, #0] + 8002eee: f003 0304 and.w r3, r3, #4 + 8002ef2: 2b00 cmp r3, #0 + 8002ef4: d016 beq.n 8002f24 { assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB1CLKDivider)); LL_RCC_SetAPB1Prescaler(RCC_ClkInitStruct->APB1CLKDivider); - 80030ea: 687b ldr r3, [r7, #4] - 80030ec: 68db ldr r3, [r3, #12] - 80030ee: 4618 mov r0, r3 - 80030f0: f7ff fb19 bl 8002726 + 8002ef6: 687b ldr r3, [r7, #4] + 8002ef8: 68db ldr r3, [r3, #12] + 8002efa: 4618 mov r0, r3 + 8002efc: f7ff fb19 bl 8002532 /* APB1 prescaler flag when value applied */ tickstart = HAL_GetTick(); - 80030f4: f7fe fbd2 bl 800189c - 80030f8: 60f8 str r0, [r7, #12] + 8002f00: f7fe fbd2 bl 80016a8 + 8002f04: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_PPRE1() == 0U) - 80030fa: e008 b.n 800310e + 8002f06: e008 b.n 8002f1a { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) - 80030fc: f7fe fbce bl 800189c - 8003100: 4602 mov r2, r0 - 8003102: 68fb ldr r3, [r7, #12] - 8003104: 1ad3 subs r3, r2, r3 - 8003106: 2b02 cmp r3, #2 - 8003108: d901 bls.n 800310e + 8002f08: f7fe fbce bl 80016a8 + 8002f0c: 4602 mov r2, r0 + 8002f0e: 68fb ldr r3, [r7, #12] + 8002f10: 1ad3 subs r3, r2, r3 + 8002f12: 2b02 cmp r3, #2 + 8002f14: d901 bls.n 8002f1a { return HAL_TIMEOUT; - 800310a: 2303 movs r3, #3 - 800310c: e09a b.n 8003244 + 8002f16: 2303 movs r3, #3 + 8002f18: e09a b.n 8003050 while (LL_RCC_IsActiveFlag_PPRE1() == 0U) - 800310e: f7ff fbdb bl 80028c8 - 8003112: 4603 mov r3, r0 - 8003114: 2b00 cmp r3, #0 - 8003116: d0f1 beq.n 80030fc + 8002f1a: f7ff fbdb bl 80026d4 + 8002f1e: 4603 mov r3, r0 + 8002f20: 2b00 cmp r3, #0 + 8002f22: d0f1 beq.n 8002f08 } } } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 8003118: 687b ldr r3, [r7, #4] - 800311a: 681b ldr r3, [r3, #0] - 800311c: f003 0308 and.w r3, r3, #8 - 8003120: 2b00 cmp r3, #0 - 8003122: d017 beq.n 8003154 + 8002f24: 687b ldr r3, [r7, #4] + 8002f26: 681b ldr r3, [r3, #0] + 8002f28: f003 0308 and.w r3, r3, #8 + 8002f2c: 2b00 cmp r3, #0 + 8002f2e: d017 beq.n 8002f60 { assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB2CLKDivider)); LL_RCC_SetAPB2Prescaler((RCC_ClkInitStruct->APB2CLKDivider) << 3U); - 8003124: 687b ldr r3, [r7, #4] - 8003126: 691b ldr r3, [r3, #16] - 8003128: 00db lsls r3, r3, #3 - 800312a: 4618 mov r0, r3 - 800312c: f7ff fb0e bl 800274c + 8002f30: 687b ldr r3, [r7, #4] + 8002f32: 691b ldr r3, [r3, #16] + 8002f34: 00db lsls r3, r3, #3 + 8002f36: 4618 mov r0, r3 + 8002f38: f7ff fb0e bl 8002558 /* APB2 prescaler flag when value applied */ tickstart = HAL_GetTick(); - 8003130: f7fe fbb4 bl 800189c - 8003134: 60f8 str r0, [r7, #12] + 8002f3c: f7fe fbb4 bl 80016a8 + 8002f40: 60f8 str r0, [r7, #12] while (LL_RCC_IsActiveFlag_PPRE2() == 0U) - 8003136: e008 b.n 800314a + 8002f42: e008 b.n 8002f56 { if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) - 8003138: f7fe fbb0 bl 800189c - 800313c: 4602 mov r2, r0 - 800313e: 68fb ldr r3, [r7, #12] - 8003140: 1ad3 subs r3, r2, r3 - 8003142: 2b02 cmp r3, #2 - 8003144: d901 bls.n 800314a + 8002f44: f7fe fbb0 bl 80016a8 + 8002f48: 4602 mov r2, r0 + 8002f4a: 68fb ldr r3, [r7, #12] + 8002f4c: 1ad3 subs r3, r2, r3 + 8002f4e: 2b02 cmp r3, #2 + 8002f50: d901 bls.n 8002f56 { return HAL_TIMEOUT; - 8003146: 2303 movs r3, #3 - 8003148: e07c b.n 8003244 + 8002f52: 2303 movs r3, #3 + 8002f54: e07c b.n 8003050 while (LL_RCC_IsActiveFlag_PPRE2() == 0U) - 800314a: f7ff fbce bl 80028ea - 800314e: 4603 mov r3, r0 - 8003150: 2b00 cmp r3, #0 - 8003152: d0f1 beq.n 8003138 + 8002f56: f7ff fbce bl 80026f6 + 8002f5a: 4603 mov r3, r0 + 8002f5c: 2b00 cmp r3, #0 + 8002f5e: d0f1 beq.n 8002f44 } } } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - 8003154: 687b ldr r3, [r7, #4] - 8003156: 681b ldr r3, [r3, #0] - 8003158: f003 0301 and.w r3, r3, #1 - 800315c: 2b00 cmp r3, #0 - 800315e: d043 beq.n 80031e8 + 8002f60: 687b ldr r3, [r7, #4] + 8002f62: 681b ldr r3, [r3, #0] + 8002f64: f003 0301 and.w r3, r3, #1 + 8002f68: 2b00 cmp r3, #0 + 8002f6a: d043 beq.n 8002ff4 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - 8003160: 687b ldr r3, [r7, #4] - 8003162: 685b ldr r3, [r3, #4] - 8003164: 2b02 cmp r3, #2 - 8003166: d106 bne.n 8003176 + 8002f6c: 687b ldr r3, [r7, #4] + 8002f6e: 685b ldr r3, [r3, #4] + 8002f70: 2b02 cmp r3, #2 + 8002f72: d106 bne.n 8002f82 { /* Check the HSE ready flag */ if (LL_RCC_HSE_IsReady() == 0U) - 8003168: f7ff f99b bl 80024a2 - 800316c: 4603 mov r3, r0 - 800316e: 2b00 cmp r3, #0 - 8003170: d11e bne.n 80031b0 + 8002f74: f7ff f99b bl 80022ae + 8002f78: 4603 mov r3, r0 + 8002f7a: 2b00 cmp r3, #0 + 8002f7c: d11e bne.n 8002fbc { return HAL_ERROR; - 8003172: 2301 movs r3, #1 - 8003174: e066 b.n 8003244 + 8002f7e: 2301 movs r3, #1 + 8002f80: e066 b.n 8003050 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - 8003176: 687b ldr r3, [r7, #4] - 8003178: 685b ldr r3, [r3, #4] - 800317a: 2b03 cmp r3, #3 - 800317c: d106 bne.n 800318c + 8002f82: 687b ldr r3, [r7, #4] + 8002f84: 685b ldr r3, [r3, #4] + 8002f86: 2b03 cmp r3, #3 + 8002f88: d106 bne.n 8002f98 { /* Check the PLL ready flag */ if (LL_RCC_PLL_IsReady() == 0U) - 800317e: f7ff fb42 bl 8002806 - 8003182: 4603 mov r3, r0 - 8003184: 2b00 cmp r3, #0 - 8003186: d113 bne.n 80031b0 + 8002f8a: f7ff fb42 bl 8002612 + 8002f8e: 4603 mov r3, r0 + 8002f90: 2b00 cmp r3, #0 + 8002f92: d113 bne.n 8002fbc { return HAL_ERROR; - 8003188: 2301 movs r3, #1 - 800318a: e05b b.n 8003244 + 8002f94: 2301 movs r3, #1 + 8002f96: e05b b.n 8003050 } } /* MSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) - 800318c: 687b ldr r3, [r7, #4] - 800318e: 685b ldr r3, [r3, #4] - 8003190: 2b00 cmp r3, #0 - 8003192: d106 bne.n 80031a2 + 8002f98: 687b ldr r3, [r7, #4] + 8002f9a: 685b ldr r3, [r3, #4] + 8002f9c: 2b00 cmp r3, #0 + 8002f9e: d106 bne.n 8002fae { /* Check the MSI ready flag */ if (LL_RCC_MSI_IsReady() == 0U) - 8003194: f7ff fa35 bl 8002602 - 8003198: 4603 mov r3, r0 - 800319a: 2b00 cmp r3, #0 - 800319c: d108 bne.n 80031b0 + 8002fa0: f7ff fa35 bl 800240e + 8002fa4: 4603 mov r3, r0 + 8002fa6: 2b00 cmp r3, #0 + 8002fa8: d108 bne.n 8002fbc { return HAL_ERROR; - 800319e: 2301 movs r3, #1 - 80031a0: e050 b.n 8003244 + 8002faa: 2301 movs r3, #1 + 8002fac: e050 b.n 8003050 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (LL_RCC_HSI_IsReady() == 0U) - 80031a2: f7ff f9ab bl 80024fc - 80031a6: 4603 mov r3, r0 - 80031a8: 2b00 cmp r3, #0 - 80031aa: d101 bne.n 80031b0 + 8002fae: f7ff f9ab bl 8002308 + 8002fb2: 4603 mov r3, r0 + 8002fb4: 2b00 cmp r3, #0 + 8002fb6: d101 bne.n 8002fbc { return HAL_ERROR; - 80031ac: 2301 movs r3, #1 - 80031ae: e049 b.n 8003244 + 8002fb8: 2301 movs r3, #1 + 8002fba: e049 b.n 8003050 } } /* apply system clock switch */ LL_RCC_SetSysClkSource(RCC_ClkInitStruct->SYSCLKSource); - 80031b0: 687b ldr r3, [r7, #4] - 80031b2: 685b ldr r3, [r3, #4] - 80031b4: 4618 mov r0, r3 - 80031b6: f7ff fa6f bl 8002698 + 8002fbc: 687b ldr r3, [r7, #4] + 8002fbe: 685b ldr r3, [r3, #4] + 8002fc0: 4618 mov r0, r3 + 8002fc2: f7ff fa6f bl 80024a4 /* Get Start Tick */ tickstart = HAL_GetTick(); - 80031ba: f7fe fb6f bl 800189c - 80031be: 60f8 str r0, [r7, #12] + 8002fc6: f7fe fb6f bl 80016a8 + 8002fca: 60f8 str r0, [r7, #12] /* check system clock source switch status */ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 80031c0: e00a b.n 80031d8 + 8002fcc: e00a b.n 8002fe4 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - 80031c2: f7fe fb6b bl 800189c - 80031c6: 4602 mov r2, r0 - 80031c8: 68fb ldr r3, [r7, #12] - 80031ca: 1ad3 subs r3, r2, r3 - 80031cc: f241 3288 movw r2, #5000 ; 0x1388 - 80031d0: 4293 cmp r3, r2 - 80031d2: d901 bls.n 80031d8 + 8002fce: f7fe fb6b bl 80016a8 + 8002fd2: 4602 mov r2, r0 + 8002fd4: 68fb ldr r3, [r7, #12] + 8002fd6: 1ad3 subs r3, r2, r3 + 8002fd8: f241 3288 movw r2, #5000 ; 0x1388 + 8002fdc: 4293 cmp r3, r2 + 8002fde: d901 bls.n 8002fe4 { return HAL_TIMEOUT; - 80031d4: 2303 movs r3, #3 - 80031d6: e035 b.n 8003244 + 8002fe0: 2303 movs r3, #3 + 8002fe2: e035 b.n 8003050 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 80031d8: f7ff fa71 bl 80026be - 80031dc: 4602 mov r2, r0 - 80031de: 687b ldr r3, [r7, #4] - 80031e0: 685b ldr r3, [r3, #4] - 80031e2: 009b lsls r3, r3, #2 - 80031e4: 429a cmp r2, r3 - 80031e6: d1ec bne.n 80031c2 + 8002fe4: f7ff fa71 bl 80024ca + 8002fe8: 4602 mov r2, r0 + 8002fea: 687b ldr r3, [r7, #4] + 8002fec: 685b ldr r3, [r3, #4] + 8002fee: 009b lsls r3, r3, #2 + 8002ff0: 429a cmp r2, r3 + 8002ff2: d1ec bne.n 8002fce } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) - 80031e8: 4b18 ldr r3, [pc, #96] ; (800324c ) - 80031ea: 681b ldr r3, [r3, #0] - 80031ec: f003 0307 and.w r3, r3, #7 - 80031f0: 683a ldr r2, [r7, #0] - 80031f2: 429a cmp r2, r3 - 80031f4: d21b bcs.n 800322e + 8002ff4: 4b18 ldr r3, [pc, #96] ; (8003058 ) + 8002ff6: 681b ldr r3, [r3, #0] + 8002ff8: f003 0307 and.w r3, r3, #7 + 8002ffc: 683a ldr r2, [r7, #0] + 8002ffe: 429a cmp r2, r3 + 8003000: d21b bcs.n 800303a { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 80031f6: 4b15 ldr r3, [pc, #84] ; (800324c ) - 80031f8: 681b ldr r3, [r3, #0] - 80031fa: f023 0207 bic.w r2, r3, #7 - 80031fe: 4913 ldr r1, [pc, #76] ; (800324c ) - 8003200: 683b ldr r3, [r7, #0] - 8003202: 4313 orrs r3, r2 - 8003204: 600b str r3, [r1, #0] + 8003002: 4b15 ldr r3, [pc, #84] ; (8003058 ) + 8003004: 681b ldr r3, [r3, #0] + 8003006: f023 0207 bic.w r2, r3, #7 + 800300a: 4913 ldr r1, [pc, #76] ; (8003058 ) + 800300c: 683b ldr r3, [r7, #0] + 800300e: 4313 orrs r3, r2 + 8003010: 600b str r3, [r1, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8003206: f7fe fb49 bl 800189c - 800320a: 60f8 str r0, [r7, #12] + 8003012: f7fe fb49 bl 80016a8 + 8003016: 60f8 str r0, [r7, #12] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ while (__HAL_FLASH_GET_LATENCY() != FLatency) - 800320c: e008 b.n 8003220 + 8003018: e008 b.n 800302c { if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) - 800320e: f7fe fb45 bl 800189c - 8003212: 4602 mov r2, r0 - 8003214: 68fb ldr r3, [r7, #12] - 8003216: 1ad3 subs r3, r2, r3 - 8003218: 2b02 cmp r3, #2 - 800321a: d901 bls.n 8003220 + 800301a: f7fe fb45 bl 80016a8 + 800301e: 4602 mov r2, r0 + 8003020: 68fb ldr r3, [r7, #12] + 8003022: 1ad3 subs r3, r2, r3 + 8003024: 2b02 cmp r3, #2 + 8003026: d901 bls.n 800302c { return HAL_TIMEOUT; - 800321c: 2303 movs r3, #3 - 800321e: e011 b.n 8003244 + 8003028: 2303 movs r3, #3 + 800302a: e011 b.n 8003050 while (__HAL_FLASH_GET_LATENCY() != FLatency) - 8003220: 4b0a ldr r3, [pc, #40] ; (800324c ) - 8003222: 681b ldr r3, [r3, #0] - 8003224: f003 0307 and.w r3, r3, #7 - 8003228: 683a ldr r2, [r7, #0] - 800322a: 429a cmp r2, r3 - 800322c: d1ef bne.n 800320e + 800302c: 4b0a ldr r3, [pc, #40] ; (8003058 ) + 800302e: 681b ldr r3, [r3, #0] + 8003030: f003 0307 and.w r3, r3, #7 + 8003034: 683a ldr r2, [r7, #0] + 8003036: 429a cmp r2, r3 + 8003038: d1ef bne.n 800301a } /*--------------------------------------------------------------------------*/ /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetHCLKFreq(); - 800322e: f000 f8b3 bl 8003398 - 8003232: 4603 mov r3, r0 - 8003234: 4a06 ldr r2, [pc, #24] ; (8003250 ) - 8003236: 6013 str r3, [r2, #0] + 800303a: f000 f8b3 bl 80031a4 + 800303e: 4603 mov r3, r0 + 8003040: 4a06 ldr r2, [pc, #24] ; (800305c ) + 8003042: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ return HAL_InitTick(uwTickPrio); - 8003238: 4b06 ldr r3, [pc, #24] ; (8003254 ) - 800323a: 681b ldr r3, [r3, #0] - 800323c: 4618 mov r0, r3 - 800323e: f7fe fae1 bl 8001804 - 8003242: 4603 mov r3, r0 -} - 8003244: 4618 mov r0, r3 - 8003246: 3710 adds r7, #16 - 8003248: 46bd mov sp, r7 - 800324a: bd80 pop {r7, pc} - 800324c: 58004000 .word 0x58004000 - 8003250: 20000008 .word 0x20000008 - 8003254: 2000000c .word 0x2000000c - -08003258 : + 8003044: 4b06 ldr r3, [pc, #24] ; (8003060 ) + 8003046: 681b ldr r3, [r3, #0] + 8003048: 4618 mov r0, r3 + 800304a: f7fe fae1 bl 8001610 + 800304e: 4603 mov r3, r0 +} + 8003050: 4618 mov r0, r3 + 8003052: 3710 adds r7, #16 + 8003054: 46bd mov sp, r7 + 8003056: bd80 pop {r7, pc} + 8003058: 58004000 .word 0x58004000 + 800305c: 20000000 .word 0x20000000 + 8003060: 20000004 .word 0x20000004 + +08003064 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { - 8003258: b590 push {r4, r7, lr} - 800325a: b087 sub sp, #28 - 800325c: af00 add r7, sp, #0 + 8003064: b590 push {r4, r7, lr} + 8003066: b087 sub sp, #28 + 8003068: af00 add r7, sp, #0 uint32_t sysclk_source; uint32_t pllsource; uint32_t sysclockfreq = 0U; - 800325e: 2300 movs r3, #0 - 8003260: 617b str r3, [r7, #20] + 800306a: 2300 movs r3, #0 + 800306c: 617b str r3, [r7, #20] uint32_t msifreq = 0U; - 8003262: 2300 movs r3, #0 - 8003264: 613b str r3, [r7, #16] + 800306e: 2300 movs r3, #0 + 8003070: 613b str r3, [r7, #16] uint32_t pllinputfreq; sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); - 8003266: f7ff fa2a bl 80026be - 800326a: 60b8 str r0, [r7, #8] + 8003072: f7ff fa2a bl 80024ca + 8003076: 60b8 str r0, [r7, #8] pllsource = __HAL_RCC_GET_PLL_OSCSOURCE(); - 800326c: f7ff fafe bl 800286c - 8003270: 6078 str r0, [r7, #4] + 8003078: f7ff fafe bl 8002678 + 800307c: 6078 str r0, [r7, #4] if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || - 8003272: 68bb ldr r3, [r7, #8] - 8003274: 2b00 cmp r3, #0 - 8003276: d005 beq.n 8003284 - 8003278: 68bb ldr r3, [r7, #8] - 800327a: 2b0c cmp r3, #12 - 800327c: d139 bne.n 80032f2 + 800307e: 68bb ldr r3, [r7, #8] + 8003080: 2b00 cmp r3, #0 + 8003082: d005 beq.n 8003090 + 8003084: 68bb ldr r3, [r7, #8] + 8003086: 2b0c cmp r3, #12 + 8003088: d139 bne.n 80030fe ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pllsource == RCC_PLLSOURCE_MSI))) - 800327e: 687b ldr r3, [r7, #4] - 8003280: 2b01 cmp r3, #1 - 8003282: d136 bne.n 80032f2 + 800308a: 687b ldr r3, [r7, #4] + 800308c: 2b01 cmp r3, #1 + 800308e: d136 bne.n 80030fe { /* MSI or PLL with MSI source used as system clock source */ /* Retrieve MSI frequency range in Hz */ msifreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - 8003284: f7ff f9cd bl 8002622 - 8003288: 4603 mov r3, r0 - 800328a: 2b00 cmp r3, #0 - 800328c: d115 bne.n 80032ba - 800328e: f7ff f9c8 bl 8002622 - 8003292: 4603 mov r3, r0 - 8003294: 2b01 cmp r3, #1 - 8003296: d106 bne.n 80032a6 - 8003298: f7ff f9d3 bl 8002642 - 800329c: 4603 mov r3, r0 - 800329e: 0a1b lsrs r3, r3, #8 - 80032a0: f003 030f and.w r3, r3, #15 - 80032a4: e005 b.n 80032b2 - 80032a6: f7ff f9d7 bl 8002658 - 80032aa: 4603 mov r3, r0 - 80032ac: 0a1b lsrs r3, r3, #8 - 80032ae: f003 030f and.w r3, r3, #15 - 80032b2: 4a36 ldr r2, [pc, #216] ; (800338c ) - 80032b4: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 80032b8: e014 b.n 80032e4 - 80032ba: f7ff f9b2 bl 8002622 - 80032be: 4603 mov r3, r0 - 80032c0: 2b01 cmp r3, #1 - 80032c2: d106 bne.n 80032d2 - 80032c4: f7ff f9bd bl 8002642 - 80032c8: 4603 mov r3, r0 - 80032ca: 091b lsrs r3, r3, #4 - 80032cc: f003 030f and.w r3, r3, #15 - 80032d0: e005 b.n 80032de - 80032d2: f7ff f9c1 bl 8002658 - 80032d6: 4603 mov r3, r0 - 80032d8: 091b lsrs r3, r3, #4 - 80032da: f003 030f and.w r3, r3, #15 - 80032de: 4a2b ldr r2, [pc, #172] ; (800338c ) - 80032e0: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 80032e4: 613b str r3, [r7, #16] + 8003090: f7ff f9cd bl 800242e + 8003094: 4603 mov r3, r0 + 8003096: 2b00 cmp r3, #0 + 8003098: d115 bne.n 80030c6 + 800309a: f7ff f9c8 bl 800242e + 800309e: 4603 mov r3, r0 + 80030a0: 2b01 cmp r3, #1 + 80030a2: d106 bne.n 80030b2 + 80030a4: f7ff f9d3 bl 800244e + 80030a8: 4603 mov r3, r0 + 80030aa: 0a1b lsrs r3, r3, #8 + 80030ac: f003 030f and.w r3, r3, #15 + 80030b0: e005 b.n 80030be + 80030b2: f7ff f9d7 bl 8002464 + 80030b6: 4603 mov r3, r0 + 80030b8: 0a1b lsrs r3, r3, #8 + 80030ba: f003 030f and.w r3, r3, #15 + 80030be: 4a36 ldr r2, [pc, #216] ; (8003198 ) + 80030c0: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80030c4: e014 b.n 80030f0 + 80030c6: f7ff f9b2 bl 800242e + 80030ca: 4603 mov r3, r0 + 80030cc: 2b01 cmp r3, #1 + 80030ce: d106 bne.n 80030de + 80030d0: f7ff f9bd bl 800244e + 80030d4: 4603 mov r3, r0 + 80030d6: 091b lsrs r3, r3, #4 + 80030d8: f003 030f and.w r3, r3, #15 + 80030dc: e005 b.n 80030ea + 80030de: f7ff f9c1 bl 8002464 + 80030e2: 4603 mov r3, r0 + 80030e4: 091b lsrs r3, r3, #4 + 80030e6: f003 030f and.w r3, r3, #15 + 80030ea: 4a2b ldr r2, [pc, #172] ; (8003198 ) + 80030ec: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80030f0: 613b str r3, [r7, #16] ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ? LL_RCC_MSI_GetRange() : LL_RCC_MSI_GetRangeAfterStandby())); /* Get SYSCLK source */ if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) - 80032e6: 68bb ldr r3, [r7, #8] - 80032e8: 2b00 cmp r3, #0 - 80032ea: d115 bne.n 8003318 + 80030f2: 68bb ldr r3, [r7, #8] + 80030f4: 2b00 cmp r3, #0 + 80030f6: d115 bne.n 8003124 { /* MSI used as system clock source */ sysclockfreq = msifreq; - 80032ec: 693b ldr r3, [r7, #16] - 80032ee: 617b str r3, [r7, #20] + 80030f8: 693b ldr r3, [r7, #16] + 80030fa: 617b str r3, [r7, #20] if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) - 80032f0: e012 b.n 8003318 + 80030fc: e012 b.n 8003124 } } else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) - 80032f2: 68bb ldr r3, [r7, #8] - 80032f4: 2b04 cmp r3, #4 - 80032f6: d102 bne.n 80032fe + 80030fe: 68bb ldr r3, [r7, #8] + 8003100: 2b04 cmp r3, #4 + 8003102: d102 bne.n 800310a { /* HSI used as system clock source */ sysclockfreq = HSI_VALUE; - 80032f8: 4b25 ldr r3, [pc, #148] ; (8003390 ) - 80032fa: 617b str r3, [r7, #20] - 80032fc: e00c b.n 8003318 + 8003104: 4b25 ldr r3, [pc, #148] ; (800319c ) + 8003106: 617b str r3, [r7, #20] + 8003108: e00c b.n 8003124 } else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) - 80032fe: 68bb ldr r3, [r7, #8] - 8003300: 2b08 cmp r3, #8 - 8003302: d109 bne.n 8003318 + 800310a: 68bb ldr r3, [r7, #8] + 800310c: 2b08 cmp r3, #8 + 800310e: d109 bne.n 8003124 { /* HSE used as system clock source */ if (LL_RCC_HSE_IsEnabledDiv2() == 1U) - 8003304: f7ff f8a0 bl 8002448 - 8003308: 4603 mov r3, r0 - 800330a: 2b01 cmp r3, #1 - 800330c: d102 bne.n 8003314 + 8003110: f7ff f8a0 bl 8002254 + 8003114: 4603 mov r3, r0 + 8003116: 2b01 cmp r3, #1 + 8003118: d102 bne.n 8003120 { sysclockfreq = HSE_VALUE / 2U; - 800330e: 4b20 ldr r3, [pc, #128] ; (8003390 ) - 8003310: 617b str r3, [r7, #20] - 8003312: e001 b.n 8003318 + 800311a: 4b20 ldr r3, [pc, #128] ; (800319c ) + 800311c: 617b str r3, [r7, #20] + 800311e: e001 b.n 8003124 } else { sysclockfreq = HSE_VALUE; - 8003314: 4b1f ldr r3, [pc, #124] ; (8003394 ) - 8003316: 617b str r3, [r7, #20] + 8003120: 4b1f ldr r3, [pc, #124] ; (80031a0 ) + 8003122: 617b str r3, [r7, #20] else { /* Nothing to do */ } if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) - 8003318: f7ff f9d1 bl 80026be - 800331c: 4603 mov r3, r0 - 800331e: 2b0c cmp r3, #12 - 8003320: d12f bne.n 8003382 + 8003124: f7ff f9d1 bl 80024ca + 8003128: 4603 mov r3, r0 + 800312a: 2b0c cmp r3, #12 + 800312c: d12f bne.n 800318e { /* PLL used as system clock source */ pllsource = LL_RCC_PLL_GetMainSource(); - 8003322: f7ff faa3 bl 800286c - 8003326: 6078 str r0, [r7, #4] + 800312e: f7ff faa3 bl 8002678 + 8003132: 6078 str r0, [r7, #4] switch (pllsource) - 8003328: 687b ldr r3, [r7, #4] - 800332a: 2b02 cmp r3, #2 - 800332c: d003 beq.n 8003336 - 800332e: 687b ldr r3, [r7, #4] - 8003330: 2b03 cmp r3, #3 - 8003332: d003 beq.n 800333c - 8003334: e00d b.n 8003352 + 8003134: 687b ldr r3, [r7, #4] + 8003136: 2b02 cmp r3, #2 + 8003138: d003 beq.n 8003142 + 800313a: 687b ldr r3, [r7, #4] + 800313c: 2b03 cmp r3, #3 + 800313e: d003 beq.n 8003148 + 8003140: e00d b.n 800315e { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ pllinputfreq = HSI_VALUE; - 8003336: 4b16 ldr r3, [pc, #88] ; (8003390 ) - 8003338: 60fb str r3, [r7, #12] + 8003142: 4b16 ldr r3, [pc, #88] ; (800319c ) + 8003144: 60fb str r3, [r7, #12] break; - 800333a: e00d b.n 8003358 + 8003146: e00d b.n 8003164 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ if (LL_RCC_HSE_IsEnabledDiv2() == 1U) - 800333c: f7ff f884 bl 8002448 - 8003340: 4603 mov r3, r0 - 8003342: 2b01 cmp r3, #1 - 8003344: d102 bne.n 800334c + 8003148: f7ff f884 bl 8002254 + 800314c: 4603 mov r3, r0 + 800314e: 2b01 cmp r3, #1 + 8003150: d102 bne.n 8003158 { pllinputfreq = HSE_VALUE / 2U; - 8003346: 4b12 ldr r3, [pc, #72] ; (8003390 ) - 8003348: 60fb str r3, [r7, #12] + 8003152: 4b12 ldr r3, [pc, #72] ; (800319c ) + 8003154: 60fb str r3, [r7, #12] } else { pllinputfreq = HSE_VALUE; } break; - 800334a: e005 b.n 8003358 + 8003156: e005 b.n 8003164 pllinputfreq = HSE_VALUE; - 800334c: 4b11 ldr r3, [pc, #68] ; (8003394 ) - 800334e: 60fb str r3, [r7, #12] + 8003158: 4b11 ldr r3, [pc, #68] ; (80031a0 ) + 800315a: 60fb str r3, [r7, #12] break; - 8003350: e002 b.n 8003358 + 800315c: e002 b.n 8003164 case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ default: pllinputfreq = msifreq; - 8003352: 693b ldr r3, [r7, #16] - 8003354: 60fb str r3, [r7, #12] + 800315e: 693b ldr r3, [r7, #16] + 8003160: 60fb str r3, [r7, #12] break; - 8003356: bf00 nop + 8003162: bf00 nop } sysclockfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), - 8003358: f7ff fa66 bl 8002828 - 800335c: 4602 mov r2, r0 - 800335e: 68fb ldr r3, [r7, #12] - 8003360: fb03 f402 mul.w r4, r3, r2 - 8003364: f7ff fa77 bl 8002856 - 8003368: 4603 mov r3, r0 - 800336a: 091b lsrs r3, r3, #4 - 800336c: 3301 adds r3, #1 - 800336e: fbb4 f4f3 udiv r4, r4, r3 - 8003372: f7ff fa65 bl 8002840 - 8003376: 4603 mov r3, r0 - 8003378: 0f5b lsrs r3, r3, #29 - 800337a: 3301 adds r3, #1 - 800337c: fbb4 f3f3 udiv r3, r4, r3 - 8003380: 617b str r3, [r7, #20] + 8003164: f7ff fa66 bl 8002634 + 8003168: 4602 mov r2, r0 + 800316a: 68fb ldr r3, [r7, #12] + 800316c: fb03 f402 mul.w r4, r3, r2 + 8003170: f7ff fa77 bl 8002662 + 8003174: 4603 mov r3, r0 + 8003176: 091b lsrs r3, r3, #4 + 8003178: 3301 adds r3, #1 + 800317a: fbb4 f4f3 udiv r4, r4, r3 + 800317e: f7ff fa65 bl 800264c + 8003182: 4603 mov r3, r0 + 8003184: 0f5b lsrs r3, r3, #29 + 8003186: 3301 adds r3, #1 + 8003188: fbb4 f3f3 udiv r3, r4, r3 + 800318c: 617b str r3, [r7, #20] LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); } return sysclockfreq; - 8003382: 697b ldr r3, [r7, #20] + 800318e: 697b ldr r3, [r7, #20] } - 8003384: 4618 mov r0, r3 - 8003386: 371c adds r7, #28 - 8003388: 46bd mov sp, r7 - 800338a: bd90 pop {r4, r7, pc} - 800338c: 08004a74 .word 0x08004a74 - 8003390: 00f42400 .word 0x00f42400 - 8003394: 01e84800 .word 0x01e84800 + 8003190: 4618 mov r0, r3 + 8003192: 371c adds r7, #28 + 8003194: 46bd mov sp, r7 + 8003196: bd90 pop {r4, r7, pc} + 8003198: 08004818 .word 0x08004818 + 800319c: 00f42400 .word 0x00f42400 + 80031a0: 01e84800 .word 0x01e84800 -08003398 : +080031a4 : /** * @brief Return the HCLK frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { - 8003398: b598 push {r3, r4, r7, lr} - 800339a: af00 add r7, sp, #0 + 80031a4: b598 push {r3, r4, r7, lr} + 80031a6: af00 add r7, sp, #0 /* Get SysClock and Compute HCLK1 frequency --------------------------------*/ return ((uint32_t)(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()))); - 800339c: f7ff ff5c bl 8003258 - 80033a0: 4604 mov r4, r0 - 80033a2: f7ff f9e6 bl 8002772 - 80033a6: 4603 mov r3, r0 - 80033a8: 091b lsrs r3, r3, #4 - 80033aa: f003 030f and.w r3, r3, #15 - 80033ae: 4a03 ldr r2, [pc, #12] ; (80033bc ) - 80033b0: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 80033b4: fbb4 f3f3 udiv r3, r4, r3 -} - 80033b8: 4618 mov r0, r3 - 80033ba: bd98 pop {r3, r4, r7, pc} - 80033bc: 08004a14 .word 0x08004a14 - -080033c0 : + 80031a8: f7ff ff5c bl 8003064 + 80031ac: 4604 mov r4, r0 + 80031ae: f7ff f9e6 bl 800257e + 80031b2: 4603 mov r3, r0 + 80031b4: 091b lsrs r3, r3, #4 + 80031b6: f003 030f and.w r3, r3, #15 + 80031ba: 4a03 ldr r2, [pc, #12] ; (80031c8 ) + 80031bc: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80031c0: fbb4 f3f3 udiv r3, r4, r3 +} + 80031c4: 4618 mov r0, r3 + 80031c6: bd98 pop {r3, r4, r7, pc} + 80031c8: 080047b8 .word 0x080047b8 + +080031cc : /** * @brief Return the PCLK1 frequency. * @retval PCLK1 frequency in Hz */ uint32_t HAL_RCC_GetPCLK1Freq(void) { - 80033c0: b598 push {r3, r4, r7, lr} - 80033c2: af00 add r7, sp, #0 + 80031cc: b598 push {r3, r4, r7, lr} + 80031ce: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency -----------------------------*/ return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler()))); - 80033c4: f7ff ffe8 bl 8003398 - 80033c8: 4604 mov r4, r0 - 80033ca: f7ff f9ea bl 80027a2 - 80033ce: 4603 mov r3, r0 - 80033d0: 0a1b lsrs r3, r3, #8 - 80033d2: 4a03 ldr r2, [pc, #12] ; (80033e0 ) - 80033d4: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 80033d8: fa24 f303 lsr.w r3, r4, r3 -} - 80033dc: 4618 mov r0, r3 - 80033de: bd98 pop {r3, r4, r7, pc} - 80033e0: 08004a54 .word 0x08004a54 - -080033e4 : + 80031d0: f7ff ffe8 bl 80031a4 + 80031d4: 4604 mov r4, r0 + 80031d6: f7ff f9ea bl 80025ae + 80031da: 4603 mov r3, r0 + 80031dc: 0a1b lsrs r3, r3, #8 + 80031de: 4a03 ldr r2, [pc, #12] ; (80031ec ) + 80031e0: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80031e4: fa24 f303 lsr.w r3, r4, r3 +} + 80031e8: 4618 mov r0, r3 + 80031ea: bd98 pop {r3, r4, r7, pc} + 80031ec: 080047f8 .word 0x080047f8 + +080031f0 : /** * @brief Return the PCLK2 frequency. * @retval PCLK2 frequency in Hz */ uint32_t HAL_RCC_GetPCLK2Freq(void) { - 80033e4: b598 push {r3, r4, r7, lr} - 80033e6: af00 add r7, sp, #0 + 80031f0: b598 push {r3, r4, r7, lr} + 80031f2: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency -----------------------------*/ return ((uint32_t)(__LL_RCC_CALC_PCLK2_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB2Prescaler()))); - 80033e8: f7ff ffd6 bl 8003398 - 80033ec: 4604 mov r4, r0 - 80033ee: f7ff f9e3 bl 80027b8 - 80033f2: 4603 mov r3, r0 - 80033f4: 0adb lsrs r3, r3, #11 - 80033f6: 4a03 ldr r2, [pc, #12] ; (8003404 ) - 80033f8: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 80033fc: fa24 f303 lsr.w r3, r4, r3 -} - 8003400: 4618 mov r0, r3 - 8003402: bd98 pop {r3, r4, r7, pc} - 8003404: 08004a54 .word 0x08004a54 - -08003408 : + 80031f4: f7ff ffd6 bl 80031a4 + 80031f8: 4604 mov r4, r0 + 80031fa: f7ff f9e3 bl 80025c4 + 80031fe: 4603 mov r3, r0 + 8003200: 0adb lsrs r3, r3, #11 + 8003202: 4a03 ldr r2, [pc, #12] ; (8003210 ) + 8003204: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8003208: fa24 f303 lsr.w r3, r4, r3 +} + 800320c: 4618 mov r0, r3 + 800320e: bd98 pop {r3, r4, r7, pc} + 8003210: 080047f8 .word 0x080047f8 + +08003214 : voltage range. * @param MSI_Range MSI range value from @ref RCC_MSIRANGE_0 to @ref RCC_MSIRANGE_11 * @retval HAL status */ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range) { - 8003408: b590 push {r4, r7, lr} - 800340a: b085 sub sp, #20 - 800340c: af00 add r7, sp, #0 - 800340e: 6078 str r0, [r7, #4] + 8003214: b590 push {r4, r7, lr} + 8003216: b085 sub sp, #20 + 8003218: af00 add r7, sp, #0 + 800321a: 6078 str r0, [r7, #4] uint32_t flash_clksrcfreq; uint32_t msifreq; /* MSI frequency range in Hz */ msifreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGESEL_RUN, MSI_Range); - 8003410: 687b ldr r3, [r7, #4] - 8003412: 091b lsrs r3, r3, #4 - 8003414: f003 030f and.w r3, r3, #15 - 8003418: 4a10 ldr r2, [pc, #64] ; (800345c ) - 800341a: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 800341e: 60fb str r3, [r7, #12] + 800321c: 687b ldr r3, [r7, #4] + 800321e: 091b lsrs r3, r3, #4 + 8003220: f003 030f and.w r3, r3, #15 + 8003224: 4a10 ldr r2, [pc, #64] ; (8003268 ) + 8003226: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800322a: 60fb str r3, [r7, #12] flash_clksrcfreq = __LL_RCC_CALC_HCLK3_FREQ(msifreq, LL_RCC_GetAHB3Prescaler()); - 8003420: f7ff f9b2 bl 8002788 - 8003424: 4603 mov r3, r0 - 8003426: 091b lsrs r3, r3, #4 - 8003428: f003 030f and.w r3, r3, #15 - 800342c: 4a0c ldr r2, [pc, #48] ; (8003460 ) - 800342e: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8003432: 68fa ldr r2, [r7, #12] - 8003434: fbb2 f3f3 udiv r3, r2, r3 - 8003438: 60bb str r3, [r7, #8] + 800322c: f7ff f9b2 bl 8002594 + 8003230: 4603 mov r3, r0 + 8003232: 091b lsrs r3, r3, #4 + 8003234: f003 030f and.w r3, r3, #15 + 8003238: 4a0c ldr r2, [pc, #48] ; (800326c ) + 800323a: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800323e: 68fa ldr r2, [r7, #12] + 8003240: fbb2 f3f3 udiv r3, r2, r3 + 8003244: 60bb str r3, [r7, #8] return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), HAL_PWREx_GetVoltageRange()); - 800343a: 68bb ldr r3, [r7, #8] - 800343c: 4a09 ldr r2, [pc, #36] ; (8003464 ) - 800343e: fba2 2303 umull r2, r3, r2, r3 - 8003442: 0c9c lsrs r4, r3, #18 - 8003444: f7fe ffc6 bl 80023d4 - 8003448: 4603 mov r3, r0 - 800344a: 4619 mov r1, r3 - 800344c: 4620 mov r0, r4 - 800344e: f000 f80b bl 8003468 - 8003452: 4603 mov r3, r0 -} - 8003454: 4618 mov r0, r3 - 8003456: 3714 adds r7, #20 - 8003458: 46bd mov sp, r7 - 800345a: bd90 pop {r4, r7, pc} - 800345c: 08004a74 .word 0x08004a74 - 8003460: 08004a14 .word 0x08004a14 - 8003464: 431bde83 .word 0x431bde83 - -08003468 : + 8003246: 68bb ldr r3, [r7, #8] + 8003248: 4a09 ldr r2, [pc, #36] ; (8003270 ) + 800324a: fba2 2303 umull r2, r3, r2, r3 + 800324e: 0c9c lsrs r4, r3, #18 + 8003250: f7fe ffc6 bl 80021e0 + 8003254: 4603 mov r3, r0 + 8003256: 4619 mov r1, r3 + 8003258: 4620 mov r0, r4 + 800325a: f000 f80b bl 8003274 + 800325e: 4603 mov r3, r0 +} + 8003260: 4618 mov r0, r3 + 8003262: 3714 adds r7, #20 + 8003264: 46bd mov sp, r7 + 8003266: bd90 pop {r4, r7, pc} + 8003268: 08004818 .word 0x08004818 + 800326c: 080047b8 .word 0x080047b8 + 8003270: 431bde83 .word 0x431bde83 + +08003274 : * @arg PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode * @arg PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode * @retval HAL status */ static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage) { - 8003468: b580 push {r7, lr} - 800346a: b08e sub sp, #56 ; 0x38 - 800346c: af00 add r7, sp, #0 - 800346e: 6078 str r0, [r7, #4] - 8003470: 6039 str r1, [r7, #0] + 8003274: b580 push {r7, lr} + 8003276: b08e sub sp, #56 ; 0x38 + 8003278: af00 add r7, sp, #0 + 800327a: 6078 str r0, [r7, #4] + 800327c: 6039 str r1, [r7, #0] /* Flash Clock source (HCLK3) range in MHz for VCORE range1 */ const uint16_t FLASH_CLK_SRC_RANGE_VOS1[] = {18, 36, 48}; - 8003472: 4a3a ldr r2, [pc, #232] ; (800355c ) - 8003474: f107 0320 add.w r3, r7, #32 - 8003478: e892 0003 ldmia.w r2, {r0, r1} - 800347c: 6018 str r0, [r3, #0] - 800347e: 3304 adds r3, #4 - 8003480: 8019 strh r1, [r3, #0] + 800327e: 4a3a ldr r2, [pc, #232] ; (8003368 ) + 8003280: f107 0320 add.w r3, r7, #32 + 8003284: e892 0003 ldmia.w r2, {r0, r1} + 8003288: 6018 str r0, [r3, #0] + 800328a: 3304 adds r3, #4 + 800328c: 8019 strh r1, [r3, #0] /* Flash Clock source (HCLK3) range in MHz for VCORE range2 */ const uint16_t FLASH_CLK_SRC_RANGE_VOS2[] = {6, 12, 16}; - 8003482: 4a37 ldr r2, [pc, #220] ; (8003560 ) - 8003484: f107 0318 add.w r3, r7, #24 - 8003488: e892 0003 ldmia.w r2, {r0, r1} - 800348c: 6018 str r0, [r3, #0] - 800348e: 3304 adds r3, #4 - 8003490: 8019 strh r1, [r3, #0] + 800328e: 4a37 ldr r2, [pc, #220] ; (800336c ) + 8003290: f107 0318 add.w r3, r7, #24 + 8003294: e892 0003 ldmia.w r2, {r0, r1} + 8003298: 6018 str r0, [r3, #0] + 800329a: 3304 adds r3, #4 + 800329c: 8019 strh r1, [r3, #0] /* Flash Latency range */ const uint32_t FLASH_LATENCY_RANGE[] = {FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2}; - 8003492: 4a34 ldr r2, [pc, #208] ; (8003564 ) - 8003494: f107 030c add.w r3, r7, #12 - 8003498: ca07 ldmia r2, {r0, r1, r2} - 800349a: e883 0007 stmia.w r3, {r0, r1, r2} + 800329e: 4a34 ldr r2, [pc, #208] ; (8003370 ) + 80032a0: f107 030c add.w r3, r7, #12 + 80032a4: ca07 ldmia r2, {r0, r1, r2} + 80032a6: e883 0007 stmia.w r3, {r0, r1, r2} uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ - 800349e: 2300 movs r3, #0 - 80034a0: 637b str r3, [r7, #52] ; 0x34 + 80032aa: 2300 movs r3, #0 + 80032ac: 637b str r3, [r7, #52] ; 0x34 uint32_t tickstart; if (VCORE_Voltage == PWR_REGULATOR_VOLTAGE_SCALE1) - 80034a2: 683b ldr r3, [r7, #0] - 80034a4: f5b3 7f00 cmp.w r3, #512 ; 0x200 - 80034a8: d11b bne.n 80034e2 + 80032ae: 683b ldr r3, [r7, #0] + 80032b0: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 80032b4: d11b bne.n 80032ee { for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) - 80034aa: 2300 movs r3, #0 - 80034ac: 633b str r3, [r7, #48] ; 0x30 - 80034ae: e014 b.n 80034da + 80032b6: 2300 movs r3, #0 + 80032b8: 633b str r3, [r7, #48] ; 0x30 + 80032ba: e014 b.n 80032e6 { if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS1[index]) - 80034b0: 6b3b ldr r3, [r7, #48] ; 0x30 - 80034b2: 005b lsls r3, r3, #1 - 80034b4: 3338 adds r3, #56 ; 0x38 - 80034b6: 443b add r3, r7 - 80034b8: f833 3c18 ldrh.w r3, [r3, #-24] - 80034bc: 461a mov r2, r3 - 80034be: 687b ldr r3, [r7, #4] - 80034c0: 4293 cmp r3, r2 - 80034c2: d807 bhi.n 80034d4 + 80032bc: 6b3b ldr r3, [r7, #48] ; 0x30 + 80032be: 005b lsls r3, r3, #1 + 80032c0: 3338 adds r3, #56 ; 0x38 + 80032c2: 443b add r3, r7 + 80032c4: f833 3c18 ldrh.w r3, [r3, #-24] + 80032c8: 461a mov r2, r3 + 80032ca: 687b ldr r3, [r7, #4] + 80032cc: 4293 cmp r3, r2 + 80032ce: d807 bhi.n 80032e0 { latency = FLASH_LATENCY_RANGE[index]; - 80034c4: 6b3b ldr r3, [r7, #48] ; 0x30 - 80034c6: 009b lsls r3, r3, #2 - 80034c8: 3338 adds r3, #56 ; 0x38 - 80034ca: 443b add r3, r7 - 80034cc: f853 3c2c ldr.w r3, [r3, #-44] - 80034d0: 637b str r3, [r7, #52] ; 0x34 + 80032d0: 6b3b ldr r3, [r7, #48] ; 0x30 + 80032d2: 009b lsls r3, r3, #2 + 80032d4: 3338 adds r3, #56 ; 0x38 + 80032d6: 443b add r3, r7 + 80032d8: f853 3c2c ldr.w r3, [r3, #-44] + 80032dc: 637b str r3, [r7, #52] ; 0x34 break; - 80034d2: e021 b.n 8003518 + 80032de: e021 b.n 8003324 for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) - 80034d4: 6b3b ldr r3, [r7, #48] ; 0x30 - 80034d6: 3301 adds r3, #1 - 80034d8: 633b str r3, [r7, #48] ; 0x30 - 80034da: 6b3b ldr r3, [r7, #48] ; 0x30 - 80034dc: 2b02 cmp r3, #2 - 80034de: d9e7 bls.n 80034b0 - 80034e0: e01a b.n 8003518 + 80032e0: 6b3b ldr r3, [r7, #48] ; 0x30 + 80032e2: 3301 adds r3, #1 + 80032e4: 633b str r3, [r7, #48] ; 0x30 + 80032e6: 6b3b ldr r3, [r7, #48] ; 0x30 + 80032e8: 2b02 cmp r3, #2 + 80032ea: d9e7 bls.n 80032bc + 80032ec: e01a b.n 8003324 } } } else /* PWR_REGULATOR_VOLTAGE_SCALE2 */ { for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) - 80034e2: 2300 movs r3, #0 - 80034e4: 62fb str r3, [r7, #44] ; 0x2c - 80034e6: e014 b.n 8003512 + 80032ee: 2300 movs r3, #0 + 80032f0: 62fb str r3, [r7, #44] ; 0x2c + 80032f2: e014 b.n 800331e { if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS2[index]) - 80034e8: 6afb ldr r3, [r7, #44] ; 0x2c - 80034ea: 005b lsls r3, r3, #1 - 80034ec: 3338 adds r3, #56 ; 0x38 - 80034ee: 443b add r3, r7 - 80034f0: f833 3c20 ldrh.w r3, [r3, #-32] - 80034f4: 461a mov r2, r3 - 80034f6: 687b ldr r3, [r7, #4] - 80034f8: 4293 cmp r3, r2 - 80034fa: d807 bhi.n 800350c + 80032f4: 6afb ldr r3, [r7, #44] ; 0x2c + 80032f6: 005b lsls r3, r3, #1 + 80032f8: 3338 adds r3, #56 ; 0x38 + 80032fa: 443b add r3, r7 + 80032fc: f833 3c20 ldrh.w r3, [r3, #-32] + 8003300: 461a mov r2, r3 + 8003302: 687b ldr r3, [r7, #4] + 8003304: 4293 cmp r3, r2 + 8003306: d807 bhi.n 8003318 { latency = FLASH_LATENCY_RANGE[index]; - 80034fc: 6afb ldr r3, [r7, #44] ; 0x2c - 80034fe: 009b lsls r3, r3, #2 - 8003500: 3338 adds r3, #56 ; 0x38 - 8003502: 443b add r3, r7 - 8003504: f853 3c2c ldr.w r3, [r3, #-44] - 8003508: 637b str r3, [r7, #52] ; 0x34 + 8003308: 6afb ldr r3, [r7, #44] ; 0x2c + 800330a: 009b lsls r3, r3, #2 + 800330c: 3338 adds r3, #56 ; 0x38 + 800330e: 443b add r3, r7 + 8003310: f853 3c2c ldr.w r3, [r3, #-44] + 8003314: 637b str r3, [r7, #52] ; 0x34 break; - 800350a: e005 b.n 8003518 + 8003316: e005 b.n 8003324 for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) - 800350c: 6afb ldr r3, [r7, #44] ; 0x2c - 800350e: 3301 adds r3, #1 - 8003510: 62fb str r3, [r7, #44] ; 0x2c - 8003512: 6afb ldr r3, [r7, #44] ; 0x2c - 8003514: 2b02 cmp r3, #2 - 8003516: d9e7 bls.n 80034e8 + 8003318: 6afb ldr r3, [r7, #44] ; 0x2c + 800331a: 3301 adds r3, #1 + 800331c: 62fb str r3, [r7, #44] ; 0x2c + 800331e: 6afb ldr r3, [r7, #44] ; 0x2c + 8003320: 2b02 cmp r3, #2 + 8003322: d9e7 bls.n 80032f4 } } } __HAL_FLASH_SET_LATENCY(latency); - 8003518: 4b13 ldr r3, [pc, #76] ; (8003568 ) - 800351a: 681b ldr r3, [r3, #0] - 800351c: f023 0207 bic.w r2, r3, #7 - 8003520: 4911 ldr r1, [pc, #68] ; (8003568 ) - 8003522: 6b7b ldr r3, [r7, #52] ; 0x34 - 8003524: 4313 orrs r3, r2 - 8003526: 600b str r3, [r1, #0] + 8003324: 4b13 ldr r3, [pc, #76] ; (8003374 ) + 8003326: 681b ldr r3, [r3, #0] + 8003328: f023 0207 bic.w r2, r3, #7 + 800332c: 4911 ldr r1, [pc, #68] ; (8003374 ) + 800332e: 6b7b ldr r3, [r7, #52] ; 0x34 + 8003330: 4313 orrs r3, r2 + 8003332: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8003528: f7fe f9b8 bl 800189c - 800352c: 62b8 str r0, [r7, #40] ; 0x28 + 8003334: f7fe f9b8 bl 80016a8 + 8003338: 62b8 str r0, [r7, #40] ; 0x28 /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ while (__HAL_FLASH_GET_LATENCY() != latency) - 800352e: e008 b.n 8003542 + 800333a: e008 b.n 800334e { if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) - 8003530: f7fe f9b4 bl 800189c - 8003534: 4602 mov r2, r0 - 8003536: 6abb ldr r3, [r7, #40] ; 0x28 - 8003538: 1ad3 subs r3, r2, r3 - 800353a: 2b02 cmp r3, #2 - 800353c: d901 bls.n 8003542 + 800333c: f7fe f9b4 bl 80016a8 + 8003340: 4602 mov r2, r0 + 8003342: 6abb ldr r3, [r7, #40] ; 0x28 + 8003344: 1ad3 subs r3, r2, r3 + 8003346: 2b02 cmp r3, #2 + 8003348: d901 bls.n 800334e { return HAL_TIMEOUT; - 800353e: 2303 movs r3, #3 - 8003540: e007 b.n 8003552 + 800334a: 2303 movs r3, #3 + 800334c: e007 b.n 800335e while (__HAL_FLASH_GET_LATENCY() != latency) - 8003542: 4b09 ldr r3, [pc, #36] ; (8003568 ) - 8003544: 681b ldr r3, [r3, #0] - 8003546: f003 0307 and.w r3, r3, #7 - 800354a: 6b7a ldr r2, [r7, #52] ; 0x34 - 800354c: 429a cmp r2, r3 - 800354e: d1ef bne.n 8003530 + 800334e: 4b09 ldr r3, [pc, #36] ; (8003374 ) + 8003350: 681b ldr r3, [r3, #0] + 8003352: f003 0307 and.w r3, r3, #7 + 8003356: 6b7a ldr r2, [r7, #52] ; 0x34 + 8003358: 429a cmp r2, r3 + 800335a: d1ef bne.n 800333c } } return HAL_OK; - 8003550: 2300 movs r3, #0 -} - 8003552: 4618 mov r0, r3 - 8003554: 3738 adds r7, #56 ; 0x38 - 8003556: 46bd mov sp, r7 - 8003558: bd80 pop {r7, pc} - 800355a: bf00 nop - 800355c: 0800499c .word 0x0800499c - 8003560: 080049a4 .word 0x080049a4 - 8003564: 080049ac .word 0x080049ac - 8003568: 58004000 .word 0x58004000 - -0800356c : -{ - 800356c: b480 push {r7} - 800356e: af00 add r7, sp, #0 + 800335c: 2300 movs r3, #0 +} + 800335e: 4618 mov r0, r3 + 8003360: 3738 adds r7, #56 ; 0x38 + 8003362: 46bd mov sp, r7 + 8003364: bd80 pop {r7, pc} + 8003366: bf00 nop + 8003368: 0800479c .word 0x0800479c + 800336c: 080047a4 .word 0x080047a4 + 8003370: 080047ac .word 0x080047ac + 8003374: 58004000 .word 0x58004000 + +08003378 : +{ + 8003378: b480 push {r7} + 800337a: af00 add r7, sp, #0 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); - 8003570: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8003574: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8003578: f003 0302 and.w r3, r3, #2 - 800357c: 2b02 cmp r3, #2 - 800357e: d101 bne.n 8003584 - 8003580: 2301 movs r3, #1 - 8003582: e000 b.n 8003586 - 8003584: 2300 movs r3, #0 -} - 8003586: 4618 mov r0, r3 - 8003588: 46bd mov sp, r7 - 800358a: bc80 pop {r7} - 800358c: 4770 bx lr - -0800358e : -{ - 800358e: b480 push {r7} - 8003590: b083 sub sp, #12 - 8003592: af00 add r7, sp, #0 - 8003594: 6078 str r0, [r7, #4] + 800337c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003380: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003384: f003 0302 and.w r3, r3, #2 + 8003388: 2b02 cmp r3, #2 + 800338a: d101 bne.n 8003390 + 800338c: 2301 movs r3, #1 + 800338e: e000 b.n 8003392 + 8003390: 2300 movs r3, #0 +} + 8003392: 4618 mov r0, r3 + 8003394: 46bd mov sp, r7 + 8003396: bc80 pop {r7} + 8003398: 4770 bx lr + +0800339a : +{ + 800339a: b480 push {r7} + 800339c: b083 sub sp, #12 + 800339e: af00 add r7, sp, #0 + 80033a0: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFFU)); - 8003596: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800359a: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 - 800359e: 687b ldr r3, [r7, #4] - 80035a0: 0c1b lsrs r3, r3, #16 - 80035a2: 43db mvns r3, r3 - 80035a4: 401a ands r2, r3 - 80035a6: 687b ldr r3, [r7, #4] - 80035a8: b29b uxth r3, r3 - 80035aa: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 80035ae: 4313 orrs r3, r2 - 80035b0: f8c1 3088 str.w r3, [r1, #136] ; 0x88 -} - 80035b4: bf00 nop - 80035b6: 370c adds r7, #12 - 80035b8: 46bd mov sp, r7 - 80035ba: bc80 pop {r7} - 80035bc: 4770 bx lr - -080035be : -{ - 80035be: b480 push {r7} - 80035c0: b083 sub sp, #12 - 80035c2: af00 add r7, sp, #0 - 80035c4: 6078 str r0, [r7, #4] + 80033a2: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80033a6: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 + 80033aa: 687b ldr r3, [r7, #4] + 80033ac: 0c1b lsrs r3, r3, #16 + 80033ae: 43db mvns r3, r3 + 80033b0: 401a ands r2, r3 + 80033b2: 687b ldr r3, [r7, #4] + 80033b4: b29b uxth r3, r3 + 80033b6: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80033ba: 4313 orrs r3, r2 + 80033bc: f8c1 3088 str.w r3, [r1, #136] ; 0x88 +} + 80033c0: bf00 nop + 80033c2: 370c adds r7, #12 + 80033c4: 46bd mov sp, r7 + 80033c6: bc80 pop {r7} + 80033c8: 4770 bx lr + +080033ca : +{ + 80033ca: b480 push {r7} + 80033cc: b083 sub sp, #12 + 80033ce: af00 add r7, sp, #0 + 80033d0: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S2SEL, I2SxSource); - 80035c6: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80035ca: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 80035ce: f423 7240 bic.w r2, r3, #768 ; 0x300 - 80035d2: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 80035d6: 687b ldr r3, [r7, #4] - 80035d8: 4313 orrs r3, r2 - 80035da: f8c1 3088 str.w r3, [r1, #136] ; 0x88 -} - 80035de: bf00 nop - 80035e0: 370c adds r7, #12 - 80035e2: 46bd mov sp, r7 - 80035e4: bc80 pop {r7} - 80035e6: 4770 bx lr - -080035e8 : -{ - 80035e8: b480 push {r7} - 80035ea: b083 sub sp, #12 - 80035ec: af00 add r7, sp, #0 - 80035ee: 6078 str r0, [r7, #4] + 80033d2: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80033d6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 80033da: f423 7240 bic.w r2, r3, #768 ; 0x300 + 80033de: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80033e2: 687b ldr r3, [r7, #4] + 80033e4: 4313 orrs r3, r2 + 80033e6: f8c1 3088 str.w r3, [r1, #136] ; 0x88 +} + 80033ea: bf00 nop + 80033ec: 370c adds r7, #12 + 80033ee: 46bd mov sp, r7 + 80033f0: bc80 pop {r7} + 80033f2: 4770 bx lr + +080033f4 : +{ + 80033f4: b480 push {r7} + 80033f6: b083 sub sp, #12 + 80033f8: af00 add r7, sp, #0 + 80033fa: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); - 80035f0: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80035f4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 80035f8: f423 6240 bic.w r2, r3, #3072 ; 0xc00 - 80035fc: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 8003600: 687b ldr r3, [r7, #4] - 8003602: 4313 orrs r3, r2 - 8003604: f8c1 3088 str.w r3, [r1, #136] ; 0x88 -} - 8003608: bf00 nop - 800360a: 370c adds r7, #12 - 800360c: 46bd mov sp, r7 - 800360e: bc80 pop {r7} - 8003610: 4770 bx lr - -08003612 : -{ - 8003612: b480 push {r7} - 8003614: b083 sub sp, #12 - 8003616: af00 add r7, sp, #0 - 8003618: 6078 str r0, [r7, #4] + 80033fc: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003400: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8003404: f423 6240 bic.w r2, r3, #3072 ; 0xc00 + 8003408: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 800340c: 687b ldr r3, [r7, #4] + 800340e: 4313 orrs r3, r2 + 8003410: f8c1 3088 str.w r3, [r1, #136] ; 0x88 +} + 8003414: bf00 nop + 8003416: 370c adds r7, #12 + 8003418: 46bd mov sp, r7 + 800341a: bc80 pop {r7} + 800341c: 4770 bx lr + +0800341e : +{ + 800341e: b480 push {r7} + 8003420: b083 sub sp, #12 + 8003422: af00 add r7, sp, #0 + 8003424: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000U), ((I2CxSource << 4) & 0x000FF000U)); - 800361a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800361e: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 - 8003622: 687b ldr r3, [r7, #4] - 8003624: 091b lsrs r3, r3, #4 - 8003626: f403 237f and.w r3, r3, #1044480 ; 0xff000 - 800362a: 43db mvns r3, r3 - 800362c: 401a ands r2, r3 - 800362e: 687b ldr r3, [r7, #4] - 8003630: 011b lsls r3, r3, #4 - 8003632: f403 237f and.w r3, r3, #1044480 ; 0xff000 - 8003636: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 800363a: 4313 orrs r3, r2 - 800363c: f8c1 3088 str.w r3, [r1, #136] ; 0x88 -} - 8003640: bf00 nop - 8003642: 370c adds r7, #12 - 8003644: 46bd mov sp, r7 - 8003646: bc80 pop {r7} - 8003648: 4770 bx lr - -0800364a : -{ - 800364a: b480 push {r7} - 800364c: b083 sub sp, #12 - 800364e: af00 add r7, sp, #0 - 8003650: 6078 str r0, [r7, #4] + 8003426: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800342a: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 + 800342e: 687b ldr r3, [r7, #4] + 8003430: 091b lsrs r3, r3, #4 + 8003432: f403 237f and.w r3, r3, #1044480 ; 0xff000 + 8003436: 43db mvns r3, r3 + 8003438: 401a ands r2, r3 + 800343a: 687b ldr r3, [r7, #4] + 800343c: 011b lsls r3, r3, #4 + 800343e: f403 237f and.w r3, r3, #1044480 ; 0xff000 + 8003442: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8003446: 4313 orrs r3, r2 + 8003448: f8c1 3088 str.w r3, [r1, #136] ; 0x88 +} + 800344c: bf00 nop + 800344e: 370c adds r7, #12 + 8003450: 46bd mov sp, r7 + 8003452: bc80 pop {r7} + 8003454: 4770 bx lr + +08003456 : +{ + 8003456: b480 push {r7} + 8003458: b083 sub sp, #12 + 800345a: af00 add r7, sp, #0 + 800345c: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16)); - 8003652: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8003656: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 - 800365a: 687b ldr r3, [r7, #4] - 800365c: 0c1b lsrs r3, r3, #16 - 800365e: 041b lsls r3, r3, #16 - 8003660: 43db mvns r3, r3 - 8003662: 401a ands r2, r3 - 8003664: 687b ldr r3, [r7, #4] - 8003666: 041b lsls r3, r3, #16 - 8003668: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 800366c: 4313 orrs r3, r2 - 800366e: f8c1 3088 str.w r3, [r1, #136] ; 0x88 -} - 8003672: bf00 nop - 8003674: 370c adds r7, #12 - 8003676: 46bd mov sp, r7 - 8003678: bc80 pop {r7} - 800367a: 4770 bx lr - -0800367c : -{ - 800367c: b480 push {r7} - 800367e: b083 sub sp, #12 - 8003680: af00 add r7, sp, #0 - 8003682: 6078 str r0, [r7, #4] + 800345e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003462: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 + 8003466: 687b ldr r3, [r7, #4] + 8003468: 0c1b lsrs r3, r3, #16 + 800346a: 041b lsls r3, r3, #16 + 800346c: 43db mvns r3, r3 + 800346e: 401a ands r2, r3 + 8003470: 687b ldr r3, [r7, #4] + 8003472: 041b lsls r3, r3, #16 + 8003474: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8003478: 4313 orrs r3, r2 + 800347a: f8c1 3088 str.w r3, [r1, #136] ; 0x88 +} + 800347e: bf00 nop + 8003480: 370c adds r7, #12 + 8003482: 46bd mov sp, r7 + 8003484: bc80 pop {r7} + 8003486: 4770 bx lr + +08003488 : +{ + 8003488: b480 push {r7} + 800348a: b083 sub sp, #12 + 800348c: af00 add r7, sp, #0 + 800348e: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource); - 8003684: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8003688: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 800368c: f023 4240 bic.w r2, r3, #3221225472 ; 0xc0000000 - 8003690: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 8003694: 687b ldr r3, [r7, #4] - 8003696: 4313 orrs r3, r2 - 8003698: f8c1 3088 str.w r3, [r1, #136] ; 0x88 -} - 800369c: bf00 nop - 800369e: 370c adds r7, #12 - 80036a0: 46bd mov sp, r7 - 80036a2: bc80 pop {r7} - 80036a4: 4770 bx lr - -080036a6 : -{ - 80036a6: b480 push {r7} - 80036a8: b083 sub sp, #12 - 80036aa: af00 add r7, sp, #0 - 80036ac: 6078 str r0, [r7, #4] + 8003490: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003494: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8003498: f023 4240 bic.w r2, r3, #3221225472 ; 0xc0000000 + 800349c: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80034a0: 687b ldr r3, [r7, #4] + 80034a2: 4313 orrs r3, r2 + 80034a4: f8c1 3088 str.w r3, [r1, #136] ; 0x88 +} + 80034a8: bf00 nop + 80034aa: 370c adds r7, #12 + 80034ac: 46bd mov sp, r7 + 80034ae: bc80 pop {r7} + 80034b0: 4770 bx lr + +080034b2 : +{ + 80034b2: b480 push {r7} + 80034b4: b083 sub sp, #12 + 80034b6: af00 add r7, sp, #0 + 80034b8: 6078 str r0, [r7, #4] MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); - 80036ae: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80036b2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 80036b6: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000 - 80036ba: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 80036be: 687b ldr r3, [r7, #4] - 80036c0: 4313 orrs r3, r2 - 80036c2: f8c1 3088 str.w r3, [r1, #136] ; 0x88 -} - 80036c6: bf00 nop - 80036c8: 370c adds r7, #12 - 80036ca: 46bd mov sp, r7 - 80036cc: bc80 pop {r7} - 80036ce: 4770 bx lr - -080036d0 : -{ - 80036d0: b480 push {r7} - 80036d2: b083 sub sp, #12 - 80036d4: af00 add r7, sp, #0 - 80036d6: 6078 str r0, [r7, #4] + 80034ba: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80034be: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 80034c2: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000 + 80034c6: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80034ca: 687b ldr r3, [r7, #4] + 80034cc: 4313 orrs r3, r2 + 80034ce: f8c1 3088 str.w r3, [r1, #136] ; 0x88 +} + 80034d2: bf00 nop + 80034d4: 370c adds r7, #12 + 80034d6: 46bd mov sp, r7 + 80034d8: bc80 pop {r7} + 80034da: 4770 bx lr + +080034dc : +{ + 80034dc: b480 push {r7} + 80034de: b083 sub sp, #12 + 80034e0: af00 add r7, sp, #0 + 80034e2: 6078 str r0, [r7, #4] MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); - 80036d8: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80036dc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 80036e0: f423 7240 bic.w r2, r3, #768 ; 0x300 - 80036e4: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 - 80036e8: 687b ldr r3, [r7, #4] - 80036ea: 4313 orrs r3, r2 - 80036ec: f8c1 3090 str.w r3, [r1, #144] ; 0x90 -} - 80036f0: bf00 nop - 80036f2: 370c adds r7, #12 - 80036f4: 46bd mov sp, r7 - 80036f6: bc80 pop {r7} - 80036f8: 4770 bx lr - -080036fa : -{ - 80036fa: b480 push {r7} - 80036fc: af00 add r7, sp, #0 + 80034e4: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80034e8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80034ec: f423 7240 bic.w r2, r3, #768 ; 0x300 + 80034f0: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80034f4: 687b ldr r3, [r7, #4] + 80034f6: 4313 orrs r3, r2 + 80034f8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 +} + 80034fc: bf00 nop + 80034fe: 370c adds r7, #12 + 8003500: 46bd mov sp, r7 + 8003502: bc80 pop {r7} + 8003504: 4770 bx lr + +08003506 : +{ + 8003506: b480 push {r7} + 8003508: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); - 80036fe: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8003702: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8003706: f403 7340 and.w r3, r3, #768 ; 0x300 + 800350a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800350e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003512: f403 7340 and.w r3, r3, #768 ; 0x300 } - 800370a: 4618 mov r0, r3 - 800370c: 46bd mov sp, r7 - 800370e: bc80 pop {r7} - 8003710: 4770 bx lr + 8003516: 4618 mov r0, r3 + 8003518: 46bd mov sp, r7 + 800351a: bc80 pop {r7} + 800351c: 4770 bx lr -08003712 : +0800351e : { - 8003712: b480 push {r7} - 8003714: af00 add r7, sp, #0 + 800351e: b480 push {r7} + 8003520: af00 add r7, sp, #0 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); - 8003716: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800371a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 800371e: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 8003722: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 8003726: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + 8003522: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003526: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800352a: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 800352e: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8003532: f8c2 3090 str.w r3, [r2, #144] ; 0x90 } - 800372a: bf00 nop - 800372c: 46bd mov sp, r7 - 800372e: bc80 pop {r7} - 8003730: 4770 bx lr + 8003536: bf00 nop + 8003538: 46bd mov sp, r7 + 800353a: bc80 pop {r7} + 800353c: 4770 bx lr -08003732 : +0800353e : { - 8003732: b480 push {r7} - 8003734: af00 add r7, sp, #0 + 800353e: b480 push {r7} + 8003540: af00 add r7, sp, #0 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); - 8003736: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800373a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 800373e: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 8003742: f423 3380 bic.w r3, r3, #65536 ; 0x10000 - 8003746: f8c2 3090 str.w r3, [r2, #144] ; 0x90 -} - 800374a: bf00 nop - 800374c: 46bd mov sp, r7 - 800374e: bc80 pop {r7} - 8003750: 4770 bx lr + 8003542: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003546: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800354a: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 800354e: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8003552: f8c2 3090 str.w r3, [r2, #144] ; 0x90 +} + 8003556: bf00 nop + 8003558: 46bd mov sp, r7 + 800355a: bc80 pop {r7} + 800355c: 4770 bx lr ... -08003754 : +08003560 : * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - 8003754: b580 push {r7, lr} - 8003756: b086 sub sp, #24 - 8003758: af00 add r7, sp, #0 - 800375a: 6078 str r0, [r7, #4] + 8003560: b580 push {r7, lr} + 8003562: b086 sub sp, #24 + 8003564: af00 add r7, sp, #0 + 8003566: 6078 str r0, [r7, #4] uint32_t tmpregister = 0; - 800375c: 2300 movs r3, #0 - 800375e: 617b str r3, [r7, #20] + 8003568: 2300 movs r3, #0 + 800356a: 617b str r3, [r7, #20] uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ - 8003760: 2300 movs r3, #0 - 8003762: 74fb strb r3, [r7, #19] + 800356c: 2300 movs r3, #0 + 800356e: 74fb strb r3, [r7, #19] HAL_StatusTypeDef status = HAL_OK; /* Final status */ - 8003764: 2300 movs r3, #0 - 8003766: 74bb strb r3, [r7, #18] + 8003570: 2300 movs r3, #0 + 8003572: 74bb strb r3, [r7, #18] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*-------------------------- RTC clock source configuration ----------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) - 8003768: 687b ldr r3, [r7, #4] - 800376a: 681b ldr r3, [r3, #0] - 800376c: f403 3380 and.w r3, r3, #65536 ; 0x10000 - 8003770: 2b00 cmp r3, #0 - 8003772: d058 beq.n 8003826 + 8003574: 687b ldr r3, [r7, #4] + 8003576: 681b ldr r3, [r3, #0] + 8003578: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 800357c: 2b00 cmp r3, #0 + 800357e: d058 beq.n 8003632 /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable write access to Backup domain */ HAL_PWR_EnableBkUpAccess(); - 8003774: f7fe fe20 bl 80023b8 + 8003580: f7fe fe20 bl 80021c4 /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - 8003778: f7fe f890 bl 800189c - 800377c: 60f8 str r0, [r7, #12] + 8003584: f7fe f890 bl 80016a8 + 8003588: 60f8 str r0, [r7, #12] while (!(READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP))) - 800377e: e009 b.n 8003794 + 800358a: e009 b.n 80035a0 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 8003780: f7fe f88c bl 800189c - 8003784: 4602 mov r2, r0 - 8003786: 68fb ldr r3, [r7, #12] - 8003788: 1ad3 subs r3, r2, r3 - 800378a: 2b02 cmp r3, #2 - 800378c: d902 bls.n 8003794 + 800358c: f7fe f88c bl 80016a8 + 8003590: 4602 mov r2, r0 + 8003592: 68fb ldr r3, [r7, #12] + 8003594: 1ad3 subs r3, r2, r3 + 8003596: 2b02 cmp r3, #2 + 8003598: d902 bls.n 80035a0 { ret = HAL_TIMEOUT; - 800378e: 2303 movs r3, #3 - 8003790: 74fb strb r3, [r7, #19] + 800359a: 2303 movs r3, #3 + 800359c: 74fb strb r3, [r7, #19] break; - 8003792: e006 b.n 80037a2 + 800359e: e006 b.n 80035ae while (!(READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP))) - 8003794: 4b7b ldr r3, [pc, #492] ; (8003984 ) - 8003796: 681b ldr r3, [r3, #0] - 8003798: f403 7380 and.w r3, r3, #256 ; 0x100 - 800379c: f5b3 7f80 cmp.w r3, #256 ; 0x100 - 80037a0: d1ee bne.n 8003780 + 80035a0: 4b7b ldr r3, [pc, #492] ; (8003790 ) + 80035a2: 681b ldr r3, [r3, #0] + 80035a4: f403 7380 and.w r3, r3, #256 ; 0x100 + 80035a8: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 80035ac: d1ee bne.n 800358c } } if (ret == HAL_OK) - 80037a2: 7cfb ldrb r3, [r7, #19] - 80037a4: 2b00 cmp r3, #0 - 80037a6: d13c bne.n 8003822 + 80035ae: 7cfb ldrb r3, [r7, #19] + 80035b0: 2b00 cmp r3, #0 + 80035b2: d13c bne.n 800362e { /* Reset the Backup domain only if the RTC Clock source selection is modified */ if (LL_RCC_GetRTCClockSource() != PeriphClkInit->RTCClockSelection) - 80037a8: f7ff ffa7 bl 80036fa - 80037ac: 4602 mov r2, r0 - 80037ae: 687b ldr r3, [r7, #4] - 80037b0: 6b5b ldr r3, [r3, #52] ; 0x34 - 80037b2: 429a cmp r2, r3 - 80037b4: d00f beq.n 80037d6 + 80035b4: f7ff ffa7 bl 8003506 + 80035b8: 4602 mov r2, r0 + 80035ba: 687b ldr r3, [r7, #4] + 80035bc: 6b5b ldr r3, [r3, #52] ; 0x34 + 80035be: 429a cmp r2, r3 + 80035c0: d00f beq.n 80035e2 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); - 80037b6: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 80037ba: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 80037be: f423 7340 bic.w r3, r3, #768 ; 0x300 - 80037c2: 617b str r3, [r7, #20] + 80035c2: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80035c6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80035ca: f423 7340 bic.w r3, r3, #768 ; 0x300 + 80035ce: 617b str r3, [r7, #20] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); - 80037c4: f7ff ffa5 bl 8003712 + 80035d0: f7ff ffa5 bl 800351e __HAL_RCC_BACKUPRESET_RELEASE(); - 80037c8: f7ff ffb3 bl 8003732 + 80035d4: f7ff ffb3 bl 800353e /* Restore the Content of BDCR register */ RCC->BDCR = tmpregister; - 80037cc: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 80037d0: 697b ldr r3, [r7, #20] - 80037d2: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + 80035d8: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 80035dc: 697b ldr r3, [r7, #20] + 80035de: f8c2 3090 str.w r3, [r2, #144] ; 0x90 } /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSERDY)) - 80037d6: 697b ldr r3, [r7, #20] - 80037d8: f003 0302 and.w r3, r3, #2 - 80037dc: 2b00 cmp r3, #0 - 80037de: d014 beq.n 800380a + 80035e2: 697b ldr r3, [r7, #20] + 80035e4: f003 0302 and.w r3, r3, #2 + 80035e8: 2b00 cmp r3, #0 + 80035ea: d014 beq.n 8003616 { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 80037e0: f7fe f85c bl 800189c - 80037e4: 60f8 str r0, [r7, #12] + 80035ec: f7fe f85c bl 80016a8 + 80035f0: 60f8 str r0, [r7, #12] /* Wait till LSE is ready */ while (LL_RCC_LSE_IsReady() != 1U) - 80037e6: e00b b.n 8003800 + 80035f2: e00b b.n 800360c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 80037e8: f7fe f858 bl 800189c - 80037ec: 4602 mov r2, r0 - 80037ee: 68fb ldr r3, [r7, #12] - 80037f0: 1ad3 subs r3, r2, r3 - 80037f2: f241 3288 movw r2, #5000 ; 0x1388 - 80037f6: 4293 cmp r3, r2 - 80037f8: d902 bls.n 8003800 + 80035f4: f7fe f858 bl 80016a8 + 80035f8: 4602 mov r2, r0 + 80035fa: 68fb ldr r3, [r7, #12] + 80035fc: 1ad3 subs r3, r2, r3 + 80035fe: f241 3288 movw r2, #5000 ; 0x1388 + 8003602: 4293 cmp r3, r2 + 8003604: d902 bls.n 800360c { ret = HAL_TIMEOUT; - 80037fa: 2303 movs r3, #3 - 80037fc: 74fb strb r3, [r7, #19] + 8003606: 2303 movs r3, #3 + 8003608: 74fb strb r3, [r7, #19] break; - 80037fe: e004 b.n 800380a + 800360a: e004 b.n 8003616 while (LL_RCC_LSE_IsReady() != 1U) - 8003800: f7ff feb4 bl 800356c - 8003804: 4603 mov r3, r0 - 8003806: 2b01 cmp r3, #1 - 8003808: d1ee bne.n 80037e8 + 800360c: f7ff feb4 bl 8003378 + 8003610: 4603 mov r3, r0 + 8003612: 2b01 cmp r3, #1 + 8003614: d1ee bne.n 80035f4 } } } if (ret == HAL_OK) - 800380a: 7cfb ldrb r3, [r7, #19] - 800380c: 2b00 cmp r3, #0 - 800380e: d105 bne.n 800381c + 8003616: 7cfb ldrb r3, [r7, #19] + 8003618: 2b00 cmp r3, #0 + 800361a: d105 bne.n 8003628 { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - 8003810: 687b ldr r3, [r7, #4] - 8003812: 6b5b ldr r3, [r3, #52] ; 0x34 - 8003814: 4618 mov r0, r3 - 8003816: f7ff ff5b bl 80036d0 - 800381a: e004 b.n 8003826 + 800361c: 687b ldr r3, [r7, #4] + 800361e: 6b5b ldr r3, [r3, #52] ; 0x34 + 8003620: 4618 mov r0, r3 + 8003622: f7ff ff5b bl 80034dc + 8003626: e004 b.n 8003632 } else { /* set overall return value */ status = ret; - 800381c: 7cfb ldrb r3, [r7, #19] - 800381e: 74bb strb r3, [r7, #18] - 8003820: e001 b.n 8003826 + 8003628: 7cfb ldrb r3, [r7, #19] + 800362a: 74bb strb r3, [r7, #18] + 800362c: e001 b.n 8003632 } } else { /* set overall return value */ status = ret; - 8003822: 7cfb ldrb r3, [r7, #19] - 8003824: 74bb strb r3, [r7, #18] + 800362e: 7cfb ldrb r3, [r7, #19] + 8003630: 74bb strb r3, [r7, #18] } } /*-------------------- USART1 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) - 8003826: 687b ldr r3, [r7, #4] - 8003828: 681b ldr r3, [r3, #0] - 800382a: f003 0301 and.w r3, r3, #1 - 800382e: 2b00 cmp r3, #0 - 8003830: d004 beq.n 800383c + 8003632: 687b ldr r3, [r7, #4] + 8003634: 681b ldr r3, [r3, #0] + 8003636: f003 0301 and.w r3, r3, #1 + 800363a: 2b00 cmp r3, #0 + 800363c: d004 beq.n 8003648 { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); - 8003832: 687b ldr r3, [r7, #4] - 8003834: 685b ldr r3, [r3, #4] - 8003836: 4618 mov r0, r3 - 8003838: f7ff fea9 bl 800358e + 800363e: 687b ldr r3, [r7, #4] + 8003640: 685b ldr r3, [r3, #4] + 8003642: 4618 mov r0, r3 + 8003644: f7ff fea9 bl 800339a } /*-------------------- USART2 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) - 800383c: 687b ldr r3, [r7, #4] - 800383e: 681b ldr r3, [r3, #0] - 8003840: f003 0302 and.w r3, r3, #2 - 8003844: 2b00 cmp r3, #0 - 8003846: d004 beq.n 8003852 + 8003648: 687b ldr r3, [r7, #4] + 800364a: 681b ldr r3, [r3, #0] + 800364c: f003 0302 and.w r3, r3, #2 + 8003650: 2b00 cmp r3, #0 + 8003652: d004 beq.n 800365e { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); - 8003848: 687b ldr r3, [r7, #4] - 800384a: 689b ldr r3, [r3, #8] - 800384c: 4618 mov r0, r3 - 800384e: f7ff fe9e bl 800358e + 8003654: 687b ldr r3, [r7, #4] + 8003656: 689b ldr r3, [r3, #8] + 8003658: 4618 mov r0, r3 + 800365a: f7ff fe9e bl 800339a } /*-------------------- LPUART1 clock source configuration ------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) - 8003852: 687b ldr r3, [r7, #4] - 8003854: 681b ldr r3, [r3, #0] - 8003856: f003 0320 and.w r3, r3, #32 - 800385a: 2b00 cmp r3, #0 - 800385c: d004 beq.n 8003868 + 800365e: 687b ldr r3, [r7, #4] + 8003660: 681b ldr r3, [r3, #0] + 8003662: f003 0320 and.w r3, r3, #32 + 8003666: 2b00 cmp r3, #0 + 8003668: d004 beq.n 8003674 { /* Check the parameters */ assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); /* Configure the LPUAR1 clock source */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); - 800385e: 687b ldr r3, [r7, #4] - 8003860: 691b ldr r3, [r3, #16] - 8003862: 4618 mov r0, r3 - 8003864: f7ff fec0 bl 80035e8 + 800366a: 687b ldr r3, [r7, #4] + 800366c: 691b ldr r3, [r3, #16] + 800366e: 4618 mov r0, r3 + 8003670: f7ff fec0 bl 80033f4 } /*-------------------- LPTIM1 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) - 8003868: 687b ldr r3, [r7, #4] - 800386a: 681b ldr r3, [r3, #0] - 800386c: f403 7300 and.w r3, r3, #512 ; 0x200 - 8003870: 2b00 cmp r3, #0 - 8003872: d004 beq.n 800387e + 8003674: 687b ldr r3, [r7, #4] + 8003676: 681b ldr r3, [r3, #0] + 8003678: f403 7300 and.w r3, r3, #512 ; 0x200 + 800367c: 2b00 cmp r3, #0 + 800367e: d004 beq.n 800368a { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); /* Configure the LPTIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); - 8003874: 687b ldr r3, [r7, #4] - 8003876: 6a1b ldr r3, [r3, #32] - 8003878: 4618 mov r0, r3 - 800387a: f7ff fee6 bl 800364a + 8003680: 687b ldr r3, [r7, #4] + 8003682: 6a1b ldr r3, [r3, #32] + 8003684: 4618 mov r0, r3 + 8003686: f7ff fee6 bl 8003456 } /*-------------------- LPTIM2 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) - 800387e: 687b ldr r3, [r7, #4] - 8003880: 681b ldr r3, [r3, #0] - 8003882: f403 6380 and.w r3, r3, #1024 ; 0x400 - 8003886: 2b00 cmp r3, #0 - 8003888: d004 beq.n 8003894 + 800368a: 687b ldr r3, [r7, #4] + 800368c: 681b ldr r3, [r3, #0] + 800368e: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8003692: 2b00 cmp r3, #0 + 8003694: d004 beq.n 80036a0 { /* Check the parameters */ assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection)); /* Configure the LPTIM2 clock source */ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); - 800388a: 687b ldr r3, [r7, #4] - 800388c: 6a5b ldr r3, [r3, #36] ; 0x24 - 800388e: 4618 mov r0, r3 - 8003890: f7ff fedb bl 800364a + 8003696: 687b ldr r3, [r7, #4] + 8003698: 6a5b ldr r3, [r3, #36] ; 0x24 + 800369a: 4618 mov r0, r3 + 800369c: f7ff fedb bl 8003456 } /*-------------------- LPTIM3 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM3) == (RCC_PERIPHCLK_LPTIM3)) - 8003894: 687b ldr r3, [r7, #4] - 8003896: 681b ldr r3, [r3, #0] - 8003898: f403 6300 and.w r3, r3, #2048 ; 0x800 - 800389c: 2b00 cmp r3, #0 - 800389e: d004 beq.n 80038aa + 80036a0: 687b ldr r3, [r7, #4] + 80036a2: 681b ldr r3, [r3, #0] + 80036a4: f403 6300 and.w r3, r3, #2048 ; 0x800 + 80036a8: 2b00 cmp r3, #0 + 80036aa: d004 beq.n 80036b6 { /* Check the parameters */ assert_param(IS_RCC_LPTIM3CLKSOURCE(PeriphClkInit->Lptim3ClockSelection)); /* Configure the LPTIM3 clock source */ __HAL_RCC_LPTIM3_CONFIG(PeriphClkInit->Lptim3ClockSelection); - 80038a0: 687b ldr r3, [r7, #4] - 80038a2: 6a9b ldr r3, [r3, #40] ; 0x28 - 80038a4: 4618 mov r0, r3 - 80038a6: f7ff fed0 bl 800364a + 80036ac: 687b ldr r3, [r7, #4] + 80036ae: 6a9b ldr r3, [r3, #40] ; 0x28 + 80036b0: 4618 mov r0, r3 + 80036b2: f7ff fed0 bl 8003456 } /*-------------------- I2C1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) - 80038aa: 687b ldr r3, [r7, #4] - 80038ac: 681b ldr r3, [r3, #0] - 80038ae: f003 0340 and.w r3, r3, #64 ; 0x40 - 80038b2: 2b00 cmp r3, #0 - 80038b4: d004 beq.n 80038c0 + 80036b6: 687b ldr r3, [r7, #4] + 80036b8: 681b ldr r3, [r3, #0] + 80036ba: f003 0340 and.w r3, r3, #64 ; 0x40 + 80036be: 2b00 cmp r3, #0 + 80036c0: d004 beq.n 80036cc { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); - 80038b6: 687b ldr r3, [r7, #4] - 80038b8: 695b ldr r3, [r3, #20] - 80038ba: 4618 mov r0, r3 - 80038bc: f7ff fea9 bl 8003612 + 80036c2: 687b ldr r3, [r7, #4] + 80036c4: 695b ldr r3, [r3, #20] + 80036c6: 4618 mov r0, r3 + 80036c8: f7ff fea9 bl 800341e } /*-------------------- I2C2 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) - 80038c0: 687b ldr r3, [r7, #4] - 80038c2: 681b ldr r3, [r3, #0] - 80038c4: f003 0380 and.w r3, r3, #128 ; 0x80 - 80038c8: 2b00 cmp r3, #0 - 80038ca: d004 beq.n 80038d6 + 80036cc: 687b ldr r3, [r7, #4] + 80036ce: 681b ldr r3, [r3, #0] + 80036d0: f003 0380 and.w r3, r3, #128 ; 0x80 + 80036d4: 2b00 cmp r3, #0 + 80036d6: d004 beq.n 80036e2 { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); - 80038cc: 687b ldr r3, [r7, #4] - 80038ce: 699b ldr r3, [r3, #24] - 80038d0: 4618 mov r0, r3 - 80038d2: f7ff fe9e bl 8003612 + 80036d8: 687b ldr r3, [r7, #4] + 80036da: 699b ldr r3, [r3, #24] + 80036dc: 4618 mov r0, r3 + 80036de: f7ff fe9e bl 800341e } /*-------------------- I2C3 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) - 80038d6: 687b ldr r3, [r7, #4] - 80038d8: 681b ldr r3, [r3, #0] - 80038da: f403 7380 and.w r3, r3, #256 ; 0x100 - 80038de: 2b00 cmp r3, #0 - 80038e0: d004 beq.n 80038ec + 80036e2: 687b ldr r3, [r7, #4] + 80036e4: 681b ldr r3, [r3, #0] + 80036e6: f403 7380 and.w r3, r3, #256 ; 0x100 + 80036ea: 2b00 cmp r3, #0 + 80036ec: d004 beq.n 80036f8 { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); - 80038e2: 687b ldr r3, [r7, #4] - 80038e4: 69db ldr r3, [r3, #28] - 80038e6: 4618 mov r0, r3 - 80038e8: f7ff fe93 bl 8003612 + 80036ee: 687b ldr r3, [r7, #4] + 80036f0: 69db ldr r3, [r3, #28] + 80036f2: 4618 mov r0, r3 + 80036f4: f7ff fe93 bl 800341e } /*-------------------- I2S2 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == (RCC_PERIPHCLK_I2S2)) - 80038ec: 687b ldr r3, [r7, #4] - 80038ee: 681b ldr r3, [r3, #0] - 80038f0: f003 0310 and.w r3, r3, #16 - 80038f4: 2b00 cmp r3, #0 - 80038f6: d011 beq.n 800391c + 80036f8: 687b ldr r3, [r7, #4] + 80036fa: 681b ldr r3, [r3, #0] + 80036fc: f003 0310 and.w r3, r3, #16 + 8003700: 2b00 cmp r3, #0 + 8003702: d011 beq.n 8003728 { /* Check the parameters */ assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); /* Configure the I2S2 clock source */ __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); - 80038f8: 687b ldr r3, [r7, #4] - 80038fa: 68db ldr r3, [r3, #12] - 80038fc: 4618 mov r0, r3 - 80038fe: f7ff fe5e bl 80035be + 8003704: 687b ldr r3, [r7, #4] + 8003706: 68db ldr r3, [r3, #12] + 8003708: 4618 mov r0, r3 + 800370a: f7ff fe5e bl 80033ca if (PeriphClkInit->I2s2ClockSelection == RCC_I2S2CLKSOURCE_PLL) - 8003902: 687b ldr r3, [r7, #4] - 8003904: 68db ldr r3, [r3, #12] - 8003906: f5b3 7f80 cmp.w r3, #256 ; 0x100 - 800390a: d107 bne.n 800391c + 800370e: 687b ldr r3, [r7, #4] + 8003710: 68db ldr r3, [r3, #12] + 8003712: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8003716: d107 bne.n 8003728 { /* Enable RCC_PLL_I2S2CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_I2S2CLK); - 800390c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8003910: 68db ldr r3, [r3, #12] - 8003912: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 8003916: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 - 800391a: 60d3 str r3, [r2, #12] + 8003718: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800371c: 68db ldr r3, [r3, #12] + 800371e: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8003722: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 8003726: 60d3 str r3, [r2, #12] } } /*-------------------- RNG clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) - 800391c: 687b ldr r3, [r7, #4] - 800391e: 681b ldr r3, [r3, #0] - 8003920: f403 4300 and.w r3, r3, #32768 ; 0x8000 - 8003924: 2b00 cmp r3, #0 - 8003926: d010 beq.n 800394a + 8003728: 687b ldr r3, [r7, #4] + 800372a: 681b ldr r3, [r3, #0] + 800372c: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 8003730: 2b00 cmp r3, #0 + 8003732: d010 beq.n 8003756 { assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); - 8003928: 687b ldr r3, [r7, #4] - 800392a: 6b1b ldr r3, [r3, #48] ; 0x30 - 800392c: 4618 mov r0, r3 - 800392e: f7ff fea5 bl 800367c + 8003734: 687b ldr r3, [r7, #4] + 8003736: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003738: 4618 mov r0, r3 + 800373a: f7ff fea5 bl 8003488 if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) - 8003932: 687b ldr r3, [r7, #4] - 8003934: 6b1b ldr r3, [r3, #48] ; 0x30 - 8003936: 2b00 cmp r3, #0 - 8003938: d107 bne.n 800394a + 800373e: 687b ldr r3, [r7, #4] + 8003740: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003742: 2b00 cmp r3, #0 + 8003744: d107 bne.n 8003756 { /* Enable RCC_PLL_RNGCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_RNGCLK); - 800393a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800393e: 68db ldr r3, [r3, #12] - 8003940: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 8003944: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 - 8003948: 60d3 str r3, [r2, #12] + 8003746: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800374a: 68db ldr r3, [r3, #12] + 800374c: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8003750: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 8003754: 60d3 str r3, [r2, #12] } } /*-------------------- ADC clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) - 800394a: 687b ldr r3, [r7, #4] - 800394c: 681b ldr r3, [r3, #0] - 800394e: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 8003952: 2b00 cmp r3, #0 - 8003954: d011 beq.n 800397a + 8003756: 687b ldr r3, [r7, #4] + 8003758: 681b ldr r3, [r3, #0] + 800375a: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800375e: 2b00 cmp r3, #0 + 8003760: d011 beq.n 8003786 { /* Check the parameters */ assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); /* Configure the ADC interface clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); - 8003956: 687b ldr r3, [r7, #4] - 8003958: 6adb ldr r3, [r3, #44] ; 0x2c - 800395a: 4618 mov r0, r3 - 800395c: f7ff fea3 bl 80036a6 + 8003762: 687b ldr r3, [r7, #4] + 8003764: 6adb ldr r3, [r3, #44] ; 0x2c + 8003766: 4618 mov r0, r3 + 8003768: f7ff fea3 bl 80034b2 if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLL) - 8003960: 687b ldr r3, [r7, #4] - 8003962: 6adb ldr r3, [r3, #44] ; 0x2c - 8003964: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 - 8003968: d107 bne.n 800397a + 800376c: 687b ldr r3, [r7, #4] + 800376e: 6adb ldr r3, [r3, #44] ; 0x2c + 8003770: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 8003774: d107 bne.n 8003786 { /* Enable RCC_PLL_RNGCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); - 800396a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 800396e: 68db ldr r3, [r3, #12] - 8003970: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 8003974: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 8003978: 60d3 str r3, [r2, #12] + 8003776: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800377a: 68db ldr r3, [r3, #12] + 800377c: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8003780: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8003784: 60d3 str r3, [r2, #12] } } return status; - 800397a: 7cbb ldrb r3, [r7, #18] + 8003786: 7cbb ldrb r3, [r7, #18] } - 800397c: 4618 mov r0, r3 - 800397e: 3718 adds r7, #24 - 8003980: 46bd mov sp, r7 - 8003982: bd80 pop {r7, pc} - 8003984: 58000400 .word 0x58000400 + 8003788: 4618 mov r0, r3 + 800378a: 3718 adds r7, #24 + 800378c: 46bd mov sp, r7 + 800378e: bd80 pop {r7, pc} + 8003790: 58000400 .word 0x58000400 -08003988 : +08003794 : * @arg @ref LL_PWR_RADIO_BUSY_TRIGGER_NONE * @arg @ref LL_PWR_RADIO_BUSY_TRIGGER_WU_IT * @retval None */ __STATIC_INLINE void LL_PWR_SetRadioBusyTrigger(uint32_t RadioBusyTrigger) { - 8003988: b480 push {r7} - 800398a: b083 sub sp, #12 - 800398c: af00 add r7, sp, #0 - 800398e: 6078 str r0, [r7, #4] + 8003794: b480 push {r7} + 8003796: b083 sub sp, #12 + 8003798: af00 add r7, sp, #0 + 800379a: 6078 str r0, [r7, #4] MODIFY_REG(PWR->CR3, PWR_CR3_EWRFBUSY, RadioBusyTrigger); - 8003990: 4b06 ldr r3, [pc, #24] ; (80039ac ) - 8003992: 689b ldr r3, [r3, #8] - 8003994: f423 6200 bic.w r2, r3, #2048 ; 0x800 - 8003998: 4904 ldr r1, [pc, #16] ; (80039ac ) - 800399a: 687b ldr r3, [r7, #4] - 800399c: 4313 orrs r3, r2 - 800399e: 608b str r3, [r1, #8] -} - 80039a0: bf00 nop - 80039a2: 370c adds r7, #12 - 80039a4: 46bd mov sp, r7 - 80039a6: bc80 pop {r7} - 80039a8: 4770 bx lr - 80039aa: bf00 nop - 80039ac: 58000400 .word 0x58000400 - -080039b0 : + 800379c: 4b06 ldr r3, [pc, #24] ; (80037b8 ) + 800379e: 689b ldr r3, [r3, #8] + 80037a0: f423 6200 bic.w r2, r3, #2048 ; 0x800 + 80037a4: 4904 ldr r1, [pc, #16] ; (80037b8 ) + 80037a6: 687b ldr r3, [r7, #4] + 80037a8: 4313 orrs r3, r2 + 80037aa: 608b str r3, [r1, #8] +} + 80037ac: bf00 nop + 80037ae: 370c adds r7, #12 + 80037b0: 46bd mov sp, r7 + 80037b2: bc80 pop {r7} + 80037b4: 4770 bx lr + 80037b6: bf00 nop + 80037b8: 58000400 .word 0x58000400 + +080037bc : * @brief Set sub-GHz radio SPI NSS at logical level high. * @rmtoll SUBGHZSPICR NSS LL_PWR_UnselectSUBGHZSPI_NSS * @retval None */ __STATIC_INLINE void LL_PWR_UnselectSUBGHZSPI_NSS(void) { - 80039b0: b480 push {r7} - 80039b2: af00 add r7, sp, #0 + 80037bc: b480 push {r7} + 80037be: af00 add r7, sp, #0 SET_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS); - 80039b4: 4b05 ldr r3, [pc, #20] ; (80039cc ) - 80039b6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 80039ba: 4a04 ldr r2, [pc, #16] ; (80039cc ) - 80039bc: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 80039c0: f8c2 3090 str.w r3, [r2, #144] ; 0x90 -} - 80039c4: bf00 nop - 80039c6: 46bd mov sp, r7 - 80039c8: bc80 pop {r7} - 80039ca: 4770 bx lr - 80039cc: 58000400 .word 0x58000400 - -080039d0 : + 80037c0: 4b05 ldr r3, [pc, #20] ; (80037d8 ) + 80037c2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80037c6: 4a04 ldr r2, [pc, #16] ; (80037d8 ) + 80037c8: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 80037cc: f8c2 3090 str.w r3, [r2, #144] ; 0x90 +} + 80037d0: bf00 nop + 80037d2: 46bd mov sp, r7 + 80037d4: bc80 pop {r7} + 80037d6: 4770 bx lr + 80037d8: 58000400 .word 0x58000400 + +080037dc : * @brief Set sub-GHz radio SPI NSS at logical level low. * @rmtoll SUBGHZSPICR NSS LL_PWR_SelectSUBGHZSPI_NSS * @retval None */ __STATIC_INLINE void LL_PWR_SelectSUBGHZSPI_NSS(void) { - 80039d0: b480 push {r7} - 80039d2: af00 add r7, sp, #0 + 80037dc: b480 push {r7} + 80037de: af00 add r7, sp, #0 CLEAR_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS); - 80039d4: 4b05 ldr r3, [pc, #20] ; (80039ec ) - 80039d6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 80039da: 4a04 ldr r2, [pc, #16] ; (80039ec ) - 80039dc: f423 4300 bic.w r3, r3, #32768 ; 0x8000 - 80039e0: f8c2 3090 str.w r3, [r2, #144] ; 0x90 -} - 80039e4: bf00 nop - 80039e6: 46bd mov sp, r7 - 80039e8: bc80 pop {r7} - 80039ea: 4770 bx lr - 80039ec: 58000400 .word 0x58000400 - -080039f0 : + 80037e0: 4b05 ldr r3, [pc, #20] ; (80037f8 ) + 80037e2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80037e6: 4a04 ldr r2, [pc, #16] ; (80037f8 ) + 80037e8: f423 4300 bic.w r3, r3, #32768 ; 0x8000 + 80037ec: f8c2 3090 str.w r3, [r2, #144] ; 0x90 +} + 80037f0: bf00 nop + 80037f2: 46bd mov sp, r7 + 80037f4: bc80 pop {r7} + 80037f6: 4770 bx lr + 80037f8: 58000400 .word 0x58000400 + +080037fc : * @brief Clear radio busy flag * @rmtoll SCR CRFBUSYF LL_PWR_ClearFlag_RFBUSY * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_RFBUSY(void) { - 80039f0: b480 push {r7} - 80039f2: af00 add r7, sp, #0 + 80037fc: b480 push {r7} + 80037fe: af00 add r7, sp, #0 WRITE_REG(PWR->SCR, PWR_SCR_CWRFBUSYF); - 80039f4: 4b03 ldr r3, [pc, #12] ; (8003a04 ) - 80039f6: f44f 6200 mov.w r2, #2048 ; 0x800 - 80039fa: 619a str r2, [r3, #24] + 8003800: 4b03 ldr r3, [pc, #12] ; (8003810 ) + 8003802: f44f 6200 mov.w r2, #2048 ; 0x800 + 8003806: 619a str r2, [r3, #24] } - 80039fc: bf00 nop - 80039fe: 46bd mov sp, r7 - 8003a00: bc80 pop {r7} - 8003a02: 4770 bx lr - 8003a04: 58000400 .word 0x58000400 + 8003808: bf00 nop + 800380a: 46bd mov sp, r7 + 800380c: bc80 pop {r7} + 800380e: 4770 bx lr + 8003810: 58000400 .word 0x58000400 -08003a08 : +08003814 : * @ref LL_PWR_IsActiveFlag_RFBUSY() * @rmtoll SR2 RFBUSYS LL_PWR_IsActiveFlag_RFBUSYS * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_RFBUSYS(void) { - 8003a08: b480 push {r7} - 8003a0a: af00 add r7, sp, #0 + 8003814: b480 push {r7} + 8003816: af00 add r7, sp, #0 return ((READ_BIT(PWR->SR2, PWR_SR2_RFBUSYS) == (PWR_SR2_RFBUSYS)) ? 1UL : 0UL); - 8003a0c: 4b06 ldr r3, [pc, #24] ; (8003a28 ) - 8003a0e: 695b ldr r3, [r3, #20] - 8003a10: f003 0302 and.w r3, r3, #2 - 8003a14: 2b02 cmp r3, #2 - 8003a16: d101 bne.n 8003a1c - 8003a18: 2301 movs r3, #1 - 8003a1a: e000 b.n 8003a1e - 8003a1c: 2300 movs r3, #0 -} - 8003a1e: 4618 mov r0, r3 - 8003a20: 46bd mov sp, r7 - 8003a22: bc80 pop {r7} - 8003a24: 4770 bx lr - 8003a26: bf00 nop - 8003a28: 58000400 .word 0x58000400 - -08003a2c : + 8003818: 4b06 ldr r3, [pc, #24] ; (8003834 ) + 800381a: 695b ldr r3, [r3, #20] + 800381c: f003 0302 and.w r3, r3, #2 + 8003820: 2b02 cmp r3, #2 + 8003822: d101 bne.n 8003828 + 8003824: 2301 movs r3, #1 + 8003826: e000 b.n 800382a + 8003828: 2300 movs r3, #0 +} + 800382a: 4618 mov r0, r3 + 800382c: 46bd mov sp, r7 + 800382e: bc80 pop {r7} + 8003830: 4770 bx lr + 8003832: bf00 nop + 8003834: 58000400 .word 0x58000400 + +08003838 : * @ref LL_PWR_IsActiveFlag_RFBUSY() * @rmtoll SR2 RFBUSYMS LL_PWR_IsActiveFlag_RFBUSYMS * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_RFBUSYMS(void) { - 8003a2c: b480 push {r7} - 8003a2e: af00 add r7, sp, #0 + 8003838: b480 push {r7} + 800383a: af00 add r7, sp, #0 return ((READ_BIT(PWR->SR2, PWR_SR2_RFBUSYMS) == (PWR_SR2_RFBUSYMS)) ? 1UL : 0UL); - 8003a30: 4b06 ldr r3, [pc, #24] ; (8003a4c ) - 8003a32: 695b ldr r3, [r3, #20] - 8003a34: f003 0304 and.w r3, r3, #4 - 8003a38: 2b04 cmp r3, #4 - 8003a3a: d101 bne.n 8003a40 - 8003a3c: 2301 movs r3, #1 - 8003a3e: e000 b.n 8003a42 - 8003a40: 2300 movs r3, #0 -} - 8003a42: 4618 mov r0, r3 - 8003a44: 46bd mov sp, r7 - 8003a46: bc80 pop {r7} - 8003a48: 4770 bx lr - 8003a4a: bf00 nop - 8003a4c: 58000400 .word 0x58000400 - -08003a50 : -{ - 8003a50: b480 push {r7} - 8003a52: af00 add r7, sp, #0 + 800383c: 4b06 ldr r3, [pc, #24] ; (8003858 ) + 800383e: 695b ldr r3, [r3, #20] + 8003840: f003 0304 and.w r3, r3, #4 + 8003844: 2b04 cmp r3, #4 + 8003846: d101 bne.n 800384c + 8003848: 2301 movs r3, #1 + 800384a: e000 b.n 800384e + 800384c: 2300 movs r3, #0 +} + 800384e: 4618 mov r0, r3 + 8003850: 46bd mov sp, r7 + 8003852: bc80 pop {r7} + 8003854: 4770 bx lr + 8003856: bf00 nop + 8003858: 58000400 .word 0x58000400 + +0800385c : +{ + 800385c: b480 push {r7} + 800385e: af00 add r7, sp, #0 CLEAR_BIT(RCC->CSR, RCC_CSR_RFRST); - 8003a54: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8003a58: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 - 8003a5c: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 - 8003a60: f423 4300 bic.w r3, r3, #32768 ; 0x8000 - 8003a64: f8c2 3094 str.w r3, [r2, #148] ; 0x94 + 8003860: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003864: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 8003868: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 800386c: f423 4300 bic.w r3, r3, #32768 ; 0x8000 + 8003870: f8c2 3094 str.w r3, [r2, #148] ; 0x94 } - 8003a68: bf00 nop - 8003a6a: 46bd mov sp, r7 - 8003a6c: bc80 pop {r7} - 8003a6e: 4770 bx lr + 8003874: bf00 nop + 8003876: 46bd mov sp, r7 + 8003878: bc80 pop {r7} + 800387a: 4770 bx lr -08003a70 : +0800387c : { - 8003a70: b480 push {r7} - 8003a72: af00 add r7, sp, #0 + 800387c: b480 push {r7} + 800387e: af00 add r7, sp, #0 return ((READ_BIT(RCC->CSR, RCC_CSR_RFRSTF) == (RCC_CSR_RFRSTF)) ? 1UL : 0UL); - 8003a74: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8003a78: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 - 8003a7c: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 8003a80: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 - 8003a84: d101 bne.n 8003a8a - 8003a86: 2301 movs r3, #1 - 8003a88: e000 b.n 8003a8c - 8003a8a: 2300 movs r3, #0 -} - 8003a8c: 4618 mov r0, r3 - 8003a8e: 46bd mov sp, r7 - 8003a90: bc80 pop {r7} - 8003a92: 4770 bx lr - -08003a94 : + 8003880: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003884: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 8003888: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800388c: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 8003890: d101 bne.n 8003896 + 8003892: 2301 movs r3, #1 + 8003894: e000 b.n 8003898 + 8003896: 2300 movs r3, #0 +} + 8003898: 4618 mov r0, r3 + 800389a: 46bd mov sp, r7 + 800389c: bc80 pop {r7} + 800389e: 4770 bx lr + +080038a0 : * @arg @ref LL_EXTI_LINE_ALL_32_63 * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) { - 8003a94: b480 push {r7} - 8003a96: b083 sub sp, #12 - 8003a98: af00 add r7, sp, #0 - 8003a9a: 6078 str r0, [r7, #4] + 80038a0: b480 push {r7} + 80038a2: b083 sub sp, #12 + 80038a4: af00 add r7, sp, #0 + 80038a6: 6078 str r0, [r7, #4] SET_BIT(EXTI->IMR2, ExtiLine); - 8003a9c: 4b06 ldr r3, [pc, #24] ; (8003ab8 ) - 8003a9e: f8d3 2090 ldr.w r2, [r3, #144] ; 0x90 - 8003aa2: 4905 ldr r1, [pc, #20] ; (8003ab8 ) - 8003aa4: 687b ldr r3, [r7, #4] - 8003aa6: 4313 orrs r3, r2 - 8003aa8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 -} - 8003aac: bf00 nop - 8003aae: 370c adds r7, #12 - 8003ab0: 46bd mov sp, r7 - 8003ab2: bc80 pop {r7} - 8003ab4: 4770 bx lr - 8003ab6: bf00 nop - 8003ab8: 58000800 .word 0x58000800 - -08003abc : + 80038a8: 4b06 ldr r3, [pc, #24] ; (80038c4 ) + 80038aa: f8d3 2090 ldr.w r2, [r3, #144] ; 0x90 + 80038ae: 4905 ldr r1, [pc, #20] ; (80038c4 ) + 80038b0: 687b ldr r3, [r7, #4] + 80038b2: 4313 orrs r3, r2 + 80038b4: f8c1 3090 str.w r3, [r1, #144] ; 0x90 +} + 80038b8: bf00 nop + 80038ba: 370c adds r7, #12 + 80038bc: 46bd mov sp, r7 + 80038be: bc80 pop {r7} + 80038c0: 4770 bx lr + 80038c2: bf00 nop + 80038c4: 58000800 .word 0x58000800 + +080038c8 : * set the state to HAL_SUBGHZ_STATE_RESET_RF_READY with __HAL_SUBGHZ_RESET_HANDLE_STATE_RF_READY * to avoid the reset of Radio peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz) { - 8003abc: b580 push {r7, lr} - 8003abe: b084 sub sp, #16 - 8003ac0: af00 add r7, sp, #0 - 8003ac2: 6078 str r0, [r7, #4] + 80038c8: b580 push {r7, lr} + 80038ca: b084 sub sp, #16 + 80038cc: af00 add r7, sp, #0 + 80038ce: 6078 str r0, [r7, #4] HAL_StatusTypeDef status; __IO uint32_t count; HAL_SUBGHZ_StateTypeDef subghz_state; /* Check the hsubghz handle allocation */ if (hsubghz == NULL) - 8003ac4: 687b ldr r3, [r7, #4] - 8003ac6: 2b00 cmp r3, #0 - 8003ac8: d103 bne.n 8003ad2 + 80038d0: 687b ldr r3, [r7, #4] + 80038d2: 2b00 cmp r3, #0 + 80038d4: d103 bne.n 80038de { status = HAL_ERROR; - 8003aca: 2301 movs r3, #1 - 8003acc: 73fb strb r3, [r7, #15] + 80038d6: 2301 movs r3, #1 + 80038d8: 73fb strb r3, [r7, #15] return status; - 8003ace: 7bfb ldrb r3, [r7, #15] - 8003ad0: e052 b.n 8003b78 + 80038da: 7bfb ldrb r3, [r7, #15] + 80038dc: e052 b.n 8003984 } else { status = HAL_OK; - 8003ad2: 2300 movs r3, #0 - 8003ad4: 73fb strb r3, [r7, #15] + 80038de: 2300 movs r3, #0 + 80038e0: 73fb strb r3, [r7, #15] } assert_param(IS_SUBGHZSPI_BAUDRATE_PRESCALER(hsubghz->Init.BaudratePrescaler)); subghz_state = hsubghz->State; - 8003ad6: 687b ldr r3, [r7, #4] - 8003ad8: 799b ldrb r3, [r3, #6] - 8003ada: 73bb strb r3, [r7, #14] + 80038e2: 687b ldr r3, [r7, #4] + 80038e4: 799b ldrb r3, [r3, #6] + 80038e6: 73bb strb r3, [r7, #14] if ((subghz_state == HAL_SUBGHZ_STATE_RESET) || - 8003adc: 7bbb ldrb r3, [r7, #14] - 8003ade: 2b00 cmp r3, #0 - 8003ae0: d002 beq.n 8003ae8 - 8003ae2: 7bbb ldrb r3, [r7, #14] - 8003ae4: 2b03 cmp r3, #3 - 8003ae6: d109 bne.n 8003afc + 80038e8: 7bbb ldrb r3, [r7, #14] + 80038ea: 2b00 cmp r3, #0 + 80038ec: d002 beq.n 80038f4 + 80038ee: 7bbb ldrb r3, [r7, #14] + 80038f0: 2b03 cmp r3, #3 + 80038f2: d109 bne.n 8003908 (subghz_state == HAL_SUBGHZ_STATE_RESET_RF_READY)) { /* Allocate lock resource and initialize it */ hsubghz->Lock = HAL_UNLOCKED; - 8003ae8: 687b ldr r3, [r7, #4] - 8003aea: 2200 movs r2, #0 - 8003aec: 715a strb r2, [r3, #5] + 80038f4: 687b ldr r3, [r7, #4] + 80038f6: 2200 movs r2, #0 + 80038f8: 715a strb r2, [r3, #5] /* Init the low level hardware : GPIO, CLOCK, NVIC... */ hsubghz->MspInitCallback(hsubghz); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SUBGHZ_MspInit(hsubghz); - 8003aee: 6878 ldr r0, [r7, #4] - 8003af0: f7fd fdbe bl 8001670 + 80038fa: 6878 ldr r0, [r7, #4] + 80038fc: f7fd fdbe bl 800147c #if defined(CM0PLUS) /* Enable EXTI 44 : Radio IRQ ITs for CPU2 */ LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_44); #else /* Enable EXTI 44 : Radio IRQ ITs for CPU1 */ LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_44); - 8003af4: f44f 5080 mov.w r0, #4096 ; 0x1000 - 8003af8: f7ff ffcc bl 8003a94 + 8003900: f44f 5080 mov.w r0, #4096 ; 0x1000 + 8003904: f7ff ffcc bl 80038a0 #endif /* CM0PLUS */ } if (subghz_state == HAL_SUBGHZ_STATE_RESET) - 8003afc: 7bbb ldrb r3, [r7, #14] - 8003afe: 2b00 cmp r3, #0 - 8003b00: d126 bne.n 8003b50 + 8003908: 7bbb ldrb r3, [r7, #14] + 800390a: 2b00 cmp r3, #0 + 800390c: d126 bne.n 800395c { /* Reinitialize Radio peripheral only if SUBGHZ is in full RESET state */ hsubghz->State = HAL_SUBGHZ_STATE_BUSY; - 8003b02: 687b ldr r3, [r7, #4] - 8003b04: 2202 movs r2, #2 - 8003b06: 719a strb r2, [r3, #6] + 800390e: 687b ldr r3, [r7, #4] + 8003910: 2202 movs r2, #2 + 8003912: 719a strb r2, [r3, #6] /* De-asserts the reset signal of the Radio peripheral */ LL_RCC_RF_DisableReset(); - 8003b08: f7ff ffa2 bl 8003a50 + 8003914: f7ff ffa2 bl 800385c /* Verify that Radio in reset status flag is set */ count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; - 8003b0c: 4b1c ldr r3, [pc, #112] ; (8003b80 ) - 8003b0e: 681a ldr r2, [r3, #0] - 8003b10: 4613 mov r3, r2 - 8003b12: 00db lsls r3, r3, #3 - 8003b14: 1a9b subs r3, r3, r2 - 8003b16: 009b lsls r3, r3, #2 - 8003b18: 0cdb lsrs r3, r3, #19 - 8003b1a: 2264 movs r2, #100 ; 0x64 - 8003b1c: fb02 f303 mul.w r3, r2, r3 - 8003b20: 60bb str r3, [r7, #8] + 8003918: 4b1c ldr r3, [pc, #112] ; (800398c ) + 800391a: 681a ldr r2, [r3, #0] + 800391c: 4613 mov r3, r2 + 800391e: 00db lsls r3, r3, #3 + 8003920: 1a9b subs r3, r3, r2 + 8003922: 009b lsls r3, r3, #2 + 8003924: 0cdb lsrs r3, r3, #19 + 8003926: 2264 movs r2, #100 ; 0x64 + 8003928: fb02 f303 mul.w r3, r2, r3 + 800392c: 60bb str r3, [r7, #8] do { if (count == 0U) - 8003b22: 68bb ldr r3, [r7, #8] - 8003b24: 2b00 cmp r3, #0 - 8003b26: d105 bne.n 8003b34 + 800392e: 68bb ldr r3, [r7, #8] + 8003930: 2b00 cmp r3, #0 + 8003932: d105 bne.n 8003940 { status = HAL_ERROR; - 8003b28: 2301 movs r3, #1 - 8003b2a: 73fb strb r3, [r7, #15] + 8003934: 2301 movs r3, #1 + 8003936: 73fb strb r3, [r7, #15] hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; - 8003b2c: 687b ldr r3, [r7, #4] - 8003b2e: 2201 movs r2, #1 - 8003b30: 609a str r2, [r3, #8] + 8003938: 687b ldr r3, [r7, #4] + 800393a: 2201 movs r2, #1 + 800393c: 609a str r2, [r3, #8] break; - 8003b32: e007 b.n 8003b44 + 800393e: e007 b.n 8003950 } count--; - 8003b34: 68bb ldr r3, [r7, #8] - 8003b36: 3b01 subs r3, #1 - 8003b38: 60bb str r3, [r7, #8] + 8003940: 68bb ldr r3, [r7, #8] + 8003942: 3b01 subs r3, #1 + 8003944: 60bb str r3, [r7, #8] } while (LL_RCC_IsRFUnderReset() != 0UL); - 8003b3a: f7ff ff99 bl 8003a70 - 8003b3e: 4603 mov r3, r0 - 8003b40: 2b00 cmp r3, #0 - 8003b42: d1ee bne.n 8003b22 + 8003946: f7ff ff99 bl 800387c + 800394a: 4603 mov r3, r0 + 800394c: 2b00 cmp r3, #0 + 800394e: d1ee bne.n 800392e /* Asserts the reset signal of the Radio peripheral */ LL_PWR_UnselectSUBGHZSPI_NSS(); - 8003b44: f7ff ff34 bl 80039b0 + 8003950: f7ff ff34 bl 80037bc #if defined(CM0PLUS) /* Enable wakeup signal of the Radio peripheral */ LL_C2_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT); #else /* Enable wakeup signal of the Radio peripheral */ LL_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT); - 8003b48: f44f 6000 mov.w r0, #2048 ; 0x800 - 8003b4c: f7ff ff1c bl 8003988 + 8003954: f44f 6000 mov.w r0, #2048 ; 0x800 + 8003958: f7ff ff1c bl 8003794 #endif /* CM0PLUS */ } /* Clear Pending Flag */ LL_PWR_ClearFlag_RFBUSY(); - 8003b50: f7ff ff4e bl 80039f0 + 800395c: f7ff ff4e bl 80037fc if (status == HAL_OK) - 8003b54: 7bfb ldrb r3, [r7, #15] - 8003b56: 2b00 cmp r3, #0 - 8003b58: d10a bne.n 8003b70 + 8003960: 7bfb ldrb r3, [r7, #15] + 8003962: 2b00 cmp r3, #0 + 8003964: d10a bne.n 800397c { /* Initialize SUBGHZSPI Peripheral */ SUBGHZSPI_Init(hsubghz->Init.BaudratePrescaler); - 8003b5a: 687b ldr r3, [r7, #4] - 8003b5c: 681b ldr r3, [r3, #0] - 8003b5e: 4618 mov r0, r3 - 8003b60: f000 f870 bl 8003c44 + 8003966: 687b ldr r3, [r7, #4] + 8003968: 681b ldr r3, [r3, #0] + 800396a: 4618 mov r0, r3 + 800396c: f000 f870 bl 8003a50 hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_ENABLE; - 8003b64: 687b ldr r3, [r7, #4] - 8003b66: 2201 movs r2, #1 - 8003b68: 711a strb r2, [r3, #4] + 8003970: 687b ldr r3, [r7, #4] + 8003972: 2201 movs r2, #1 + 8003974: 711a strb r2, [r3, #4] hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_NONE; - 8003b6a: 687b ldr r3, [r7, #4] - 8003b6c: 2200 movs r2, #0 - 8003b6e: 609a str r2, [r3, #8] + 8003976: 687b ldr r3, [r7, #4] + 8003978: 2200 movs r2, #0 + 800397a: 609a str r2, [r3, #8] } hsubghz->State = HAL_SUBGHZ_STATE_READY; - 8003b70: 687b ldr r3, [r7, #4] - 8003b72: 2201 movs r2, #1 - 8003b74: 719a strb r2, [r3, #6] + 800397c: 687b ldr r3, [r7, #4] + 800397e: 2201 movs r2, #1 + 8003980: 719a strb r2, [r3, #6] return status; - 8003b76: 7bfb ldrb r3, [r7, #15] + 8003982: 7bfb ldrb r3, [r7, #15] } - 8003b78: 4618 mov r0, r3 - 8003b7a: 3710 adds r7, #16 - 8003b7c: 46bd mov sp, r7 - 8003b7e: bd80 pop {r7, pc} - 8003b80: 20000008 .word 0x20000008 + 8003984: 4618 mov r0, r3 + 8003986: 3710 adds r7, #16 + 8003988: 46bd mov sp, r7 + 800398a: bd80 pop {r7, pc} + 800398c: 20000000 .word 0x20000000 -08003b84 : +08003990 : */ HAL_StatusTypeDef HAL_SUBGHZ_ExecSetCmd(SUBGHZ_HandleTypeDef *hsubghz, SUBGHZ_RadioSetCmd_t Command, uint8_t *pBuffer, uint16_t Size) { - 8003b84: b580 push {r7, lr} - 8003b86: b086 sub sp, #24 - 8003b88: af00 add r7, sp, #0 - 8003b8a: 60f8 str r0, [r7, #12] - 8003b8c: 607a str r2, [r7, #4] - 8003b8e: 461a mov r2, r3 - 8003b90: 460b mov r3, r1 - 8003b92: 72fb strb r3, [r7, #11] - 8003b94: 4613 mov r3, r2 - 8003b96: 813b strh r3, [r7, #8] + 8003990: b580 push {r7, lr} + 8003992: b086 sub sp, #24 + 8003994: af00 add r7, sp, #0 + 8003996: 60f8 str r0, [r7, #12] + 8003998: 607a str r2, [r7, #4] + 800399a: 461a mov r2, r3 + 800399c: 460b mov r3, r1 + 800399e: 72fb strb r3, [r7, #11] + 80039a0: 4613 mov r3, r2 + 80039a2: 813b strh r3, [r7, #8] HAL_StatusTypeDef status; /* LORA Modulation not available on STM32WLx4xx devices */ assert_param(IS_SUBGHZ_MODULATION_SUPPORTED(Command, pBuffer[0U])); if (hsubghz->State == HAL_SUBGHZ_STATE_READY) - 8003b98: 68fb ldr r3, [r7, #12] - 8003b9a: 799b ldrb r3, [r3, #6] - 8003b9c: b2db uxtb r3, r3 - 8003b9e: 2b01 cmp r3, #1 - 8003ba0: d14a bne.n 8003c38 + 80039a4: 68fb ldr r3, [r7, #12] + 80039a6: 799b ldrb r3, [r3, #6] + 80039a8: b2db uxtb r3, r3 + 80039aa: 2b01 cmp r3, #1 + 80039ac: d14a bne.n 8003a44 { /* Process Locked */ __HAL_LOCK(hsubghz); - 8003ba2: 68fb ldr r3, [r7, #12] - 8003ba4: 795b ldrb r3, [r3, #5] - 8003ba6: 2b01 cmp r3, #1 - 8003ba8: d101 bne.n 8003bae - 8003baa: 2302 movs r3, #2 - 8003bac: e045 b.n 8003c3a - 8003bae: 68fb ldr r3, [r7, #12] - 8003bb0: 2201 movs r2, #1 - 8003bb2: 715a strb r2, [r3, #5] + 80039ae: 68fb ldr r3, [r7, #12] + 80039b0: 795b ldrb r3, [r3, #5] + 80039b2: 2b01 cmp r3, #1 + 80039b4: d101 bne.n 80039ba + 80039b6: 2302 movs r3, #2 + 80039b8: e045 b.n 8003a46 + 80039ba: 68fb ldr r3, [r7, #12] + 80039bc: 2201 movs r2, #1 + 80039be: 715a strb r2, [r3, #5] /* Need to wakeup Radio if already in Sleep at startup */ (void)SUBGHZ_CheckDeviceReady(hsubghz); - 8003bb4: 68f8 ldr r0, [r7, #12] - 8003bb6: f000 f8bb bl 8003d30 + 80039c0: 68f8 ldr r0, [r7, #12] + 80039c2: f000 f8bb bl 8003b3c if ((Command == RADIO_SET_SLEEP) || (Command == RADIO_SET_RXDUTYCYCLE)) - 8003bba: 7afb ldrb r3, [r7, #11] - 8003bbc: 2b84 cmp r3, #132 ; 0x84 - 8003bbe: d002 beq.n 8003bc6 - 8003bc0: 7afb ldrb r3, [r7, #11] - 8003bc2: 2b94 cmp r3, #148 ; 0x94 - 8003bc4: d103 bne.n 8003bce + 80039c6: 7afb ldrb r3, [r7, #11] + 80039c8: 2b84 cmp r3, #132 ; 0x84 + 80039ca: d002 beq.n 80039d2 + 80039cc: 7afb ldrb r3, [r7, #11] + 80039ce: 2b94 cmp r3, #148 ; 0x94 + 80039d0: d103 bne.n 80039da { hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_ENABLE; - 8003bc6: 68fb ldr r3, [r7, #12] - 8003bc8: 2201 movs r2, #1 - 8003bca: 711a strb r2, [r3, #4] - 8003bcc: e002 b.n 8003bd4 + 80039d2: 68fb ldr r3, [r7, #12] + 80039d4: 2201 movs r2, #1 + 80039d6: 711a strb r2, [r3, #4] + 80039d8: e002 b.n 80039e0 } else { hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_DISABLE; - 8003bce: 68fb ldr r3, [r7, #12] - 8003bd0: 2200 movs r2, #0 - 8003bd2: 711a strb r2, [r3, #4] + 80039da: 68fb ldr r3, [r7, #12] + 80039dc: 2200 movs r2, #0 + 80039de: 711a strb r2, [r3, #4] } /* NSS = 0 */ LL_PWR_SelectSUBGHZSPI_NSS(); - 8003bd4: f7ff fefc bl 80039d0 + 80039e0: f7ff fefc bl 80037dc (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)Command); - 8003bd8: 7afb ldrb r3, [r7, #11] - 8003bda: 4619 mov r1, r3 - 8003bdc: 68f8 ldr r0, [r7, #12] - 8003bde: f000 f851 bl 8003c84 + 80039e4: 7afb ldrb r3, [r7, #11] + 80039e6: 4619 mov r1, r3 + 80039e8: 68f8 ldr r0, [r7, #12] + 80039ea: f000 f851 bl 8003a90 for (uint16_t i = 0U; i < Size; i++) - 8003be2: 2300 movs r3, #0 - 8003be4: 82bb strh r3, [r7, #20] - 8003be6: e00a b.n 8003bfe + 80039ee: 2300 movs r3, #0 + 80039f0: 82bb strh r3, [r7, #20] + 80039f2: e00a b.n 8003a0a { (void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]); - 8003be8: 8abb ldrh r3, [r7, #20] - 8003bea: 687a ldr r2, [r7, #4] - 8003bec: 4413 add r3, r2 - 8003bee: 781b ldrb r3, [r3, #0] - 8003bf0: 4619 mov r1, r3 - 8003bf2: 68f8 ldr r0, [r7, #12] - 8003bf4: f000 f846 bl 8003c84 + 80039f4: 8abb ldrh r3, [r7, #20] + 80039f6: 687a ldr r2, [r7, #4] + 80039f8: 4413 add r3, r2 + 80039fa: 781b ldrb r3, [r3, #0] + 80039fc: 4619 mov r1, r3 + 80039fe: 68f8 ldr r0, [r7, #12] + 8003a00: f000 f846 bl 8003a90 for (uint16_t i = 0U; i < Size; i++) - 8003bf8: 8abb ldrh r3, [r7, #20] - 8003bfa: 3301 adds r3, #1 - 8003bfc: 82bb strh r3, [r7, #20] - 8003bfe: 8aba ldrh r2, [r7, #20] - 8003c00: 893b ldrh r3, [r7, #8] - 8003c02: 429a cmp r2, r3 - 8003c04: d3f0 bcc.n 8003be8 + 8003a04: 8abb ldrh r3, [r7, #20] + 8003a06: 3301 adds r3, #1 + 8003a08: 82bb strh r3, [r7, #20] + 8003a0a: 8aba ldrh r2, [r7, #20] + 8003a0c: 893b ldrh r3, [r7, #8] + 8003a0e: 429a cmp r2, r3 + 8003a10: d3f0 bcc.n 80039f4 } /* NSS = 1 */ LL_PWR_UnselectSUBGHZSPI_NSS(); - 8003c06: f7ff fed3 bl 80039b0 + 8003a12: f7ff fed3 bl 80037bc if (Command != RADIO_SET_SLEEP) - 8003c0a: 7afb ldrb r3, [r7, #11] - 8003c0c: 2b84 cmp r3, #132 ; 0x84 - 8003c0e: d002 beq.n 8003c16 + 8003a16: 7afb ldrb r3, [r7, #11] + 8003a18: 2b84 cmp r3, #132 ; 0x84 + 8003a1a: d002 beq.n 8003a22 { (void)SUBGHZ_WaitOnBusy(hsubghz); - 8003c10: 68f8 ldr r0, [r7, #12] - 8003c12: f000 f8b1 bl 8003d78 + 8003a1c: 68f8 ldr r0, [r7, #12] + 8003a1e: f000 f8b1 bl 8003b84 } if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) - 8003c16: 68fb ldr r3, [r7, #12] - 8003c18: 689b ldr r3, [r3, #8] - 8003c1a: 2b00 cmp r3, #0 - 8003c1c: d002 beq.n 8003c24 + 8003a22: 68fb ldr r3, [r7, #12] + 8003a24: 689b ldr r3, [r3, #8] + 8003a26: 2b00 cmp r3, #0 + 8003a28: d002 beq.n 8003a30 { status = HAL_ERROR; - 8003c1e: 2301 movs r3, #1 - 8003c20: 75fb strb r3, [r7, #23] - 8003c22: e001 b.n 8003c28 + 8003a2a: 2301 movs r3, #1 + 8003a2c: 75fb strb r3, [r7, #23] + 8003a2e: e001 b.n 8003a34 } else { status = HAL_OK; - 8003c24: 2300 movs r3, #0 - 8003c26: 75fb strb r3, [r7, #23] + 8003a30: 2300 movs r3, #0 + 8003a32: 75fb strb r3, [r7, #23] } hsubghz->State = HAL_SUBGHZ_STATE_READY; - 8003c28: 68fb ldr r3, [r7, #12] - 8003c2a: 2201 movs r2, #1 - 8003c2c: 719a strb r2, [r3, #6] + 8003a34: 68fb ldr r3, [r7, #12] + 8003a36: 2201 movs r2, #1 + 8003a38: 719a strb r2, [r3, #6] /* Process Unlocked */ __HAL_UNLOCK(hsubghz); - 8003c2e: 68fb ldr r3, [r7, #12] - 8003c30: 2200 movs r2, #0 - 8003c32: 715a strb r2, [r3, #5] + 8003a3a: 68fb ldr r3, [r7, #12] + 8003a3c: 2200 movs r2, #0 + 8003a3e: 715a strb r2, [r3, #5] return status; - 8003c34: 7dfb ldrb r3, [r7, #23] - 8003c36: e000 b.n 8003c3a + 8003a40: 7dfb ldrb r3, [r7, #23] + 8003a42: e000 b.n 8003a46 } else { return HAL_BUSY; - 8003c38: 2302 movs r3, #2 + 8003a44: 2302 movs r3, #2 } } - 8003c3a: 4618 mov r0, r3 - 8003c3c: 3718 adds r7, #24 - 8003c3e: 46bd mov sp, r7 - 8003c40: bd80 pop {r7, pc} + 8003a46: 4618 mov r0, r3 + 8003a48: 3718 adds r7, #24 + 8003a4a: 46bd mov sp, r7 + 8003a4c: bd80 pop {r7, pc} ... -08003c44 : +08003a50 : * @brief Initializes the SUBGHZSPI peripheral * @param BaudratePrescaler SPI Baudrate prescaler * @retval None */ void SUBGHZSPI_Init(uint32_t BaudratePrescaler) { - 8003c44: b480 push {r7} - 8003c46: b083 sub sp, #12 - 8003c48: af00 add r7, sp, #0 - 8003c4a: 6078 str r0, [r7, #4] + 8003a50: b480 push {r7} + 8003a52: b083 sub sp, #12 + 8003a54: af00 add r7, sp, #0 + 8003a56: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_SUBGHZ_ALL_INSTANCE(SUBGHZSPI)); /* Disable SUBGHZSPI Peripheral */ CLEAR_BIT(SUBGHZSPI->CR1, SPI_CR1_SPE); - 8003c4c: 4b0c ldr r3, [pc, #48] ; (8003c80 ) - 8003c4e: 681b ldr r3, [r3, #0] - 8003c50: 4a0b ldr r2, [pc, #44] ; (8003c80 ) - 8003c52: f023 0340 bic.w r3, r3, #64 ; 0x40 - 8003c56: 6013 str r3, [r2, #0] + 8003a58: 4b0c ldr r3, [pc, #48] ; (8003a8c ) + 8003a5a: 681b ldr r3, [r3, #0] + 8003a5c: 4a0b ldr r2, [pc, #44] ; (8003a8c ) + 8003a5e: f023 0340 bic.w r3, r3, #64 ; 0x40 + 8003a62: 6013 str r3, [r2, #0] * NSS management: Internal (Done with External bit inside PWR * * Communication speed: BaudratePrescaler * * First bit: MSB * * CRC calculation: Disable * *--------------------------------------------------------------------------*/ WRITE_REG(SUBGHZSPI->CR1, (SPI_CR1_MSTR | SPI_CR1_SSI | BaudratePrescaler | SPI_CR1_SSM)); - 8003c58: 4a09 ldr r2, [pc, #36] ; (8003c80 ) - 8003c5a: 687b ldr r3, [r7, #4] - 8003c5c: f443 7341 orr.w r3, r3, #772 ; 0x304 - 8003c60: 6013 str r3, [r2, #0] + 8003a64: 4a09 ldr r2, [pc, #36] ; (8003a8c ) + 8003a66: 687b ldr r3, [r7, #4] + 8003a68: f443 7341 orr.w r3, r3, #772 ; 0x304 + 8003a6c: 6013 str r3, [r2, #0] * Data Size: 8bits * * TI Mode: Disable * * NSS Pulse: Disable * * Rx FIFO Threshold: 8bits * *--------------------------------------------------------------------------*/ WRITE_REG(SUBGHZSPI->CR2, (SPI_CR2_FRXTH | SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2)); - 8003c62: 4b07 ldr r3, [pc, #28] ; (8003c80 ) - 8003c64: f44f 52b8 mov.w r2, #5888 ; 0x1700 - 8003c68: 605a str r2, [r3, #4] + 8003a6e: 4b07 ldr r3, [pc, #28] ; (8003a8c ) + 8003a70: f44f 52b8 mov.w r2, #5888 ; 0x1700 + 8003a74: 605a str r2, [r3, #4] /* Enable SUBGHZSPI Peripheral */ SET_BIT(SUBGHZSPI->CR1, SPI_CR1_SPE); - 8003c6a: 4b05 ldr r3, [pc, #20] ; (8003c80 ) - 8003c6c: 681b ldr r3, [r3, #0] - 8003c6e: 4a04 ldr r2, [pc, #16] ; (8003c80 ) - 8003c70: f043 0340 orr.w r3, r3, #64 ; 0x40 - 8003c74: 6013 str r3, [r2, #0] -} - 8003c76: bf00 nop - 8003c78: 370c adds r7, #12 - 8003c7a: 46bd mov sp, r7 - 8003c7c: bc80 pop {r7} - 8003c7e: 4770 bx lr - 8003c80: 58010000 .word 0x58010000 - -08003c84 : + 8003a76: 4b05 ldr r3, [pc, #20] ; (8003a8c ) + 8003a78: 681b ldr r3, [r3, #0] + 8003a7a: 4a04 ldr r2, [pc, #16] ; (8003a8c ) + 8003a7c: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8003a80: 6013 str r3, [r2, #0] +} + 8003a82: bf00 nop + 8003a84: 370c adds r7, #12 + 8003a86: 46bd mov sp, r7 + 8003a88: bc80 pop {r7} + 8003a8a: 4770 bx lr + 8003a8c: 58010000 .word 0x58010000 + +08003a90 : * @param Data data to transmit * @retval HAL status */ HAL_StatusTypeDef SUBGHZSPI_Transmit(SUBGHZ_HandleTypeDef *hsubghz, uint8_t Data) { - 8003c84: b480 push {r7} - 8003c86: b087 sub sp, #28 - 8003c88: af00 add r7, sp, #0 - 8003c8a: 6078 str r0, [r7, #4] - 8003c8c: 460b mov r3, r1 - 8003c8e: 70fb strb r3, [r7, #3] + 8003a90: b480 push {r7} + 8003a92: b087 sub sp, #28 + 8003a94: af00 add r7, sp, #0 + 8003a96: 6078 str r0, [r7, #4] + 8003a98: 460b mov r3, r1 + 8003a9a: 70fb strb r3, [r7, #3] HAL_StatusTypeDef status = HAL_OK; - 8003c90: 2300 movs r3, #0 - 8003c92: 75fb strb r3, [r7, #23] + 8003a9c: 2300 movs r3, #0 + 8003a9e: 75fb strb r3, [r7, #23] __IO uint32_t count; /* Handle Tx transmission from SUBGHZSPI peripheral to Radio ****************/ /* Initialize Timeout */ count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; - 8003c94: 4b23 ldr r3, [pc, #140] ; (8003d24 ) - 8003c96: 681a ldr r2, [r3, #0] - 8003c98: 4613 mov r3, r2 - 8003c9a: 00db lsls r3, r3, #3 - 8003c9c: 1a9b subs r3, r3, r2 - 8003c9e: 009b lsls r3, r3, #2 - 8003ca0: 0cdb lsrs r3, r3, #19 - 8003ca2: 2264 movs r2, #100 ; 0x64 - 8003ca4: fb02 f303 mul.w r3, r2, r3 - 8003ca8: 60fb str r3, [r7, #12] + 8003aa0: 4b23 ldr r3, [pc, #140] ; (8003b30 ) + 8003aa2: 681a ldr r2, [r3, #0] + 8003aa4: 4613 mov r3, r2 + 8003aa6: 00db lsls r3, r3, #3 + 8003aa8: 1a9b subs r3, r3, r2 + 8003aaa: 009b lsls r3, r3, #2 + 8003aac: 0cdb lsrs r3, r3, #19 + 8003aae: 2264 movs r2, #100 ; 0x64 + 8003ab0: fb02 f303 mul.w r3, r2, r3 + 8003ab4: 60fb str r3, [r7, #12] /* Wait until TXE flag is set */ do { if (count == 0U) - 8003caa: 68fb ldr r3, [r7, #12] - 8003cac: 2b00 cmp r3, #0 - 8003cae: d105 bne.n 8003cbc + 8003ab6: 68fb ldr r3, [r7, #12] + 8003ab8: 2b00 cmp r3, #0 + 8003aba: d105 bne.n 8003ac8 { status = HAL_ERROR; - 8003cb0: 2301 movs r3, #1 - 8003cb2: 75fb strb r3, [r7, #23] + 8003abc: 2301 movs r3, #1 + 8003abe: 75fb strb r3, [r7, #23] hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; - 8003cb4: 687b ldr r3, [r7, #4] - 8003cb6: 2201 movs r2, #1 - 8003cb8: 609a str r2, [r3, #8] + 8003ac0: 687b ldr r3, [r7, #4] + 8003ac2: 2201 movs r2, #1 + 8003ac4: 609a str r2, [r3, #8] break; - 8003cba: e008 b.n 8003cce + 8003ac6: e008 b.n 8003ada } count--; - 8003cbc: 68fb ldr r3, [r7, #12] - 8003cbe: 3b01 subs r3, #1 - 8003cc0: 60fb str r3, [r7, #12] + 8003ac8: 68fb ldr r3, [r7, #12] + 8003aca: 3b01 subs r3, #1 + 8003acc: 60fb str r3, [r7, #12] } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_TXE) != (SPI_SR_TXE)); - 8003cc2: 4b19 ldr r3, [pc, #100] ; (8003d28 ) - 8003cc4: 689b ldr r3, [r3, #8] - 8003cc6: f003 0302 and.w r3, r3, #2 - 8003cca: 2b02 cmp r3, #2 - 8003ccc: d1ed bne.n 8003caa + 8003ace: 4b19 ldr r3, [pc, #100] ; (8003b34 ) + 8003ad0: 689b ldr r3, [r3, #8] + 8003ad2: f003 0302 and.w r3, r3, #2 + 8003ad6: 2b02 cmp r3, #2 + 8003ad8: d1ed bne.n 8003ab6 /* Transmit Data*/ #if defined (__GNUC__) __IO uint8_t *spidr = ((__IO uint8_t *)&SUBGHZSPI->DR); - 8003cce: 4b17 ldr r3, [pc, #92] ; (8003d2c ) - 8003cd0: 613b str r3, [r7, #16] + 8003ada: 4b17 ldr r3, [pc, #92] ; (8003b38 ) + 8003adc: 613b str r3, [r7, #16] *spidr = Data; - 8003cd2: 693b ldr r3, [r7, #16] - 8003cd4: 78fa ldrb r2, [r7, #3] - 8003cd6: 701a strb r2, [r3, #0] + 8003ade: 693b ldr r3, [r7, #16] + 8003ae0: 78fa ldrb r2, [r7, #3] + 8003ae2: 701a strb r2, [r3, #0] *((__IO uint8_t *)&SUBGHZSPI->DR) = Data; #endif /* __GNUC__ */ /* Handle Rx transmission from SUBGHZSPI peripheral to Radio ****************/ /* Initialize Timeout */ count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; - 8003cd8: 4b12 ldr r3, [pc, #72] ; (8003d24 ) - 8003cda: 681a ldr r2, [r3, #0] - 8003cdc: 4613 mov r3, r2 - 8003cde: 00db lsls r3, r3, #3 - 8003ce0: 1a9b subs r3, r3, r2 - 8003ce2: 009b lsls r3, r3, #2 - 8003ce4: 0cdb lsrs r3, r3, #19 - 8003ce6: 2264 movs r2, #100 ; 0x64 - 8003ce8: fb02 f303 mul.w r3, r2, r3 - 8003cec: 60fb str r3, [r7, #12] + 8003ae4: 4b12 ldr r3, [pc, #72] ; (8003b30 ) + 8003ae6: 681a ldr r2, [r3, #0] + 8003ae8: 4613 mov r3, r2 + 8003aea: 00db lsls r3, r3, #3 + 8003aec: 1a9b subs r3, r3, r2 + 8003aee: 009b lsls r3, r3, #2 + 8003af0: 0cdb lsrs r3, r3, #19 + 8003af2: 2264 movs r2, #100 ; 0x64 + 8003af4: fb02 f303 mul.w r3, r2, r3 + 8003af8: 60fb str r3, [r7, #12] /* Wait until RXNE flag is set */ do { if (count == 0U) - 8003cee: 68fb ldr r3, [r7, #12] - 8003cf0: 2b00 cmp r3, #0 - 8003cf2: d105 bne.n 8003d00 + 8003afa: 68fb ldr r3, [r7, #12] + 8003afc: 2b00 cmp r3, #0 + 8003afe: d105 bne.n 8003b0c { status = HAL_ERROR; - 8003cf4: 2301 movs r3, #1 - 8003cf6: 75fb strb r3, [r7, #23] + 8003b00: 2301 movs r3, #1 + 8003b02: 75fb strb r3, [r7, #23] hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; - 8003cf8: 687b ldr r3, [r7, #4] - 8003cfa: 2201 movs r2, #1 - 8003cfc: 609a str r2, [r3, #8] + 8003b04: 687b ldr r3, [r7, #4] + 8003b06: 2201 movs r2, #1 + 8003b08: 609a str r2, [r3, #8] break; - 8003cfe: e008 b.n 8003d12 + 8003b0a: e008 b.n 8003b1e } count--; - 8003d00: 68fb ldr r3, [r7, #12] - 8003d02: 3b01 subs r3, #1 - 8003d04: 60fb str r3, [r7, #12] + 8003b0c: 68fb ldr r3, [r7, #12] + 8003b0e: 3b01 subs r3, #1 + 8003b10: 60fb str r3, [r7, #12] } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_RXNE) != (SPI_SR_RXNE)); - 8003d06: 4b08 ldr r3, [pc, #32] ; (8003d28 ) - 8003d08: 689b ldr r3, [r3, #8] - 8003d0a: f003 0301 and.w r3, r3, #1 - 8003d0e: 2b01 cmp r3, #1 - 8003d10: d1ed bne.n 8003cee + 8003b12: 4b08 ldr r3, [pc, #32] ; (8003b34 ) + 8003b14: 689b ldr r3, [r3, #8] + 8003b16: f003 0301 and.w r3, r3, #1 + 8003b1a: 2b01 cmp r3, #1 + 8003b1c: d1ed bne.n 8003afa /* Flush Rx data */ READ_REG(SUBGHZSPI->DR); - 8003d12: 4b05 ldr r3, [pc, #20] ; (8003d28 ) - 8003d14: 68db ldr r3, [r3, #12] + 8003b1e: 4b05 ldr r3, [pc, #20] ; (8003b34 ) + 8003b20: 68db ldr r3, [r3, #12] return status; - 8003d16: 7dfb ldrb r3, [r7, #23] -} - 8003d18: 4618 mov r0, r3 - 8003d1a: 371c adds r7, #28 - 8003d1c: 46bd mov sp, r7 - 8003d1e: bc80 pop {r7} - 8003d20: 4770 bx lr - 8003d22: bf00 nop - 8003d24: 20000008 .word 0x20000008 - 8003d28: 58010000 .word 0x58010000 - 8003d2c: 5801000c .word 0x5801000c - -08003d30 : + 8003b22: 7dfb ldrb r3, [r7, #23] +} + 8003b24: 4618 mov r0, r3 + 8003b26: 371c adds r7, #28 + 8003b28: 46bd mov sp, r7 + 8003b2a: bc80 pop {r7} + 8003b2c: 4770 bx lr + 8003b2e: bf00 nop + 8003b30: 20000000 .word 0x20000000 + 8003b34: 58010000 .word 0x58010000 + 8003b38: 5801000c .word 0x5801000c + +08003b3c : * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains * the handle information for SUBGHZ module. * @retval HAL status */ HAL_StatusTypeDef SUBGHZ_CheckDeviceReady(SUBGHZ_HandleTypeDef *hsubghz) { - 8003d30: b580 push {r7, lr} - 8003d32: b084 sub sp, #16 - 8003d34: af00 add r7, sp, #0 - 8003d36: 6078 str r0, [r7, #4] + 8003b3c: b580 push {r7, lr} + 8003b3e: b084 sub sp, #16 + 8003b40: af00 add r7, sp, #0 + 8003b42: 6078 str r0, [r7, #4] __IO uint32_t count; /* Wakeup radio in case of sleep mode: Select-Unselect radio */ if (hsubghz->DeepSleep == SUBGHZ_DEEP_SLEEP_ENABLE) - 8003d38: 687b ldr r3, [r7, #4] - 8003d3a: 791b ldrb r3, [r3, #4] - 8003d3c: 2b01 cmp r3, #1 - 8003d3e: d111 bne.n 8003d64 + 8003b44: 687b ldr r3, [r7, #4] + 8003b46: 791b ldrb r3, [r3, #4] + 8003b48: 2b01 cmp r3, #1 + 8003b4a: d111 bne.n 8003b70 { /* Initialize NSS switch Delay */ count = SUBGHZ_NSS_LOOP_TIME; - 8003d40: 4b0c ldr r3, [pc, #48] ; (8003d74 ) - 8003d42: 681a ldr r2, [r3, #0] - 8003d44: 4613 mov r3, r2 - 8003d46: 005b lsls r3, r3, #1 - 8003d48: 4413 add r3, r2 - 8003d4a: 00db lsls r3, r3, #3 - 8003d4c: 0c1b lsrs r3, r3, #16 - 8003d4e: 60fb str r3, [r7, #12] + 8003b4c: 4b0c ldr r3, [pc, #48] ; (8003b80 ) + 8003b4e: 681a ldr r2, [r3, #0] + 8003b50: 4613 mov r3, r2 + 8003b52: 005b lsls r3, r3, #1 + 8003b54: 4413 add r3, r2 + 8003b56: 00db lsls r3, r3, #3 + 8003b58: 0c1b lsrs r3, r3, #16 + 8003b5a: 60fb str r3, [r7, #12] /* NSS = 0; */ LL_PWR_SelectSUBGHZSPI_NSS(); - 8003d50: f7ff fe3e bl 80039d0 + 8003b5c: f7ff fe3e bl 80037dc /* Wait Radio wakeup */ do { count--; - 8003d54: 68fb ldr r3, [r7, #12] - 8003d56: 3b01 subs r3, #1 - 8003d58: 60fb str r3, [r7, #12] + 8003b60: 68fb ldr r3, [r7, #12] + 8003b62: 3b01 subs r3, #1 + 8003b64: 60fb str r3, [r7, #12] } while (count != 0UL); - 8003d5a: 68fb ldr r3, [r7, #12] - 8003d5c: 2b00 cmp r3, #0 - 8003d5e: d1f9 bne.n 8003d54 + 8003b66: 68fb ldr r3, [r7, #12] + 8003b68: 2b00 cmp r3, #0 + 8003b6a: d1f9 bne.n 8003b60 /* NSS = 1 */ LL_PWR_UnselectSUBGHZSPI_NSS(); - 8003d60: f7ff fe26 bl 80039b0 + 8003b6c: f7ff fe26 bl 80037bc } return (SUBGHZ_WaitOnBusy(hsubghz)); - 8003d64: 6878 ldr r0, [r7, #4] - 8003d66: f000 f807 bl 8003d78 - 8003d6a: 4603 mov r3, r0 + 8003b70: 6878 ldr r0, [r7, #4] + 8003b72: f000 f807 bl 8003b84 + 8003b76: 4603 mov r3, r0 } - 8003d6c: 4618 mov r0, r3 - 8003d6e: 3710 adds r7, #16 - 8003d70: 46bd mov sp, r7 - 8003d72: bd80 pop {r7, pc} - 8003d74: 20000008 .word 0x20000008 + 8003b78: 4618 mov r0, r3 + 8003b7a: 3710 adds r7, #16 + 8003b7c: 46bd mov sp, r7 + 8003b7e: bd80 pop {r7, pc} + 8003b80: 20000000 .word 0x20000000 -08003d78 : +08003b84 : * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains * the handle information for SUBGHZ module. * @retval HAL status */ HAL_StatusTypeDef SUBGHZ_WaitOnBusy(SUBGHZ_HandleTypeDef *hsubghz) { - 8003d78: b580 push {r7, lr} - 8003d7a: b086 sub sp, #24 - 8003d7c: af00 add r7, sp, #0 - 8003d7e: 6078 str r0, [r7, #4] + 8003b84: b580 push {r7, lr} + 8003b86: b086 sub sp, #24 + 8003b88: af00 add r7, sp, #0 + 8003b8a: 6078 str r0, [r7, #4] HAL_StatusTypeDef status; __IO uint32_t count; uint32_t mask; status = HAL_OK; - 8003d80: 2300 movs r3, #0 - 8003d82: 75fb strb r3, [r7, #23] + 8003b8c: 2300 movs r3, #0 + 8003b8e: 75fb strb r3, [r7, #23] count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_RFBUSY_LOOP_TIME; - 8003d84: 4b12 ldr r3, [pc, #72] ; (8003dd0 ) - 8003d86: 681a ldr r2, [r3, #0] - 8003d88: 4613 mov r3, r2 - 8003d8a: 005b lsls r3, r3, #1 - 8003d8c: 4413 add r3, r2 - 8003d8e: 00db lsls r3, r3, #3 - 8003d90: 0d1b lsrs r3, r3, #20 - 8003d92: 2264 movs r2, #100 ; 0x64 - 8003d94: fb02 f303 mul.w r3, r2, r3 - 8003d98: 60fb str r3, [r7, #12] + 8003b90: 4b12 ldr r3, [pc, #72] ; (8003bdc ) + 8003b92: 681a ldr r2, [r3, #0] + 8003b94: 4613 mov r3, r2 + 8003b96: 005b lsls r3, r3, #1 + 8003b98: 4413 add r3, r2 + 8003b9a: 00db lsls r3, r3, #3 + 8003b9c: 0d1b lsrs r3, r3, #20 + 8003b9e: 2264 movs r2, #100 ; 0x64 + 8003ba0: fb02 f303 mul.w r3, r2, r3 + 8003ba4: 60fb str r3, [r7, #12] /* Wait until Busy signal is set */ do { mask = LL_PWR_IsActiveFlag_RFBUSYMS(); - 8003d9a: f7ff fe47 bl 8003a2c - 8003d9e: 6138 str r0, [r7, #16] + 8003ba6: f7ff fe47 bl 8003838 + 8003baa: 6138 str r0, [r7, #16] if (count == 0U) - 8003da0: 68fb ldr r3, [r7, #12] - 8003da2: 2b00 cmp r3, #0 - 8003da4: d105 bne.n 8003db2 + 8003bac: 68fb ldr r3, [r7, #12] + 8003bae: 2b00 cmp r3, #0 + 8003bb0: d105 bne.n 8003bbe { status = HAL_ERROR; - 8003da6: 2301 movs r3, #1 - 8003da8: 75fb strb r3, [r7, #23] + 8003bb2: 2301 movs r3, #1 + 8003bb4: 75fb strb r3, [r7, #23] hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_RF_BUSY; - 8003daa: 687b ldr r3, [r7, #4] - 8003dac: 2202 movs r2, #2 - 8003dae: 609a str r2, [r3, #8] + 8003bb6: 687b ldr r3, [r7, #4] + 8003bb8: 2202 movs r2, #2 + 8003bba: 609a str r2, [r3, #8] break; - 8003db0: e009 b.n 8003dc6 + 8003bbc: e009 b.n 8003bd2 } count--; - 8003db2: 68fb ldr r3, [r7, #12] - 8003db4: 3b01 subs r3, #1 - 8003db6: 60fb str r3, [r7, #12] + 8003bbe: 68fb ldr r3, [r7, #12] + 8003bc0: 3b01 subs r3, #1 + 8003bc2: 60fb str r3, [r7, #12] } while ((LL_PWR_IsActiveFlag_RFBUSYS()& mask) == 1UL); - 8003db8: f7ff fe26 bl 8003a08 - 8003dbc: 4602 mov r2, r0 - 8003dbe: 693b ldr r3, [r7, #16] - 8003dc0: 4013 ands r3, r2 - 8003dc2: 2b01 cmp r3, #1 - 8003dc4: d0e9 beq.n 8003d9a + 8003bc4: f7ff fe26 bl 8003814 + 8003bc8: 4602 mov r2, r0 + 8003bca: 693b ldr r3, [r7, #16] + 8003bcc: 4013 ands r3, r2 + 8003bce: 2b01 cmp r3, #1 + 8003bd0: d0e9 beq.n 8003ba6 return status; - 8003dc6: 7dfb ldrb r3, [r7, #23] + 8003bd2: 7dfb ldrb r3, [r7, #23] } - 8003dc8: 4618 mov r0, r3 - 8003dca: 3718 adds r7, #24 - 8003dcc: 46bd mov sp, r7 - 8003dce: bd80 pop {r7, pc} - 8003dd0: 20000008 .word 0x20000008 + 8003bd4: 4618 mov r0, r3 + 8003bd6: 3718 adds r7, #24 + 8003bd8: 46bd mov sp, r7 + 8003bda: bd80 pop {r7, pc} + 8003bdc: 20000000 .word 0x20000000 -08003dd4 : +08003be0 : { - 8003dd4: b480 push {r7} - 8003dd6: b083 sub sp, #12 - 8003dd8: af00 add r7, sp, #0 - 8003dda: 6078 str r0, [r7, #4] + 8003be0: b480 push {r7} + 8003be2: b083 sub sp, #12 + 8003be4: af00 add r7, sp, #0 + 8003be6: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16)); - 8003ddc: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8003de0: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 - 8003de4: 687b ldr r3, [r7, #4] - 8003de6: 401a ands r2, r3 - 8003de8: 687b ldr r3, [r7, #4] - 8003dea: 041b lsls r3, r3, #16 - 8003dec: 4313 orrs r3, r2 -} - 8003dee: 4618 mov r0, r3 - 8003df0: 370c adds r7, #12 - 8003df2: 46bd mov sp, r7 - 8003df4: bc80 pop {r7} - 8003df6: 4770 bx lr - -08003df8 : -{ - 8003df8: b480 push {r7} - 8003dfa: b083 sub sp, #12 - 8003dfc: af00 add r7, sp, #0 - 8003dfe: 6078 str r0, [r7, #4] + 8003be8: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003bec: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 + 8003bf0: 687b ldr r3, [r7, #4] + 8003bf2: 401a ands r2, r3 + 8003bf4: 687b ldr r3, [r7, #4] + 8003bf6: 041b lsls r3, r3, #16 + 8003bf8: 4313 orrs r3, r2 +} + 8003bfa: 4618 mov r0, r3 + 8003bfc: 370c adds r7, #12 + 8003bfe: 46bd mov sp, r7 + 8003c00: bc80 pop {r7} + 8003c02: 4770 bx lr + +08003c04 : +{ + 8003c04: b480 push {r7} + 8003c06: b083 sub sp, #12 + 8003c08: af00 add r7, sp, #0 + 8003c0a: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx)); - 8003e00: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 - 8003e04: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 - 8003e08: 687b ldr r3, [r7, #4] - 8003e0a: 4013 ands r3, r2 -} - 8003e0c: 4618 mov r0, r3 - 8003e0e: 370c adds r7, #12 - 8003e10: 46bd mov sp, r7 - 8003e12: bc80 pop {r7} - 8003e14: 4770 bx lr - -08003e16 : + 8003c0c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003c10: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 + 8003c14: 687b ldr r3, [r7, #4] + 8003c16: 4013 ands r3, r2 +} + 8003c18: 4618 mov r0, r3 + 8003c1a: 370c adds r7, #12 + 8003c1c: 46bd mov sp, r7 + 8003c1e: bc80 pop {r7} + 8003c20: 4770 bx lr + +08003c22 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { - 8003e16: b580 push {r7, lr} - 8003e18: b082 sub sp, #8 - 8003e1a: af00 add r7, sp, #0 - 8003e1c: 6078 str r0, [r7, #4] + 8003c22: b580 push {r7, lr} + 8003c24: b082 sub sp, #8 + 8003c26: af00 add r7, sp, #0 + 8003c28: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) - 8003e1e: 687b ldr r3, [r7, #4] - 8003e20: 2b00 cmp r3, #0 - 8003e22: d101 bne.n 8003e28 + 8003c2a: 687b ldr r3, [r7, #4] + 8003c2c: 2b00 cmp r3, #0 + 8003c2e: d101 bne.n 8003c34 { return HAL_ERROR; - 8003e24: 2301 movs r3, #1 - 8003e26: e042 b.n 8003eae + 8003c30: 2301 movs r3, #1 + 8003c32: e042 b.n 8003cba { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) - 8003e28: 687b ldr r3, [r7, #4] - 8003e2a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8003e2e: 2b00 cmp r3, #0 - 8003e30: d106 bne.n 8003e40 + 8003c34: 687b ldr r3, [r7, #4] + 8003c36: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8003c3a: 2b00 cmp r3, #0 + 8003c3c: d106 bne.n 8003c4c { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - 8003e32: 687b ldr r3, [r7, #4] - 8003e34: 2200 movs r2, #0 - 8003e36: f883 2084 strb.w r2, [r3, #132] ; 0x84 + 8003c3e: 687b ldr r3, [r7, #4] + 8003c40: 2200 movs r2, #0 + 8003c42: f883 2084 strb.w r2, [r3, #132] ; 0x84 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); - 8003e3a: 6878 ldr r0, [r7, #4] - 8003e3c: f7fd fc24 bl 8001688 + 8003c46: 6878 ldr r0, [r7, #4] + 8003c48: f7fd fc24 bl 8001494 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; - 8003e40: 687b ldr r3, [r7, #4] - 8003e42: 2224 movs r2, #36 ; 0x24 - 8003e44: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + 8003c4c: 687b ldr r3, [r7, #4] + 8003c4e: 2224 movs r2, #36 ; 0x24 + 8003c50: f8c3 2088 str.w r2, [r3, #136] ; 0x88 __HAL_UART_DISABLE(huart); - 8003e48: 687b ldr r3, [r7, #4] - 8003e4a: 681b ldr r3, [r3, #0] - 8003e4c: 681a ldr r2, [r3, #0] - 8003e4e: 687b ldr r3, [r7, #4] - 8003e50: 681b ldr r3, [r3, #0] - 8003e52: f022 0201 bic.w r2, r2, #1 - 8003e56: 601a str r2, [r3, #0] + 8003c54: 687b ldr r3, [r7, #4] + 8003c56: 681b ldr r3, [r3, #0] + 8003c58: 681a ldr r2, [r3, #0] + 8003c5a: 687b ldr r3, [r7, #4] + 8003c5c: 681b ldr r3, [r3, #0] + 8003c5e: f022 0201 bic.w r2, r2, #1 + 8003c62: 601a str r2, [r3, #0] /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) - 8003e58: 6878 ldr r0, [r7, #4] - 8003e5a: f000 f82d bl 8003eb8 - 8003e5e: 4603 mov r3, r0 - 8003e60: 2b01 cmp r3, #1 - 8003e62: d101 bne.n 8003e68 + 8003c64: 6878 ldr r0, [r7, #4] + 8003c66: f000 f82d bl 8003cc4 + 8003c6a: 4603 mov r3, r0 + 8003c6c: 2b01 cmp r3, #1 + 8003c6e: d101 bne.n 8003c74 { return HAL_ERROR; - 8003e64: 2301 movs r3, #1 - 8003e66: e022 b.n 8003eae + 8003c70: 2301 movs r3, #1 + 8003c72: e022 b.n 8003cba } if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - 8003e68: 687b ldr r3, [r7, #4] - 8003e6a: 6a9b ldr r3, [r3, #40] ; 0x28 - 8003e6c: 2b00 cmp r3, #0 - 8003e6e: d002 beq.n 8003e76 + 8003c74: 687b ldr r3, [r7, #4] + 8003c76: 6a9b ldr r3, [r3, #40] ; 0x28 + 8003c78: 2b00 cmp r3, #0 + 8003c7a: d002 beq.n 8003c82 { UART_AdvFeatureConfig(huart); - 8003e70: 6878 ldr r0, [r7, #4] - 8003e72: f000 fa95 bl 80043a0 + 8003c7c: 6878 ldr r0, [r7, #4] + 8003c7e: f000 fa95 bl 80041ac } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - 8003e76: 687b ldr r3, [r7, #4] - 8003e78: 681b ldr r3, [r3, #0] - 8003e7a: 685a ldr r2, [r3, #4] - 8003e7c: 687b ldr r3, [r7, #4] - 8003e7e: 681b ldr r3, [r3, #0] - 8003e80: f422 4290 bic.w r2, r2, #18432 ; 0x4800 - 8003e84: 605a str r2, [r3, #4] + 8003c82: 687b ldr r3, [r7, #4] + 8003c84: 681b ldr r3, [r3, #0] + 8003c86: 685a ldr r2, [r3, #4] + 8003c88: 687b ldr r3, [r7, #4] + 8003c8a: 681b ldr r3, [r3, #0] + 8003c8c: f422 4290 bic.w r2, r2, #18432 ; 0x4800 + 8003c90: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - 8003e86: 687b ldr r3, [r7, #4] - 8003e88: 681b ldr r3, [r3, #0] - 8003e8a: 689a ldr r2, [r3, #8] - 8003e8c: 687b ldr r3, [r7, #4] - 8003e8e: 681b ldr r3, [r3, #0] - 8003e90: f022 022a bic.w r2, r2, #42 ; 0x2a - 8003e94: 609a str r2, [r3, #8] + 8003c92: 687b ldr r3, [r7, #4] + 8003c94: 681b ldr r3, [r3, #0] + 8003c96: 689a ldr r2, [r3, #8] + 8003c98: 687b ldr r3, [r7, #4] + 8003c9a: 681b ldr r3, [r3, #0] + 8003c9c: f022 022a bic.w r2, r2, #42 ; 0x2a + 8003ca0: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); - 8003e96: 687b ldr r3, [r7, #4] - 8003e98: 681b ldr r3, [r3, #0] - 8003e9a: 681a ldr r2, [r3, #0] - 8003e9c: 687b ldr r3, [r7, #4] - 8003e9e: 681b ldr r3, [r3, #0] - 8003ea0: f042 0201 orr.w r2, r2, #1 - 8003ea4: 601a str r2, [r3, #0] + 8003ca2: 687b ldr r3, [r7, #4] + 8003ca4: 681b ldr r3, [r3, #0] + 8003ca6: 681a ldr r2, [r3, #0] + 8003ca8: 687b ldr r3, [r7, #4] + 8003caa: 681b ldr r3, [r3, #0] + 8003cac: f042 0201 orr.w r2, r2, #1 + 8003cb0: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); - 8003ea6: 6878 ldr r0, [r7, #4] - 8003ea8: f000 fb1b bl 80044e2 - 8003eac: 4603 mov r3, r0 -} - 8003eae: 4618 mov r0, r3 - 8003eb0: 3708 adds r7, #8 - 8003eb2: 46bd mov sp, r7 - 8003eb4: bd80 pop {r7, pc} + 8003cb2: 6878 ldr r0, [r7, #4] + 8003cb4: f000 fb1b bl 80042ee + 8003cb8: 4603 mov r3, r0 +} + 8003cba: 4618 mov r0, r3 + 8003cbc: 3708 adds r7, #8 + 8003cbe: 46bd mov sp, r7 + 8003cc0: bd80 pop {r7, pc} ... -08003eb8 : +08003cc4 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { - 8003eb8: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} - 8003ebc: b08c sub sp, #48 ; 0x30 - 8003ebe: af00 add r7, sp, #0 - 8003ec0: 6178 str r0, [r7, #20] + 8003cc4: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8003cc8: b08c sub sp, #48 ; 0x30 + 8003cca: af00 add r7, sp, #0 + 8003ccc: 6178 str r0, [r7, #20] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; - 8003ec2: 2300 movs r3, #0 - 8003ec4: f887 302a strb.w r3, [r7, #42] ; 0x2a + 8003cce: 2300 movs r3, #0 + 8003cd0: f887 302a strb.w r3, [r7, #42] ; 0x2a * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - 8003ec8: 697b ldr r3, [r7, #20] - 8003eca: 689a ldr r2, [r3, #8] - 8003ecc: 697b ldr r3, [r7, #20] - 8003ece: 691b ldr r3, [r3, #16] - 8003ed0: 431a orrs r2, r3 - 8003ed2: 697b ldr r3, [r7, #20] - 8003ed4: 695b ldr r3, [r3, #20] - 8003ed6: 431a orrs r2, r3 - 8003ed8: 697b ldr r3, [r7, #20] - 8003eda: 69db ldr r3, [r3, #28] - 8003edc: 4313 orrs r3, r2 - 8003ede: 62fb str r3, [r7, #44] ; 0x2c + 8003cd4: 697b ldr r3, [r7, #20] + 8003cd6: 689a ldr r2, [r3, #8] + 8003cd8: 697b ldr r3, [r7, #20] + 8003cda: 691b ldr r3, [r3, #16] + 8003cdc: 431a orrs r2, r3 + 8003cde: 697b ldr r3, [r7, #20] + 8003ce0: 695b ldr r3, [r3, #20] + 8003ce2: 431a orrs r2, r3 + 8003ce4: 697b ldr r3, [r7, #20] + 8003ce6: 69db ldr r3, [r3, #28] + 8003ce8: 4313 orrs r3, r2 + 8003cea: 62fb str r3, [r7, #44] ; 0x2c MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - 8003ee0: 697b ldr r3, [r7, #20] - 8003ee2: 681b ldr r3, [r3, #0] - 8003ee4: 681a ldr r2, [r3, #0] - 8003ee6: 4b94 ldr r3, [pc, #592] ; (8004138 ) - 8003ee8: 4013 ands r3, r2 - 8003eea: 697a ldr r2, [r7, #20] - 8003eec: 6812 ldr r2, [r2, #0] - 8003eee: 6af9 ldr r1, [r7, #44] ; 0x2c - 8003ef0: 430b orrs r3, r1 - 8003ef2: 6013 str r3, [r2, #0] + 8003cec: 697b ldr r3, [r7, #20] + 8003cee: 681b ldr r3, [r3, #0] + 8003cf0: 681a ldr r2, [r3, #0] + 8003cf2: 4b94 ldr r3, [pc, #592] ; (8003f44 ) + 8003cf4: 4013 ands r3, r2 + 8003cf6: 697a ldr r2, [r7, #20] + 8003cf8: 6812 ldr r2, [r2, #0] + 8003cfa: 6af9 ldr r1, [r7, #44] ; 0x2c + 8003cfc: 430b orrs r3, r1 + 8003cfe: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - 8003ef4: 697b ldr r3, [r7, #20] - 8003ef6: 681b ldr r3, [r3, #0] - 8003ef8: 685b ldr r3, [r3, #4] - 8003efa: f423 5140 bic.w r1, r3, #12288 ; 0x3000 - 8003efe: 697b ldr r3, [r7, #20] - 8003f00: 68da ldr r2, [r3, #12] - 8003f02: 697b ldr r3, [r7, #20] - 8003f04: 681b ldr r3, [r3, #0] - 8003f06: 430a orrs r2, r1 - 8003f08: 605a str r2, [r3, #4] + 8003d00: 697b ldr r3, [r7, #20] + 8003d02: 681b ldr r3, [r3, #0] + 8003d04: 685b ldr r3, [r3, #4] + 8003d06: f423 5140 bic.w r1, r3, #12288 ; 0x3000 + 8003d0a: 697b ldr r3, [r7, #20] + 8003d0c: 68da ldr r2, [r3, #12] + 8003d0e: 697b ldr r3, [r7, #20] + 8003d10: 681b ldr r3, [r3, #0] + 8003d12: 430a orrs r2, r1 + 8003d14: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; - 8003f0a: 697b ldr r3, [r7, #20] - 8003f0c: 699b ldr r3, [r3, #24] - 8003f0e: 62fb str r3, [r7, #44] ; 0x2c + 8003d16: 697b ldr r3, [r7, #20] + 8003d18: 699b ldr r3, [r3, #24] + 8003d1a: 62fb str r3, [r7, #44] ; 0x2c if (!(UART_INSTANCE_LOWPOWER(huart))) - 8003f10: 697b ldr r3, [r7, #20] - 8003f12: 681b ldr r3, [r3, #0] - 8003f14: 4a89 ldr r2, [pc, #548] ; (800413c ) - 8003f16: 4293 cmp r3, r2 - 8003f18: d004 beq.n 8003f24 + 8003d1c: 697b ldr r3, [r7, #20] + 8003d1e: 681b ldr r3, [r3, #0] + 8003d20: 4a89 ldr r2, [pc, #548] ; (8003f48 ) + 8003d22: 4293 cmp r3, r2 + 8003d24: d004 beq.n 8003d30 { tmpreg |= huart->Init.OneBitSampling; - 8003f1a: 697b ldr r3, [r7, #20] - 8003f1c: 6a1b ldr r3, [r3, #32] - 8003f1e: 6afa ldr r2, [r7, #44] ; 0x2c - 8003f20: 4313 orrs r3, r2 - 8003f22: 62fb str r3, [r7, #44] ; 0x2c + 8003d26: 697b ldr r3, [r7, #20] + 8003d28: 6a1b ldr r3, [r3, #32] + 8003d2a: 6afa ldr r2, [r7, #44] ; 0x2c + 8003d2c: 4313 orrs r3, r2 + 8003d2e: 62fb str r3, [r7, #44] ; 0x2c } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); - 8003f24: 697b ldr r3, [r7, #20] - 8003f26: 681b ldr r3, [r3, #0] - 8003f28: 689b ldr r3, [r3, #8] - 8003f2a: f023 436e bic.w r3, r3, #3992977408 ; 0xee000000 - 8003f2e: f423 6330 bic.w r3, r3, #2816 ; 0xb00 - 8003f32: 697a ldr r2, [r7, #20] - 8003f34: 6812 ldr r2, [r2, #0] - 8003f36: 6af9 ldr r1, [r7, #44] ; 0x2c - 8003f38: 430b orrs r3, r1 - 8003f3a: 6093 str r3, [r2, #8] + 8003d30: 697b ldr r3, [r7, #20] + 8003d32: 681b ldr r3, [r3, #0] + 8003d34: 689b ldr r3, [r3, #8] + 8003d36: f023 436e bic.w r3, r3, #3992977408 ; 0xee000000 + 8003d3a: f423 6330 bic.w r3, r3, #2816 ; 0xb00 + 8003d3e: 697a ldr r2, [r7, #20] + 8003d40: 6812 ldr r2, [r2, #0] + 8003d42: 6af9 ldr r1, [r7, #44] ; 0x2c + 8003d44: 430b orrs r3, r1 + 8003d46: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); - 8003f3c: 697b ldr r3, [r7, #20] - 8003f3e: 681b ldr r3, [r3, #0] - 8003f40: 6adb ldr r3, [r3, #44] ; 0x2c - 8003f42: f023 010f bic.w r1, r3, #15 - 8003f46: 697b ldr r3, [r7, #20] - 8003f48: 6a5a ldr r2, [r3, #36] ; 0x24 - 8003f4a: 697b ldr r3, [r7, #20] - 8003f4c: 681b ldr r3, [r3, #0] - 8003f4e: 430a orrs r2, r1 - 8003f50: 62da str r2, [r3, #44] ; 0x2c + 8003d48: 697b ldr r3, [r7, #20] + 8003d4a: 681b ldr r3, [r3, #0] + 8003d4c: 6adb ldr r3, [r3, #44] ; 0x2c + 8003d4e: f023 010f bic.w r1, r3, #15 + 8003d52: 697b ldr r3, [r7, #20] + 8003d54: 6a5a ldr r2, [r3, #36] ; 0x24 + 8003d56: 697b ldr r3, [r7, #20] + 8003d58: 681b ldr r3, [r3, #0] + 8003d5a: 430a orrs r2, r1 + 8003d5c: 62da str r2, [r3, #44] ; 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); - 8003f52: 697b ldr r3, [r7, #20] - 8003f54: 681b ldr r3, [r3, #0] - 8003f56: 4a7a ldr r2, [pc, #488] ; (8004140 ) - 8003f58: 4293 cmp r3, r2 - 8003f5a: d127 bne.n 8003fac - 8003f5c: 2003 movs r0, #3 - 8003f5e: f7ff ff39 bl 8003dd4 - 8003f62: 4603 mov r3, r0 - 8003f64: f5a3 3340 sub.w r3, r3, #196608 ; 0x30000 - 8003f68: 2b03 cmp r3, #3 - 8003f6a: d81b bhi.n 8003fa4 - 8003f6c: a201 add r2, pc, #4 ; (adr r2, 8003f74 ) - 8003f6e: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8003f72: bf00 nop - 8003f74: 08003f85 .word 0x08003f85 - 8003f78: 08003f95 .word 0x08003f95 - 8003f7c: 08003f8d .word 0x08003f8d - 8003f80: 08003f9d .word 0x08003f9d - 8003f84: 2301 movs r3, #1 - 8003f86: f887 302b strb.w r3, [r7, #43] ; 0x2b - 8003f8a: e080 b.n 800408e - 8003f8c: 2302 movs r3, #2 - 8003f8e: f887 302b strb.w r3, [r7, #43] ; 0x2b - 8003f92: e07c b.n 800408e - 8003f94: 2304 movs r3, #4 - 8003f96: f887 302b strb.w r3, [r7, #43] ; 0x2b - 8003f9a: e078 b.n 800408e - 8003f9c: 2308 movs r3, #8 - 8003f9e: f887 302b strb.w r3, [r7, #43] ; 0x2b - 8003fa2: e074 b.n 800408e - 8003fa4: 2310 movs r3, #16 - 8003fa6: f887 302b strb.w r3, [r7, #43] ; 0x2b - 8003faa: e070 b.n 800408e - 8003fac: 697b ldr r3, [r7, #20] - 8003fae: 681b ldr r3, [r3, #0] - 8003fb0: 4a64 ldr r2, [pc, #400] ; (8004144 ) - 8003fb2: 4293 cmp r3, r2 - 8003fb4: d138 bne.n 8004028 - 8003fb6: 200c movs r0, #12 - 8003fb8: f7ff ff0c bl 8003dd4 - 8003fbc: 4603 mov r3, r0 - 8003fbe: f5a3 2340 sub.w r3, r3, #786432 ; 0xc0000 - 8003fc2: 2b0c cmp r3, #12 - 8003fc4: d82c bhi.n 8004020 - 8003fc6: a201 add r2, pc, #4 ; (adr r2, 8003fcc ) - 8003fc8: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8003fcc: 08004001 .word 0x08004001 - 8003fd0: 08004021 .word 0x08004021 - 8003fd4: 08004021 .word 0x08004021 - 8003fd8: 08004021 .word 0x08004021 - 8003fdc: 08004011 .word 0x08004011 - 8003fe0: 08004021 .word 0x08004021 - 8003fe4: 08004021 .word 0x08004021 - 8003fe8: 08004021 .word 0x08004021 - 8003fec: 08004009 .word 0x08004009 - 8003ff0: 08004021 .word 0x08004021 - 8003ff4: 08004021 .word 0x08004021 - 8003ff8: 08004021 .word 0x08004021 - 8003ffc: 08004019 .word 0x08004019 - 8004000: 2300 movs r3, #0 - 8004002: f887 302b strb.w r3, [r7, #43] ; 0x2b - 8004006: e042 b.n 800408e - 8004008: 2302 movs r3, #2 - 800400a: f887 302b strb.w r3, [r7, #43] ; 0x2b - 800400e: e03e b.n 800408e - 8004010: 2304 movs r3, #4 - 8004012: f887 302b strb.w r3, [r7, #43] ; 0x2b - 8004016: e03a b.n 800408e - 8004018: 2308 movs r3, #8 - 800401a: f887 302b strb.w r3, [r7, #43] ; 0x2b - 800401e: e036 b.n 800408e - 8004020: 2310 movs r3, #16 - 8004022: f887 302b strb.w r3, [r7, #43] ; 0x2b - 8004026: e032 b.n 800408e - 8004028: 697b ldr r3, [r7, #20] - 800402a: 681b ldr r3, [r3, #0] - 800402c: 4a43 ldr r2, [pc, #268] ; (800413c ) - 800402e: 4293 cmp r3, r2 - 8004030: d12a bne.n 8004088 - 8004032: f44f 6040 mov.w r0, #3072 ; 0xc00 - 8004036: f7ff fedf bl 8003df8 - 800403a: 4603 mov r3, r0 - 800403c: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 - 8004040: d01a beq.n 8004078 - 8004042: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 - 8004046: d81b bhi.n 8004080 - 8004048: f5b3 6f00 cmp.w r3, #2048 ; 0x800 - 800404c: d00c beq.n 8004068 - 800404e: f5b3 6f00 cmp.w r3, #2048 ; 0x800 - 8004052: d815 bhi.n 8004080 - 8004054: 2b00 cmp r3, #0 - 8004056: d003 beq.n 8004060 - 8004058: f5b3 6f80 cmp.w r3, #1024 ; 0x400 - 800405c: d008 beq.n 8004070 - 800405e: e00f b.n 8004080 - 8004060: 2300 movs r3, #0 - 8004062: f887 302b strb.w r3, [r7, #43] ; 0x2b - 8004066: e012 b.n 800408e - 8004068: 2302 movs r3, #2 - 800406a: f887 302b strb.w r3, [r7, #43] ; 0x2b - 800406e: e00e b.n 800408e - 8004070: 2304 movs r3, #4 - 8004072: f887 302b strb.w r3, [r7, #43] ; 0x2b - 8004076: e00a b.n 800408e - 8004078: 2308 movs r3, #8 - 800407a: f887 302b strb.w r3, [r7, #43] ; 0x2b - 800407e: e006 b.n 800408e - 8004080: 2310 movs r3, #16 - 8004082: f887 302b strb.w r3, [r7, #43] ; 0x2b - 8004086: e002 b.n 800408e - 8004088: 2310 movs r3, #16 - 800408a: f887 302b strb.w r3, [r7, #43] ; 0x2b + 8003d5e: 697b ldr r3, [r7, #20] + 8003d60: 681b ldr r3, [r3, #0] + 8003d62: 4a7a ldr r2, [pc, #488] ; (8003f4c ) + 8003d64: 4293 cmp r3, r2 + 8003d66: d127 bne.n 8003db8 + 8003d68: 2003 movs r0, #3 + 8003d6a: f7ff ff39 bl 8003be0 + 8003d6e: 4603 mov r3, r0 + 8003d70: f5a3 3340 sub.w r3, r3, #196608 ; 0x30000 + 8003d74: 2b03 cmp r3, #3 + 8003d76: d81b bhi.n 8003db0 + 8003d78: a201 add r2, pc, #4 ; (adr r2, 8003d80 ) + 8003d7a: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8003d7e: bf00 nop + 8003d80: 08003d91 .word 0x08003d91 + 8003d84: 08003da1 .word 0x08003da1 + 8003d88: 08003d99 .word 0x08003d99 + 8003d8c: 08003da9 .word 0x08003da9 + 8003d90: 2301 movs r3, #1 + 8003d92: f887 302b strb.w r3, [r7, #43] ; 0x2b + 8003d96: e080 b.n 8003e9a + 8003d98: 2302 movs r3, #2 + 8003d9a: f887 302b strb.w r3, [r7, #43] ; 0x2b + 8003d9e: e07c b.n 8003e9a + 8003da0: 2304 movs r3, #4 + 8003da2: f887 302b strb.w r3, [r7, #43] ; 0x2b + 8003da6: e078 b.n 8003e9a + 8003da8: 2308 movs r3, #8 + 8003daa: f887 302b strb.w r3, [r7, #43] ; 0x2b + 8003dae: e074 b.n 8003e9a + 8003db0: 2310 movs r3, #16 + 8003db2: f887 302b strb.w r3, [r7, #43] ; 0x2b + 8003db6: e070 b.n 8003e9a + 8003db8: 697b ldr r3, [r7, #20] + 8003dba: 681b ldr r3, [r3, #0] + 8003dbc: 4a64 ldr r2, [pc, #400] ; (8003f50 ) + 8003dbe: 4293 cmp r3, r2 + 8003dc0: d138 bne.n 8003e34 + 8003dc2: 200c movs r0, #12 + 8003dc4: f7ff ff0c bl 8003be0 + 8003dc8: 4603 mov r3, r0 + 8003dca: f5a3 2340 sub.w r3, r3, #786432 ; 0xc0000 + 8003dce: 2b0c cmp r3, #12 + 8003dd0: d82c bhi.n 8003e2c + 8003dd2: a201 add r2, pc, #4 ; (adr r2, 8003dd8 ) + 8003dd4: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8003dd8: 08003e0d .word 0x08003e0d + 8003ddc: 08003e2d .word 0x08003e2d + 8003de0: 08003e2d .word 0x08003e2d + 8003de4: 08003e2d .word 0x08003e2d + 8003de8: 08003e1d .word 0x08003e1d + 8003dec: 08003e2d .word 0x08003e2d + 8003df0: 08003e2d .word 0x08003e2d + 8003df4: 08003e2d .word 0x08003e2d + 8003df8: 08003e15 .word 0x08003e15 + 8003dfc: 08003e2d .word 0x08003e2d + 8003e00: 08003e2d .word 0x08003e2d + 8003e04: 08003e2d .word 0x08003e2d + 8003e08: 08003e25 .word 0x08003e25 + 8003e0c: 2300 movs r3, #0 + 8003e0e: f887 302b strb.w r3, [r7, #43] ; 0x2b + 8003e12: e042 b.n 8003e9a + 8003e14: 2302 movs r3, #2 + 8003e16: f887 302b strb.w r3, [r7, #43] ; 0x2b + 8003e1a: e03e b.n 8003e9a + 8003e1c: 2304 movs r3, #4 + 8003e1e: f887 302b strb.w r3, [r7, #43] ; 0x2b + 8003e22: e03a b.n 8003e9a + 8003e24: 2308 movs r3, #8 + 8003e26: f887 302b strb.w r3, [r7, #43] ; 0x2b + 8003e2a: e036 b.n 8003e9a + 8003e2c: 2310 movs r3, #16 + 8003e2e: f887 302b strb.w r3, [r7, #43] ; 0x2b + 8003e32: e032 b.n 8003e9a + 8003e34: 697b ldr r3, [r7, #20] + 8003e36: 681b ldr r3, [r3, #0] + 8003e38: 4a43 ldr r2, [pc, #268] ; (8003f48 ) + 8003e3a: 4293 cmp r3, r2 + 8003e3c: d12a bne.n 8003e94 + 8003e3e: f44f 6040 mov.w r0, #3072 ; 0xc00 + 8003e42: f7ff fedf bl 8003c04 + 8003e46: 4603 mov r3, r0 + 8003e48: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 + 8003e4c: d01a beq.n 8003e84 + 8003e4e: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 + 8003e52: d81b bhi.n 8003e8c + 8003e54: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 8003e58: d00c beq.n 8003e74 + 8003e5a: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 8003e5e: d815 bhi.n 8003e8c + 8003e60: 2b00 cmp r3, #0 + 8003e62: d003 beq.n 8003e6c + 8003e64: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8003e68: d008 beq.n 8003e7c + 8003e6a: e00f b.n 8003e8c + 8003e6c: 2300 movs r3, #0 + 8003e6e: f887 302b strb.w r3, [r7, #43] ; 0x2b + 8003e72: e012 b.n 8003e9a + 8003e74: 2302 movs r3, #2 + 8003e76: f887 302b strb.w r3, [r7, #43] ; 0x2b + 8003e7a: e00e b.n 8003e9a + 8003e7c: 2304 movs r3, #4 + 8003e7e: f887 302b strb.w r3, [r7, #43] ; 0x2b + 8003e82: e00a b.n 8003e9a + 8003e84: 2308 movs r3, #8 + 8003e86: f887 302b strb.w r3, [r7, #43] ; 0x2b + 8003e8a: e006 b.n 8003e9a + 8003e8c: 2310 movs r3, #16 + 8003e8e: f887 302b strb.w r3, [r7, #43] ; 0x2b + 8003e92: e002 b.n 8003e9a + 8003e94: 2310 movs r3, #16 + 8003e96: f887 302b strb.w r3, [r7, #43] ; 0x2b /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) - 800408e: 697b ldr r3, [r7, #20] - 8004090: 681b ldr r3, [r3, #0] - 8004092: 4a2a ldr r2, [pc, #168] ; (800413c ) - 8004094: 4293 cmp r3, r2 - 8004096: f040 80a4 bne.w 80041e2 + 8003e9a: 697b ldr r3, [r7, #20] + 8003e9c: 681b ldr r3, [r3, #0] + 8003e9e: 4a2a ldr r2, [pc, #168] ; (8003f48 ) + 8003ea0: 4293 cmp r3, r2 + 8003ea2: f040 80a4 bne.w 8003fee { /* Retrieve frequency clock */ switch (clocksource) - 800409a: f897 302b ldrb.w r3, [r7, #43] ; 0x2b - 800409e: 2b08 cmp r3, #8 - 80040a0: d823 bhi.n 80040ea - 80040a2: a201 add r2, pc, #4 ; (adr r2, 80040a8 ) - 80040a4: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 80040a8: 080040cd .word 0x080040cd - 80040ac: 080040eb .word 0x080040eb - 80040b0: 080040d5 .word 0x080040d5 - 80040b4: 080040eb .word 0x080040eb - 80040b8: 080040db .word 0x080040db - 80040bc: 080040eb .word 0x080040eb - 80040c0: 080040eb .word 0x080040eb - 80040c4: 080040eb .word 0x080040eb - 80040c8: 080040e3 .word 0x080040e3 + 8003ea6: f897 302b ldrb.w r3, [r7, #43] ; 0x2b + 8003eaa: 2b08 cmp r3, #8 + 8003eac: d823 bhi.n 8003ef6 + 8003eae: a201 add r2, pc, #4 ; (adr r2, 8003eb4 ) + 8003eb0: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8003eb4: 08003ed9 .word 0x08003ed9 + 8003eb8: 08003ef7 .word 0x08003ef7 + 8003ebc: 08003ee1 .word 0x08003ee1 + 8003ec0: 08003ef7 .word 0x08003ef7 + 8003ec4: 08003ee7 .word 0x08003ee7 + 8003ec8: 08003ef7 .word 0x08003ef7 + 8003ecc: 08003ef7 .word 0x08003ef7 + 8003ed0: 08003ef7 .word 0x08003ef7 + 8003ed4: 08003eef .word 0x08003eef { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 80040cc: f7ff f978 bl 80033c0 - 80040d0: 6278 str r0, [r7, #36] ; 0x24 + 8003ed8: f7ff f978 bl 80031cc + 8003edc: 6278 str r0, [r7, #36] ; 0x24 break; - 80040d2: e010 b.n 80040f6 + 8003ede: e010 b.n 8003f02 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; - 80040d4: 4b1c ldr r3, [pc, #112] ; (8004148 ) - 80040d6: 627b str r3, [r7, #36] ; 0x24 + 8003ee0: 4b1c ldr r3, [pc, #112] ; (8003f54 ) + 8003ee2: 627b str r3, [r7, #36] ; 0x24 break; - 80040d8: e00d b.n 80040f6 + 8003ee4: e00d b.n 8003f02 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 80040da: f7ff f8bd bl 8003258 - 80040de: 6278 str r0, [r7, #36] ; 0x24 + 8003ee6: f7ff f8bd bl 8003064 + 8003eea: 6278 str r0, [r7, #36] ; 0x24 break; - 80040e0: e009 b.n 80040f6 + 8003eec: e009 b.n 8003f02 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 80040e2: f44f 4300 mov.w r3, #32768 ; 0x8000 - 80040e6: 627b str r3, [r7, #36] ; 0x24 + 8003eee: f44f 4300 mov.w r3, #32768 ; 0x8000 + 8003ef2: 627b str r3, [r7, #36] ; 0x24 break; - 80040e8: e005 b.n 80040f6 + 8003ef4: e005 b.n 8003f02 default: pclk = 0U; - 80040ea: 2300 movs r3, #0 - 80040ec: 627b str r3, [r7, #36] ; 0x24 + 8003ef6: 2300 movs r3, #0 + 8003ef8: 627b str r3, [r7, #36] ; 0x24 ret = HAL_ERROR; - 80040ee: 2301 movs r3, #1 - 80040f0: f887 302a strb.w r3, [r7, #42] ; 0x2a + 8003efa: 2301 movs r3, #1 + 8003efc: f887 302a strb.w r3, [r7, #42] ; 0x2a break; - 80040f4: bf00 nop + 8003f00: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) - 80040f6: 6a7b ldr r3, [r7, #36] ; 0x24 - 80040f8: 2b00 cmp r3, #0 - 80040fa: f000 8137 beq.w 800436c + 8003f02: 6a7b ldr r3, [r7, #36] ; 0x24 + 8003f04: 2b00 cmp r3, #0 + 8003f06: f000 8137 beq.w 8004178 { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); - 80040fe: 697b ldr r3, [r7, #20] - 8004100: 6a5b ldr r3, [r3, #36] ; 0x24 - 8004102: 4a12 ldr r2, [pc, #72] ; (800414c ) - 8004104: f832 3013 ldrh.w r3, [r2, r3, lsl #1] - 8004108: 461a mov r2, r3 - 800410a: 6a7b ldr r3, [r7, #36] ; 0x24 - 800410c: fbb3 f3f2 udiv r3, r3, r2 - 8004110: 61bb str r3, [r7, #24] + 8003f0a: 697b ldr r3, [r7, #20] + 8003f0c: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003f0e: 4a12 ldr r2, [pc, #72] ; (8003f58 ) + 8003f10: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8003f14: 461a mov r2, r3 + 8003f16: 6a7b ldr r3, [r7, #36] ; 0x24 + 8003f18: fbb3 f3f2 udiv r3, r3, r2 + 8003f1c: 61bb str r3, [r7, #24] /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || - 8004112: 697b ldr r3, [r7, #20] - 8004114: 685a ldr r2, [r3, #4] - 8004116: 4613 mov r3, r2 - 8004118: 005b lsls r3, r3, #1 - 800411a: 4413 add r3, r2 - 800411c: 69ba ldr r2, [r7, #24] - 800411e: 429a cmp r2, r3 - 8004120: d305 bcc.n 800412e + 8003f1e: 697b ldr r3, [r7, #20] + 8003f20: 685a ldr r2, [r3, #4] + 8003f22: 4613 mov r3, r2 + 8003f24: 005b lsls r3, r3, #1 + 8003f26: 4413 add r3, r2 + 8003f28: 69ba ldr r2, [r7, #24] + 8003f2a: 429a cmp r2, r3 + 8003f2c: d305 bcc.n 8003f3a (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) - 8004122: 697b ldr r3, [r7, #20] - 8004124: 685b ldr r3, [r3, #4] - 8004126: 031b lsls r3, r3, #12 + 8003f2e: 697b ldr r3, [r7, #20] + 8003f30: 685b ldr r3, [r3, #4] + 8003f32: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || - 8004128: 69ba ldr r2, [r7, #24] - 800412a: 429a cmp r2, r3 - 800412c: d910 bls.n 8004150 + 8003f34: 69ba ldr r2, [r7, #24] + 8003f36: 429a cmp r2, r3 + 8003f38: d910 bls.n 8003f5c { ret = HAL_ERROR; - 800412e: 2301 movs r3, #1 - 8004130: f887 302a strb.w r3, [r7, #42] ; 0x2a - 8004134: e11a b.n 800436c - 8004136: bf00 nop - 8004138: cfff69f3 .word 0xcfff69f3 - 800413c: 40008000 .word 0x40008000 - 8004140: 40013800 .word 0x40013800 - 8004144: 40004400 .word 0x40004400 - 8004148: 00f42400 .word 0x00f42400 - 800414c: 08004ab4 .word 0x08004ab4 + 8003f3a: 2301 movs r3, #1 + 8003f3c: f887 302a strb.w r3, [r7, #42] ; 0x2a + 8003f40: e11a b.n 8004178 + 8003f42: bf00 nop + 8003f44: cfff69f3 .word 0xcfff69f3 + 8003f48: 40008000 .word 0x40008000 + 8003f4c: 40013800 .word 0x40013800 + 8003f50: 40004400 .word 0x40004400 + 8003f54: 00f42400 .word 0x00f42400 + 8003f58: 08004858 .word 0x08004858 } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - 8004150: 6a7b ldr r3, [r7, #36] ; 0x24 - 8004152: 2200 movs r2, #0 - 8004154: 60bb str r3, [r7, #8] - 8004156: 60fa str r2, [r7, #12] - 8004158: 697b ldr r3, [r7, #20] - 800415a: 6a5b ldr r3, [r3, #36] ; 0x24 - 800415c: 4a8e ldr r2, [pc, #568] ; (8004398 ) - 800415e: f832 3013 ldrh.w r3, [r2, r3, lsl #1] - 8004162: b29b uxth r3, r3 - 8004164: 2200 movs r2, #0 - 8004166: 603b str r3, [r7, #0] - 8004168: 607a str r2, [r7, #4] - 800416a: e9d7 2300 ldrd r2, r3, [r7] - 800416e: e9d7 0102 ldrd r0, r1, [r7, #8] - 8004172: f7fc fbef bl 8000954 <__aeabi_uldivmod> - 8004176: 4602 mov r2, r0 - 8004178: 460b mov r3, r1 - 800417a: 4610 mov r0, r2 - 800417c: 4619 mov r1, r3 - 800417e: f04f 0200 mov.w r2, #0 - 8004182: f04f 0300 mov.w r3, #0 - 8004186: 020b lsls r3, r1, #8 - 8004188: ea43 6310 orr.w r3, r3, r0, lsr #24 - 800418c: 0202 lsls r2, r0, #8 - 800418e: 6979 ldr r1, [r7, #20] - 8004190: 6849 ldr r1, [r1, #4] - 8004192: 0849 lsrs r1, r1, #1 - 8004194: 2000 movs r0, #0 - 8004196: 460c mov r4, r1 - 8004198: 4605 mov r5, r0 - 800419a: eb12 0804 adds.w r8, r2, r4 - 800419e: eb43 0905 adc.w r9, r3, r5 - 80041a2: 697b ldr r3, [r7, #20] - 80041a4: 685b ldr r3, [r3, #4] - 80041a6: 2200 movs r2, #0 - 80041a8: 469a mov sl, r3 - 80041aa: 4693 mov fp, r2 - 80041ac: 4652 mov r2, sl - 80041ae: 465b mov r3, fp - 80041b0: 4640 mov r0, r8 - 80041b2: 4649 mov r1, r9 - 80041b4: f7fc fbce bl 8000954 <__aeabi_uldivmod> - 80041b8: 4602 mov r2, r0 - 80041ba: 460b mov r3, r1 - 80041bc: 4613 mov r3, r2 - 80041be: 623b str r3, [r7, #32] + 8003f5c: 6a7b ldr r3, [r7, #36] ; 0x24 + 8003f5e: 2200 movs r2, #0 + 8003f60: 60bb str r3, [r7, #8] + 8003f62: 60fa str r2, [r7, #12] + 8003f64: 697b ldr r3, [r7, #20] + 8003f66: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003f68: 4a8e ldr r2, [pc, #568] ; (80041a4 ) + 8003f6a: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8003f6e: b29b uxth r3, r3 + 8003f70: 2200 movs r2, #0 + 8003f72: 603b str r3, [r7, #0] + 8003f74: 607a str r2, [r7, #4] + 8003f76: e9d7 2300 ldrd r2, r3, [r7] + 8003f7a: e9d7 0102 ldrd r0, r1, [r7, #8] + 8003f7e: f7fc fce9 bl 8000954 <__aeabi_uldivmod> + 8003f82: 4602 mov r2, r0 + 8003f84: 460b mov r3, r1 + 8003f86: 4610 mov r0, r2 + 8003f88: 4619 mov r1, r3 + 8003f8a: f04f 0200 mov.w r2, #0 + 8003f8e: f04f 0300 mov.w r3, #0 + 8003f92: 020b lsls r3, r1, #8 + 8003f94: ea43 6310 orr.w r3, r3, r0, lsr #24 + 8003f98: 0202 lsls r2, r0, #8 + 8003f9a: 6979 ldr r1, [r7, #20] + 8003f9c: 6849 ldr r1, [r1, #4] + 8003f9e: 0849 lsrs r1, r1, #1 + 8003fa0: 2000 movs r0, #0 + 8003fa2: 460c mov r4, r1 + 8003fa4: 4605 mov r5, r0 + 8003fa6: eb12 0804 adds.w r8, r2, r4 + 8003faa: eb43 0905 adc.w r9, r3, r5 + 8003fae: 697b ldr r3, [r7, #20] + 8003fb0: 685b ldr r3, [r3, #4] + 8003fb2: 2200 movs r2, #0 + 8003fb4: 469a mov sl, r3 + 8003fb6: 4693 mov fp, r2 + 8003fb8: 4652 mov r2, sl + 8003fba: 465b mov r3, fp + 8003fbc: 4640 mov r0, r8 + 8003fbe: 4649 mov r1, r9 + 8003fc0: f7fc fcc8 bl 8000954 <__aeabi_uldivmod> + 8003fc4: 4602 mov r2, r0 + 8003fc6: 460b mov r3, r1 + 8003fc8: 4613 mov r3, r2 + 8003fca: 623b str r3, [r7, #32] if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) - 80041c0: 6a3b ldr r3, [r7, #32] - 80041c2: f5b3 7f40 cmp.w r3, #768 ; 0x300 - 80041c6: d308 bcc.n 80041da - 80041c8: 6a3b ldr r3, [r7, #32] - 80041ca: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 - 80041ce: d204 bcs.n 80041da + 8003fcc: 6a3b ldr r3, [r7, #32] + 8003fce: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 8003fd2: d308 bcc.n 8003fe6 + 8003fd4: 6a3b ldr r3, [r7, #32] + 8003fd6: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 8003fda: d204 bcs.n 8003fe6 { huart->Instance->BRR = usartdiv; - 80041d0: 697b ldr r3, [r7, #20] - 80041d2: 681b ldr r3, [r3, #0] - 80041d4: 6a3a ldr r2, [r7, #32] - 80041d6: 60da str r2, [r3, #12] - 80041d8: e0c8 b.n 800436c + 8003fdc: 697b ldr r3, [r7, #20] + 8003fde: 681b ldr r3, [r3, #0] + 8003fe0: 6a3a ldr r2, [r7, #32] + 8003fe2: 60da str r2, [r3, #12] + 8003fe4: e0c8 b.n 8004178 } else { ret = HAL_ERROR; - 80041da: 2301 movs r3, #1 - 80041dc: f887 302a strb.w r3, [r7, #42] ; 0x2a - 80041e0: e0c4 b.n 800436c + 8003fe6: 2301 movs r3, #1 + 8003fe8: f887 302a strb.w r3, [r7, #42] ; 0x2a + 8003fec: e0c4 b.n 8004178 } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - 80041e2: 697b ldr r3, [r7, #20] - 80041e4: 69db ldr r3, [r3, #28] - 80041e6: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 - 80041ea: d167 bne.n 80042bc + 8003fee: 697b ldr r3, [r7, #20] + 8003ff0: 69db ldr r3, [r3, #28] + 8003ff2: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8003ff6: d167 bne.n 80040c8 { switch (clocksource) - 80041ec: f897 302b ldrb.w r3, [r7, #43] ; 0x2b - 80041f0: 2b08 cmp r3, #8 - 80041f2: d828 bhi.n 8004246 - 80041f4: a201 add r2, pc, #4 ; (adr r2, 80041fc ) - 80041f6: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 80041fa: bf00 nop - 80041fc: 08004221 .word 0x08004221 - 8004200: 08004229 .word 0x08004229 - 8004204: 08004231 .word 0x08004231 - 8004208: 08004247 .word 0x08004247 - 800420c: 08004237 .word 0x08004237 - 8004210: 08004247 .word 0x08004247 - 8004214: 08004247 .word 0x08004247 - 8004218: 08004247 .word 0x08004247 - 800421c: 0800423f .word 0x0800423f + 8003ff8: f897 302b ldrb.w r3, [r7, #43] ; 0x2b + 8003ffc: 2b08 cmp r3, #8 + 8003ffe: d828 bhi.n 8004052 + 8004000: a201 add r2, pc, #4 ; (adr r2, 8004008 ) + 8004002: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8004006: bf00 nop + 8004008: 0800402d .word 0x0800402d + 800400c: 08004035 .word 0x08004035 + 8004010: 0800403d .word 0x0800403d + 8004014: 08004053 .word 0x08004053 + 8004018: 08004043 .word 0x08004043 + 800401c: 08004053 .word 0x08004053 + 8004020: 08004053 .word 0x08004053 + 8004024: 08004053 .word 0x08004053 + 8004028: 0800404b .word 0x0800404b { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 8004220: f7ff f8ce bl 80033c0 - 8004224: 6278 str r0, [r7, #36] ; 0x24 + 800402c: f7ff f8ce bl 80031cc + 8004030: 6278 str r0, [r7, #36] ; 0x24 break; - 8004226: e014 b.n 8004252 + 8004032: e014 b.n 800405e case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - 8004228: f7ff f8dc bl 80033e4 - 800422c: 6278 str r0, [r7, #36] ; 0x24 + 8004034: f7ff f8dc bl 80031f0 + 8004038: 6278 str r0, [r7, #36] ; 0x24 break; - 800422e: e010 b.n 8004252 + 800403a: e010 b.n 800405e case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; - 8004230: 4b5a ldr r3, [pc, #360] ; (800439c ) - 8004232: 627b str r3, [r7, #36] ; 0x24 + 800403c: 4b5a ldr r3, [pc, #360] ; (80041a8 ) + 800403e: 627b str r3, [r7, #36] ; 0x24 break; - 8004234: e00d b.n 8004252 + 8004040: e00d b.n 800405e case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 8004236: f7ff f80f bl 8003258 - 800423a: 6278 str r0, [r7, #36] ; 0x24 + 8004042: f7ff f80f bl 8003064 + 8004046: 6278 str r0, [r7, #36] ; 0x24 break; - 800423c: e009 b.n 8004252 + 8004048: e009 b.n 800405e case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 800423e: f44f 4300 mov.w r3, #32768 ; 0x8000 - 8004242: 627b str r3, [r7, #36] ; 0x24 + 800404a: f44f 4300 mov.w r3, #32768 ; 0x8000 + 800404e: 627b str r3, [r7, #36] ; 0x24 break; - 8004244: e005 b.n 8004252 + 8004050: e005 b.n 800405e default: pclk = 0U; - 8004246: 2300 movs r3, #0 - 8004248: 627b str r3, [r7, #36] ; 0x24 + 8004052: 2300 movs r3, #0 + 8004054: 627b str r3, [r7, #36] ; 0x24 ret = HAL_ERROR; - 800424a: 2301 movs r3, #1 - 800424c: f887 302a strb.w r3, [r7, #42] ; 0x2a + 8004056: 2301 movs r3, #1 + 8004058: f887 302a strb.w r3, [r7, #42] ; 0x2a break; - 8004250: bf00 nop + 800405c: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) - 8004252: 6a7b ldr r3, [r7, #36] ; 0x24 - 8004254: 2b00 cmp r3, #0 - 8004256: f000 8089 beq.w 800436c + 800405e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8004060: 2b00 cmp r3, #0 + 8004062: f000 8089 beq.w 8004178 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - 800425a: 697b ldr r3, [r7, #20] - 800425c: 6a5b ldr r3, [r3, #36] ; 0x24 - 800425e: 4a4e ldr r2, [pc, #312] ; (8004398 ) - 8004260: f832 3013 ldrh.w r3, [r2, r3, lsl #1] - 8004264: 461a mov r2, r3 - 8004266: 6a7b ldr r3, [r7, #36] ; 0x24 - 8004268: fbb3 f3f2 udiv r3, r3, r2 - 800426c: 005a lsls r2, r3, #1 - 800426e: 697b ldr r3, [r7, #20] - 8004270: 685b ldr r3, [r3, #4] - 8004272: 085b lsrs r3, r3, #1 - 8004274: 441a add r2, r3 - 8004276: 697b ldr r3, [r7, #20] - 8004278: 685b ldr r3, [r3, #4] - 800427a: fbb2 f3f3 udiv r3, r2, r3 - 800427e: 623b str r3, [r7, #32] + 8004066: 697b ldr r3, [r7, #20] + 8004068: 6a5b ldr r3, [r3, #36] ; 0x24 + 800406a: 4a4e ldr r2, [pc, #312] ; (80041a4 ) + 800406c: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8004070: 461a mov r2, r3 + 8004072: 6a7b ldr r3, [r7, #36] ; 0x24 + 8004074: fbb3 f3f2 udiv r3, r3, r2 + 8004078: 005a lsls r2, r3, #1 + 800407a: 697b ldr r3, [r7, #20] + 800407c: 685b ldr r3, [r3, #4] + 800407e: 085b lsrs r3, r3, #1 + 8004080: 441a add r2, r3 + 8004082: 697b ldr r3, [r7, #20] + 8004084: 685b ldr r3, [r3, #4] + 8004086: fbb2 f3f3 udiv r3, r2, r3 + 800408a: 623b str r3, [r7, #32] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - 8004280: 6a3b ldr r3, [r7, #32] - 8004282: 2b0f cmp r3, #15 - 8004284: d916 bls.n 80042b4 - 8004286: 6a3b ldr r3, [r7, #32] - 8004288: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 - 800428c: d212 bcs.n 80042b4 + 800408c: 6a3b ldr r3, [r7, #32] + 800408e: 2b0f cmp r3, #15 + 8004090: d916 bls.n 80040c0 + 8004092: 6a3b ldr r3, [r7, #32] + 8004094: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8004098: d212 bcs.n 80040c0 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); - 800428e: 6a3b ldr r3, [r7, #32] - 8004290: b29b uxth r3, r3 - 8004292: f023 030f bic.w r3, r3, #15 - 8004296: 83fb strh r3, [r7, #30] + 800409a: 6a3b ldr r3, [r7, #32] + 800409c: b29b uxth r3, r3 + 800409e: f023 030f bic.w r3, r3, #15 + 80040a2: 83fb strh r3, [r7, #30] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - 8004298: 6a3b ldr r3, [r7, #32] - 800429a: 085b lsrs r3, r3, #1 - 800429c: b29b uxth r3, r3 - 800429e: f003 0307 and.w r3, r3, #7 - 80042a2: b29a uxth r2, r3 - 80042a4: 8bfb ldrh r3, [r7, #30] - 80042a6: 4313 orrs r3, r2 - 80042a8: 83fb strh r3, [r7, #30] + 80040a4: 6a3b ldr r3, [r7, #32] + 80040a6: 085b lsrs r3, r3, #1 + 80040a8: b29b uxth r3, r3 + 80040aa: f003 0307 and.w r3, r3, #7 + 80040ae: b29a uxth r2, r3 + 80040b0: 8bfb ldrh r3, [r7, #30] + 80040b2: 4313 orrs r3, r2 + 80040b4: 83fb strh r3, [r7, #30] huart->Instance->BRR = brrtemp; - 80042aa: 697b ldr r3, [r7, #20] - 80042ac: 681b ldr r3, [r3, #0] - 80042ae: 8bfa ldrh r2, [r7, #30] - 80042b0: 60da str r2, [r3, #12] - 80042b2: e05b b.n 800436c + 80040b6: 697b ldr r3, [r7, #20] + 80040b8: 681b ldr r3, [r3, #0] + 80040ba: 8bfa ldrh r2, [r7, #30] + 80040bc: 60da str r2, [r3, #12] + 80040be: e05b b.n 8004178 } else { ret = HAL_ERROR; - 80042b4: 2301 movs r3, #1 - 80042b6: f887 302a strb.w r3, [r7, #42] ; 0x2a - 80042ba: e057 b.n 800436c + 80040c0: 2301 movs r3, #1 + 80040c2: f887 302a strb.w r3, [r7, #42] ; 0x2a + 80040c6: e057 b.n 8004178 } } } else { switch (clocksource) - 80042bc: f897 302b ldrb.w r3, [r7, #43] ; 0x2b - 80042c0: 2b08 cmp r3, #8 - 80042c2: d828 bhi.n 8004316 - 80042c4: a201 add r2, pc, #4 ; (adr r2, 80042cc ) - 80042c6: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 80042ca: bf00 nop - 80042cc: 080042f1 .word 0x080042f1 - 80042d0: 080042f9 .word 0x080042f9 - 80042d4: 08004301 .word 0x08004301 - 80042d8: 08004317 .word 0x08004317 - 80042dc: 08004307 .word 0x08004307 - 80042e0: 08004317 .word 0x08004317 - 80042e4: 08004317 .word 0x08004317 - 80042e8: 08004317 .word 0x08004317 - 80042ec: 0800430f .word 0x0800430f + 80040c8: f897 302b ldrb.w r3, [r7, #43] ; 0x2b + 80040cc: 2b08 cmp r3, #8 + 80040ce: d828 bhi.n 8004122 + 80040d0: a201 add r2, pc, #4 ; (adr r2, 80040d8 ) + 80040d2: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80040d6: bf00 nop + 80040d8: 080040fd .word 0x080040fd + 80040dc: 08004105 .word 0x08004105 + 80040e0: 0800410d .word 0x0800410d + 80040e4: 08004123 .word 0x08004123 + 80040e8: 08004113 .word 0x08004113 + 80040ec: 08004123 .word 0x08004123 + 80040f0: 08004123 .word 0x08004123 + 80040f4: 08004123 .word 0x08004123 + 80040f8: 0800411b .word 0x0800411b { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 80042f0: f7ff f866 bl 80033c0 - 80042f4: 6278 str r0, [r7, #36] ; 0x24 + 80040fc: f7ff f866 bl 80031cc + 8004100: 6278 str r0, [r7, #36] ; 0x24 break; - 80042f6: e014 b.n 8004322 + 8004102: e014 b.n 800412e case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - 80042f8: f7ff f874 bl 80033e4 - 80042fc: 6278 str r0, [r7, #36] ; 0x24 + 8004104: f7ff f874 bl 80031f0 + 8004108: 6278 str r0, [r7, #36] ; 0x24 break; - 80042fe: e010 b.n 8004322 + 800410a: e010 b.n 800412e case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; - 8004300: 4b26 ldr r3, [pc, #152] ; (800439c ) - 8004302: 627b str r3, [r7, #36] ; 0x24 + 800410c: 4b26 ldr r3, [pc, #152] ; (80041a8 ) + 800410e: 627b str r3, [r7, #36] ; 0x24 break; - 8004304: e00d b.n 8004322 + 8004110: e00d b.n 800412e case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 8004306: f7fe ffa7 bl 8003258 - 800430a: 6278 str r0, [r7, #36] ; 0x24 + 8004112: f7fe ffa7 bl 8003064 + 8004116: 6278 str r0, [r7, #36] ; 0x24 break; - 800430c: e009 b.n 8004322 + 8004118: e009 b.n 800412e case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 800430e: f44f 4300 mov.w r3, #32768 ; 0x8000 - 8004312: 627b str r3, [r7, #36] ; 0x24 + 800411a: f44f 4300 mov.w r3, #32768 ; 0x8000 + 800411e: 627b str r3, [r7, #36] ; 0x24 break; - 8004314: e005 b.n 8004322 + 8004120: e005 b.n 800412e default: pclk = 0U; - 8004316: 2300 movs r3, #0 - 8004318: 627b str r3, [r7, #36] ; 0x24 + 8004122: 2300 movs r3, #0 + 8004124: 627b str r3, [r7, #36] ; 0x24 ret = HAL_ERROR; - 800431a: 2301 movs r3, #1 - 800431c: f887 302a strb.w r3, [r7, #42] ; 0x2a + 8004126: 2301 movs r3, #1 + 8004128: f887 302a strb.w r3, [r7, #42] ; 0x2a break; - 8004320: bf00 nop + 800412c: bf00 nop } if (pclk != 0U) - 8004322: 6a7b ldr r3, [r7, #36] ; 0x24 - 8004324: 2b00 cmp r3, #0 - 8004326: d021 beq.n 800436c + 800412e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8004130: 2b00 cmp r3, #0 + 8004132: d021 beq.n 8004178 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - 8004328: 697b ldr r3, [r7, #20] - 800432a: 6a5b ldr r3, [r3, #36] ; 0x24 - 800432c: 4a1a ldr r2, [pc, #104] ; (8004398 ) - 800432e: f832 3013 ldrh.w r3, [r2, r3, lsl #1] - 8004332: 461a mov r2, r3 - 8004334: 6a7b ldr r3, [r7, #36] ; 0x24 - 8004336: fbb3 f2f2 udiv r2, r3, r2 - 800433a: 697b ldr r3, [r7, #20] - 800433c: 685b ldr r3, [r3, #4] - 800433e: 085b lsrs r3, r3, #1 - 8004340: 441a add r2, r3 - 8004342: 697b ldr r3, [r7, #20] - 8004344: 685b ldr r3, [r3, #4] - 8004346: fbb2 f3f3 udiv r3, r2, r3 - 800434a: 623b str r3, [r7, #32] + 8004134: 697b ldr r3, [r7, #20] + 8004136: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004138: 4a1a ldr r2, [pc, #104] ; (80041a4 ) + 800413a: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 800413e: 461a mov r2, r3 + 8004140: 6a7b ldr r3, [r7, #36] ; 0x24 + 8004142: fbb3 f2f2 udiv r2, r3, r2 + 8004146: 697b ldr r3, [r7, #20] + 8004148: 685b ldr r3, [r3, #4] + 800414a: 085b lsrs r3, r3, #1 + 800414c: 441a add r2, r3 + 800414e: 697b ldr r3, [r7, #20] + 8004150: 685b ldr r3, [r3, #4] + 8004152: fbb2 f3f3 udiv r3, r2, r3 + 8004156: 623b str r3, [r7, #32] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - 800434c: 6a3b ldr r3, [r7, #32] - 800434e: 2b0f cmp r3, #15 - 8004350: d909 bls.n 8004366 - 8004352: 6a3b ldr r3, [r7, #32] - 8004354: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 - 8004358: d205 bcs.n 8004366 + 8004158: 6a3b ldr r3, [r7, #32] + 800415a: 2b0f cmp r3, #15 + 800415c: d909 bls.n 8004172 + 800415e: 6a3b ldr r3, [r7, #32] + 8004160: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8004164: d205 bcs.n 8004172 { huart->Instance->BRR = (uint16_t)usartdiv; - 800435a: 6a3b ldr r3, [r7, #32] - 800435c: b29a uxth r2, r3 - 800435e: 697b ldr r3, [r7, #20] - 8004360: 681b ldr r3, [r3, #0] - 8004362: 60da str r2, [r3, #12] - 8004364: e002 b.n 800436c + 8004166: 6a3b ldr r3, [r7, #32] + 8004168: b29a uxth r2, r3 + 800416a: 697b ldr r3, [r7, #20] + 800416c: 681b ldr r3, [r3, #0] + 800416e: 60da str r2, [r3, #12] + 8004170: e002 b.n 8004178 } else { ret = HAL_ERROR; - 8004366: 2301 movs r3, #1 - 8004368: f887 302a strb.w r3, [r7, #42] ; 0x2a + 8004172: 2301 movs r3, #1 + 8004174: f887 302a strb.w r3, [r7, #42] ; 0x2a } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; - 800436c: 697b ldr r3, [r7, #20] - 800436e: 2201 movs r2, #1 - 8004370: f8a3 206a strh.w r2, [r3, #106] ; 0x6a + 8004178: 697b ldr r3, [r7, #20] + 800417a: 2201 movs r2, #1 + 800417c: f8a3 206a strh.w r2, [r3, #106] ; 0x6a huart->NbRxDataToProcess = 1; - 8004374: 697b ldr r3, [r7, #20] - 8004376: 2201 movs r2, #1 - 8004378: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 + 8004180: 697b ldr r3, [r7, #20] + 8004182: 2201 movs r2, #1 + 8004184: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; - 800437c: 697b ldr r3, [r7, #20] - 800437e: 2200 movs r2, #0 - 8004380: 675a str r2, [r3, #116] ; 0x74 + 8004188: 697b ldr r3, [r7, #20] + 800418a: 2200 movs r2, #0 + 800418c: 675a str r2, [r3, #116] ; 0x74 huart->TxISR = NULL; - 8004382: 697b ldr r3, [r7, #20] - 8004384: 2200 movs r2, #0 - 8004386: 679a str r2, [r3, #120] ; 0x78 + 800418e: 697b ldr r3, [r7, #20] + 8004190: 2200 movs r2, #0 + 8004192: 679a str r2, [r3, #120] ; 0x78 return ret; - 8004388: f897 302a ldrb.w r3, [r7, #42] ; 0x2a + 8004194: f897 302a ldrb.w r3, [r7, #42] ; 0x2a } - 800438c: 4618 mov r0, r3 - 800438e: 3730 adds r7, #48 ; 0x30 - 8004390: 46bd mov sp, r7 - 8004392: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} - 8004396: bf00 nop - 8004398: 08004ab4 .word 0x08004ab4 - 800439c: 00f42400 .word 0x00f42400 + 8004198: 4618 mov r0, r3 + 800419a: 3730 adds r7, #48 ; 0x30 + 800419c: 46bd mov sp, r7 + 800419e: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 80041a2: bf00 nop + 80041a4: 08004858 .word 0x08004858 + 80041a8: 00f42400 .word 0x00f42400 -080043a0 : +080041ac : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { - 80043a0: b480 push {r7} - 80043a2: b083 sub sp, #12 - 80043a4: af00 add r7, sp, #0 - 80043a6: 6078 str r0, [r7, #4] + 80041ac: b480 push {r7} + 80041ae: b083 sub sp, #12 + 80041b0: af00 add r7, sp, #0 + 80041b2: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) - 80043a8: 687b ldr r3, [r7, #4] - 80043aa: 6a9b ldr r3, [r3, #40] ; 0x28 - 80043ac: f003 0301 and.w r3, r3, #1 - 80043b0: 2b00 cmp r3, #0 - 80043b2: d00a beq.n 80043ca + 80041b4: 687b ldr r3, [r7, #4] + 80041b6: 6a9b ldr r3, [r3, #40] ; 0x28 + 80041b8: f003 0301 and.w r3, r3, #1 + 80041bc: 2b00 cmp r3, #0 + 80041be: d00a beq.n 80041d6 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); - 80043b4: 687b ldr r3, [r7, #4] - 80043b6: 681b ldr r3, [r3, #0] - 80043b8: 685b ldr r3, [r3, #4] - 80043ba: f423 3100 bic.w r1, r3, #131072 ; 0x20000 - 80043be: 687b ldr r3, [r7, #4] - 80043c0: 6ada ldr r2, [r3, #44] ; 0x2c - 80043c2: 687b ldr r3, [r7, #4] - 80043c4: 681b ldr r3, [r3, #0] - 80043c6: 430a orrs r2, r1 - 80043c8: 605a str r2, [r3, #4] + 80041c0: 687b ldr r3, [r7, #4] + 80041c2: 681b ldr r3, [r3, #0] + 80041c4: 685b ldr r3, [r3, #4] + 80041c6: f423 3100 bic.w r1, r3, #131072 ; 0x20000 + 80041ca: 687b ldr r3, [r7, #4] + 80041cc: 6ada ldr r2, [r3, #44] ; 0x2c + 80041ce: 687b ldr r3, [r7, #4] + 80041d0: 681b ldr r3, [r3, #0] + 80041d2: 430a orrs r2, r1 + 80041d4: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) - 80043ca: 687b ldr r3, [r7, #4] - 80043cc: 6a9b ldr r3, [r3, #40] ; 0x28 - 80043ce: f003 0302 and.w r3, r3, #2 - 80043d2: 2b00 cmp r3, #0 - 80043d4: d00a beq.n 80043ec + 80041d6: 687b ldr r3, [r7, #4] + 80041d8: 6a9b ldr r3, [r3, #40] ; 0x28 + 80041da: f003 0302 and.w r3, r3, #2 + 80041de: 2b00 cmp r3, #0 + 80041e0: d00a beq.n 80041f8 { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); - 80043d6: 687b ldr r3, [r7, #4] - 80043d8: 681b ldr r3, [r3, #0] - 80043da: 685b ldr r3, [r3, #4] - 80043dc: f423 3180 bic.w r1, r3, #65536 ; 0x10000 - 80043e0: 687b ldr r3, [r7, #4] - 80043e2: 6b1a ldr r2, [r3, #48] ; 0x30 - 80043e4: 687b ldr r3, [r7, #4] - 80043e6: 681b ldr r3, [r3, #0] - 80043e8: 430a orrs r2, r1 - 80043ea: 605a str r2, [r3, #4] + 80041e2: 687b ldr r3, [r7, #4] + 80041e4: 681b ldr r3, [r3, #0] + 80041e6: 685b ldr r3, [r3, #4] + 80041e8: f423 3180 bic.w r1, r3, #65536 ; 0x10000 + 80041ec: 687b ldr r3, [r7, #4] + 80041ee: 6b1a ldr r2, [r3, #48] ; 0x30 + 80041f0: 687b ldr r3, [r7, #4] + 80041f2: 681b ldr r3, [r3, #0] + 80041f4: 430a orrs r2, r1 + 80041f6: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) - 80043ec: 687b ldr r3, [r7, #4] - 80043ee: 6a9b ldr r3, [r3, #40] ; 0x28 - 80043f0: f003 0304 and.w r3, r3, #4 - 80043f4: 2b00 cmp r3, #0 - 80043f6: d00a beq.n 800440e + 80041f8: 687b ldr r3, [r7, #4] + 80041fa: 6a9b ldr r3, [r3, #40] ; 0x28 + 80041fc: f003 0304 and.w r3, r3, #4 + 8004200: 2b00 cmp r3, #0 + 8004202: d00a beq.n 800421a { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); - 80043f8: 687b ldr r3, [r7, #4] - 80043fa: 681b ldr r3, [r3, #0] - 80043fc: 685b ldr r3, [r3, #4] - 80043fe: f423 2180 bic.w r1, r3, #262144 ; 0x40000 - 8004402: 687b ldr r3, [r7, #4] - 8004404: 6b5a ldr r2, [r3, #52] ; 0x34 - 8004406: 687b ldr r3, [r7, #4] - 8004408: 681b ldr r3, [r3, #0] - 800440a: 430a orrs r2, r1 - 800440c: 605a str r2, [r3, #4] + 8004204: 687b ldr r3, [r7, #4] + 8004206: 681b ldr r3, [r3, #0] + 8004208: 685b ldr r3, [r3, #4] + 800420a: f423 2180 bic.w r1, r3, #262144 ; 0x40000 + 800420e: 687b ldr r3, [r7, #4] + 8004210: 6b5a ldr r2, [r3, #52] ; 0x34 + 8004212: 687b ldr r3, [r7, #4] + 8004214: 681b ldr r3, [r3, #0] + 8004216: 430a orrs r2, r1 + 8004218: 605a str r2, [r3, #4] } /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - 800440e: 687b ldr r3, [r7, #4] - 8004410: 6a9b ldr r3, [r3, #40] ; 0x28 - 8004412: f003 0308 and.w r3, r3, #8 - 8004416: 2b00 cmp r3, #0 - 8004418: d00a beq.n 8004430 + 800421a: 687b ldr r3, [r7, #4] + 800421c: 6a9b ldr r3, [r3, #40] ; 0x28 + 800421e: f003 0308 and.w r3, r3, #8 + 8004222: 2b00 cmp r3, #0 + 8004224: d00a beq.n 800423c { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - 800441a: 687b ldr r3, [r7, #4] - 800441c: 681b ldr r3, [r3, #0] - 800441e: 685b ldr r3, [r3, #4] - 8004420: f423 4100 bic.w r1, r3, #32768 ; 0x8000 - 8004424: 687b ldr r3, [r7, #4] - 8004426: 6b9a ldr r2, [r3, #56] ; 0x38 - 8004428: 687b ldr r3, [r7, #4] - 800442a: 681b ldr r3, [r3, #0] - 800442c: 430a orrs r2, r1 - 800442e: 605a str r2, [r3, #4] + 8004226: 687b ldr r3, [r7, #4] + 8004228: 681b ldr r3, [r3, #0] + 800422a: 685b ldr r3, [r3, #4] + 800422c: f423 4100 bic.w r1, r3, #32768 ; 0x8000 + 8004230: 687b ldr r3, [r7, #4] + 8004232: 6b9a ldr r2, [r3, #56] ; 0x38 + 8004234: 687b ldr r3, [r7, #4] + 8004236: 681b ldr r3, [r3, #0] + 8004238: 430a orrs r2, r1 + 800423a: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) - 8004430: 687b ldr r3, [r7, #4] - 8004432: 6a9b ldr r3, [r3, #40] ; 0x28 - 8004434: f003 0310 and.w r3, r3, #16 - 8004438: 2b00 cmp r3, #0 - 800443a: d00a beq.n 8004452 + 800423c: 687b ldr r3, [r7, #4] + 800423e: 6a9b ldr r3, [r3, #40] ; 0x28 + 8004240: f003 0310 and.w r3, r3, #16 + 8004244: 2b00 cmp r3, #0 + 8004246: d00a beq.n 800425e { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); - 800443c: 687b ldr r3, [r7, #4] - 800443e: 681b ldr r3, [r3, #0] - 8004440: 689b ldr r3, [r3, #8] - 8004442: f423 5180 bic.w r1, r3, #4096 ; 0x1000 - 8004446: 687b ldr r3, [r7, #4] - 8004448: 6bda ldr r2, [r3, #60] ; 0x3c - 800444a: 687b ldr r3, [r7, #4] - 800444c: 681b ldr r3, [r3, #0] - 800444e: 430a orrs r2, r1 - 8004450: 609a str r2, [r3, #8] + 8004248: 687b ldr r3, [r7, #4] + 800424a: 681b ldr r3, [r3, #0] + 800424c: 689b ldr r3, [r3, #8] + 800424e: f423 5180 bic.w r1, r3, #4096 ; 0x1000 + 8004252: 687b ldr r3, [r7, #4] + 8004254: 6bda ldr r2, [r3, #60] ; 0x3c + 8004256: 687b ldr r3, [r7, #4] + 8004258: 681b ldr r3, [r3, #0] + 800425a: 430a orrs r2, r1 + 800425c: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) - 8004452: 687b ldr r3, [r7, #4] - 8004454: 6a9b ldr r3, [r3, #40] ; 0x28 - 8004456: f003 0320 and.w r3, r3, #32 - 800445a: 2b00 cmp r3, #0 - 800445c: d00a beq.n 8004474 + 800425e: 687b ldr r3, [r7, #4] + 8004260: 6a9b ldr r3, [r3, #40] ; 0x28 + 8004262: f003 0320 and.w r3, r3, #32 + 8004266: 2b00 cmp r3, #0 + 8004268: d00a beq.n 8004280 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); - 800445e: 687b ldr r3, [r7, #4] - 8004460: 681b ldr r3, [r3, #0] - 8004462: 689b ldr r3, [r3, #8] - 8004464: f423 5100 bic.w r1, r3, #8192 ; 0x2000 - 8004468: 687b ldr r3, [r7, #4] - 800446a: 6c1a ldr r2, [r3, #64] ; 0x40 - 800446c: 687b ldr r3, [r7, #4] - 800446e: 681b ldr r3, [r3, #0] - 8004470: 430a orrs r2, r1 - 8004472: 609a str r2, [r3, #8] + 800426a: 687b ldr r3, [r7, #4] + 800426c: 681b ldr r3, [r3, #0] + 800426e: 689b ldr r3, [r3, #8] + 8004270: f423 5100 bic.w r1, r3, #8192 ; 0x2000 + 8004274: 687b ldr r3, [r7, #4] + 8004276: 6c1a ldr r2, [r3, #64] ; 0x40 + 8004278: 687b ldr r3, [r7, #4] + 800427a: 681b ldr r3, [r3, #0] + 800427c: 430a orrs r2, r1 + 800427e: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) - 8004474: 687b ldr r3, [r7, #4] - 8004476: 6a9b ldr r3, [r3, #40] ; 0x28 - 8004478: f003 0340 and.w r3, r3, #64 ; 0x40 - 800447c: 2b00 cmp r3, #0 - 800447e: d01a beq.n 80044b6 + 8004280: 687b ldr r3, [r7, #4] + 8004282: 6a9b ldr r3, [r3, #40] ; 0x28 + 8004284: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004288: 2b00 cmp r3, #0 + 800428a: d01a beq.n 80042c2 { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); - 8004480: 687b ldr r3, [r7, #4] - 8004482: 681b ldr r3, [r3, #0] - 8004484: 685b ldr r3, [r3, #4] - 8004486: f423 1180 bic.w r1, r3, #1048576 ; 0x100000 - 800448a: 687b ldr r3, [r7, #4] - 800448c: 6c5a ldr r2, [r3, #68] ; 0x44 - 800448e: 687b ldr r3, [r7, #4] - 8004490: 681b ldr r3, [r3, #0] - 8004492: 430a orrs r2, r1 - 8004494: 605a str r2, [r3, #4] + 800428c: 687b ldr r3, [r7, #4] + 800428e: 681b ldr r3, [r3, #0] + 8004290: 685b ldr r3, [r3, #4] + 8004292: f423 1180 bic.w r1, r3, #1048576 ; 0x100000 + 8004296: 687b ldr r3, [r7, #4] + 8004298: 6c5a ldr r2, [r3, #68] ; 0x44 + 800429a: 687b ldr r3, [r7, #4] + 800429c: 681b ldr r3, [r3, #0] + 800429e: 430a orrs r2, r1 + 80042a0: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) - 8004496: 687b ldr r3, [r7, #4] - 8004498: 6c5b ldr r3, [r3, #68] ; 0x44 - 800449a: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 - 800449e: d10a bne.n 80044b6 + 80042a2: 687b ldr r3, [r7, #4] + 80042a4: 6c5b ldr r3, [r3, #68] ; 0x44 + 80042a6: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 80042aa: d10a bne.n 80042c2 { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); - 80044a0: 687b ldr r3, [r7, #4] - 80044a2: 681b ldr r3, [r3, #0] - 80044a4: 685b ldr r3, [r3, #4] - 80044a6: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000 - 80044aa: 687b ldr r3, [r7, #4] - 80044ac: 6c9a ldr r2, [r3, #72] ; 0x48 - 80044ae: 687b ldr r3, [r7, #4] - 80044b0: 681b ldr r3, [r3, #0] - 80044b2: 430a orrs r2, r1 - 80044b4: 605a str r2, [r3, #4] + 80042ac: 687b ldr r3, [r7, #4] + 80042ae: 681b ldr r3, [r3, #0] + 80042b0: 685b ldr r3, [r3, #4] + 80042b2: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000 + 80042b6: 687b ldr r3, [r7, #4] + 80042b8: 6c9a ldr r2, [r3, #72] ; 0x48 + 80042ba: 687b ldr r3, [r7, #4] + 80042bc: 681b ldr r3, [r3, #0] + 80042be: 430a orrs r2, r1 + 80042c0: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) - 80044b6: 687b ldr r3, [r7, #4] - 80044b8: 6a9b ldr r3, [r3, #40] ; 0x28 - 80044ba: f003 0380 and.w r3, r3, #128 ; 0x80 - 80044be: 2b00 cmp r3, #0 - 80044c0: d00a beq.n 80044d8 + 80042c2: 687b ldr r3, [r7, #4] + 80042c4: 6a9b ldr r3, [r3, #40] ; 0x28 + 80042c6: f003 0380 and.w r3, r3, #128 ; 0x80 + 80042ca: 2b00 cmp r3, #0 + 80042cc: d00a beq.n 80042e4 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); - 80044c2: 687b ldr r3, [r7, #4] - 80044c4: 681b ldr r3, [r3, #0] - 80044c6: 685b ldr r3, [r3, #4] - 80044c8: f423 2100 bic.w r1, r3, #524288 ; 0x80000 - 80044cc: 687b ldr r3, [r7, #4] - 80044ce: 6cda ldr r2, [r3, #76] ; 0x4c - 80044d0: 687b ldr r3, [r7, #4] - 80044d2: 681b ldr r3, [r3, #0] - 80044d4: 430a orrs r2, r1 - 80044d6: 605a str r2, [r3, #4] + 80042ce: 687b ldr r3, [r7, #4] + 80042d0: 681b ldr r3, [r3, #0] + 80042d2: 685b ldr r3, [r3, #4] + 80042d4: f423 2100 bic.w r1, r3, #524288 ; 0x80000 + 80042d8: 687b ldr r3, [r7, #4] + 80042da: 6cda ldr r2, [r3, #76] ; 0x4c + 80042dc: 687b ldr r3, [r7, #4] + 80042de: 681b ldr r3, [r3, #0] + 80042e0: 430a orrs r2, r1 + 80042e2: 605a str r2, [r3, #4] } } - 80044d8: bf00 nop - 80044da: 370c adds r7, #12 - 80044dc: 46bd mov sp, r7 - 80044de: bc80 pop {r7} - 80044e0: 4770 bx lr + 80042e4: bf00 nop + 80042e6: 370c adds r7, #12 + 80042e8: 46bd mov sp, r7 + 80042ea: bc80 pop {r7} + 80042ec: 4770 bx lr -080044e2 : +080042ee : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { - 80044e2: b580 push {r7, lr} - 80044e4: b086 sub sp, #24 - 80044e6: af02 add r7, sp, #8 - 80044e8: 6078 str r0, [r7, #4] + 80042ee: b580 push {r7, lr} + 80042f0: b086 sub sp, #24 + 80042f2: af02 add r7, sp, #8 + 80042f4: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - 80044ea: 687b ldr r3, [r7, #4] - 80044ec: 2200 movs r2, #0 - 80044ee: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + 80042f6: 687b ldr r3, [r7, #4] + 80042f8: 2200 movs r2, #0 + 80042fa: f8c3 2090 str.w r2, [r3, #144] ; 0x90 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - 80044f2: f7fd f9d3 bl 800189c - 80044f6: 60f8 str r0, [r7, #12] + 80042fe: f7fd f9d3 bl 80016a8 + 8004302: 60f8 str r0, [r7, #12] /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - 80044f8: 687b ldr r3, [r7, #4] - 80044fa: 681b ldr r3, [r3, #0] - 80044fc: 681b ldr r3, [r3, #0] - 80044fe: f003 0308 and.w r3, r3, #8 - 8004502: 2b08 cmp r3, #8 - 8004504: d10e bne.n 8004524 + 8004304: 687b ldr r3, [r7, #4] + 8004306: 681b ldr r3, [r3, #0] + 8004308: 681b ldr r3, [r3, #0] + 800430a: f003 0308 and.w r3, r3, #8 + 800430e: 2b08 cmp r3, #8 + 8004310: d10e bne.n 8004330 { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - 8004506: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 - 800450a: 9300 str r3, [sp, #0] - 800450c: 68fb ldr r3, [r7, #12] - 800450e: 2200 movs r2, #0 - 8004510: f44f 1100 mov.w r1, #2097152 ; 0x200000 - 8004514: 6878 ldr r0, [r7, #4] - 8004516: f000 f832 bl 800457e - 800451a: 4603 mov r3, r0 - 800451c: 2b00 cmp r3, #0 - 800451e: d001 beq.n 8004524 + 8004312: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 + 8004316: 9300 str r3, [sp, #0] + 8004318: 68fb ldr r3, [r7, #12] + 800431a: 2200 movs r2, #0 + 800431c: f44f 1100 mov.w r1, #2097152 ; 0x200000 + 8004320: 6878 ldr r0, [r7, #4] + 8004322: f000 f832 bl 800438a + 8004326: 4603 mov r3, r0 + 8004328: 2b00 cmp r3, #0 + 800432a: d001 beq.n 8004330 { /* Timeout occurred */ return HAL_TIMEOUT; - 8004520: 2303 movs r3, #3 - 8004522: e028 b.n 8004576 + 800432c: 2303 movs r3, #3 + 800432e: e028 b.n 8004382 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - 8004524: 687b ldr r3, [r7, #4] - 8004526: 681b ldr r3, [r3, #0] - 8004528: 681b ldr r3, [r3, #0] - 800452a: f003 0304 and.w r3, r3, #4 - 800452e: 2b04 cmp r3, #4 - 8004530: d10e bne.n 8004550 + 8004330: 687b ldr r3, [r7, #4] + 8004332: 681b ldr r3, [r3, #0] + 8004334: 681b ldr r3, [r3, #0] + 8004336: f003 0304 and.w r3, r3, #4 + 800433a: 2b04 cmp r3, #4 + 800433c: d10e bne.n 800435c { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - 8004532: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 - 8004536: 9300 str r3, [sp, #0] - 8004538: 68fb ldr r3, [r7, #12] - 800453a: 2200 movs r2, #0 - 800453c: f44f 0180 mov.w r1, #4194304 ; 0x400000 - 8004540: 6878 ldr r0, [r7, #4] - 8004542: f000 f81c bl 800457e - 8004546: 4603 mov r3, r0 - 8004548: 2b00 cmp r3, #0 - 800454a: d001 beq.n 8004550 + 800433e: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 + 8004342: 9300 str r3, [sp, #0] + 8004344: 68fb ldr r3, [r7, #12] + 8004346: 2200 movs r2, #0 + 8004348: f44f 0180 mov.w r1, #4194304 ; 0x400000 + 800434c: 6878 ldr r0, [r7, #4] + 800434e: f000 f81c bl 800438a + 8004352: 4603 mov r3, r0 + 8004354: 2b00 cmp r3, #0 + 8004356: d001 beq.n 800435c { /* Timeout occurred */ return HAL_TIMEOUT; - 800454c: 2303 movs r3, #3 - 800454e: e012 b.n 8004576 + 8004358: 2303 movs r3, #3 + 800435a: e012 b.n 8004382 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; - 8004550: 687b ldr r3, [r7, #4] - 8004552: 2220 movs r2, #32 - 8004554: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + 800435c: 687b ldr r3, [r7, #4] + 800435e: 2220 movs r2, #32 + 8004360: f8c3 2088 str.w r2, [r3, #136] ; 0x88 huart->RxState = HAL_UART_STATE_READY; - 8004558: 687b ldr r3, [r7, #4] - 800455a: 2220 movs r2, #32 - 800455c: f8c3 208c str.w r2, [r3, #140] ; 0x8c + 8004364: 687b ldr r3, [r7, #4] + 8004366: 2220 movs r2, #32 + 8004368: f8c3 208c str.w r2, [r3, #140] ; 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 8004560: 687b ldr r3, [r7, #4] - 8004562: 2200 movs r2, #0 - 8004564: 66da str r2, [r3, #108] ; 0x6c + 800436c: 687b ldr r3, [r7, #4] + 800436e: 2200 movs r2, #0 + 8004370: 66da str r2, [r3, #108] ; 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; - 8004566: 687b ldr r3, [r7, #4] - 8004568: 2200 movs r2, #0 - 800456a: 671a str r2, [r3, #112] ; 0x70 + 8004372: 687b ldr r3, [r7, #4] + 8004374: 2200 movs r2, #0 + 8004376: 671a str r2, [r3, #112] ; 0x70 __HAL_UNLOCK(huart); - 800456c: 687b ldr r3, [r7, #4] - 800456e: 2200 movs r2, #0 - 8004570: f883 2084 strb.w r2, [r3, #132] ; 0x84 + 8004378: 687b ldr r3, [r7, #4] + 800437a: 2200 movs r2, #0 + 800437c: f883 2084 strb.w r2, [r3, #132] ; 0x84 return HAL_OK; - 8004574: 2300 movs r3, #0 + 8004380: 2300 movs r3, #0 } - 8004576: 4618 mov r0, r3 - 8004578: 3710 adds r7, #16 - 800457a: 46bd mov sp, r7 - 800457c: bd80 pop {r7, pc} + 8004382: 4618 mov r0, r3 + 8004384: 3710 adds r7, #16 + 8004386: 46bd mov sp, r7 + 8004388: bd80 pop {r7, pc} -0800457e : +0800438a : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - 800457e: b580 push {r7, lr} - 8004580: b09c sub sp, #112 ; 0x70 - 8004582: af00 add r7, sp, #0 - 8004584: 60f8 str r0, [r7, #12] - 8004586: 60b9 str r1, [r7, #8] - 8004588: 603b str r3, [r7, #0] - 800458a: 4613 mov r3, r2 - 800458c: 71fb strb r3, [r7, #7] + 800438a: b580 push {r7, lr} + 800438c: b09c sub sp, #112 ; 0x70 + 800438e: af00 add r7, sp, #0 + 8004390: 60f8 str r0, [r7, #12] + 8004392: 60b9 str r1, [r7, #8] + 8004394: 603b str r3, [r7, #0] + 8004396: 4613 mov r3, r2 + 8004398: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 800458e: e0a9 b.n 80046e4 + 800439a: e0a9 b.n 80044f0 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) - 8004590: 6fbb ldr r3, [r7, #120] ; 0x78 - 8004592: f1b3 3fff cmp.w r3, #4294967295 - 8004596: f000 80a5 beq.w 80046e4 + 800439c: 6fbb ldr r3, [r7, #120] ; 0x78 + 800439e: f1b3 3fff cmp.w r3, #4294967295 + 80043a2: f000 80a5 beq.w 80044f0 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - 800459a: f7fd f97f bl 800189c - 800459e: 4602 mov r2, r0 - 80045a0: 683b ldr r3, [r7, #0] - 80045a2: 1ad3 subs r3, r2, r3 - 80045a4: 6fba ldr r2, [r7, #120] ; 0x78 - 80045a6: 429a cmp r2, r3 - 80045a8: d302 bcc.n 80045b0 - 80045aa: 6fbb ldr r3, [r7, #120] ; 0x78 - 80045ac: 2b00 cmp r3, #0 - 80045ae: d140 bne.n 8004632 + 80043a6: f7fd f97f bl 80016a8 + 80043aa: 4602 mov r2, r0 + 80043ac: 683b ldr r3, [r7, #0] + 80043ae: 1ad3 subs r3, r2, r3 + 80043b0: 6fba ldr r2, [r7, #120] ; 0x78 + 80043b2: 429a cmp r2, r3 + 80043b4: d302 bcc.n 80043bc + 80043b6: 6fbb ldr r3, [r7, #120] ; 0x78 + 80043b8: 2b00 cmp r3, #0 + 80043ba: d140 bne.n 800443e { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | - 80045b0: 68fb ldr r3, [r7, #12] - 80045b2: 681b ldr r3, [r3, #0] - 80045b4: 653b str r3, [r7, #80] ; 0x50 + 80043bc: 68fb ldr r3, [r7, #12] + 80043be: 681b ldr r3, [r3, #0] + 80043c0: 653b str r3, [r7, #80] ; 0x50 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 80045b6: 6d3b ldr r3, [r7, #80] ; 0x50 - 80045b8: e853 3f00 ldrex r3, [r3] - 80045bc: 64fb str r3, [r7, #76] ; 0x4c + 80043c2: 6d3b ldr r3, [r7, #80] ; 0x50 + 80043c4: e853 3f00 ldrex r3, [r3] + 80043c8: 64fb str r3, [r7, #76] ; 0x4c return(result); - 80045be: 6cfb ldr r3, [r7, #76] ; 0x4c - 80045c0: f423 73d0 bic.w r3, r3, #416 ; 0x1a0 - 80045c4: 667b str r3, [r7, #100] ; 0x64 - 80045c6: 68fb ldr r3, [r7, #12] - 80045c8: 681b ldr r3, [r3, #0] - 80045ca: 461a mov r2, r3 - 80045cc: 6e7b ldr r3, [r7, #100] ; 0x64 - 80045ce: 65fb str r3, [r7, #92] ; 0x5c - 80045d0: 65ba str r2, [r7, #88] ; 0x58 + 80043ca: 6cfb ldr r3, [r7, #76] ; 0x4c + 80043cc: f423 73d0 bic.w r3, r3, #416 ; 0x1a0 + 80043d0: 667b str r3, [r7, #100] ; 0x64 + 80043d2: 68fb ldr r3, [r7, #12] + 80043d4: 681b ldr r3, [r3, #0] + 80043d6: 461a mov r2, r3 + 80043d8: 6e7b ldr r3, [r7, #100] ; 0x64 + 80043da: 65fb str r3, [r7, #92] ; 0x5c + 80043dc: 65ba str r2, [r7, #88] ; 0x58 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 80045d2: 6db9 ldr r1, [r7, #88] ; 0x58 - 80045d4: 6dfa ldr r2, [r7, #92] ; 0x5c - 80045d6: e841 2300 strex r3, r2, [r1] - 80045da: 657b str r3, [r7, #84] ; 0x54 + 80043de: 6db9 ldr r1, [r7, #88] ; 0x58 + 80043e0: 6dfa ldr r2, [r7, #92] ; 0x5c + 80043e2: e841 2300 strex r3, r2, [r1] + 80043e6: 657b str r3, [r7, #84] ; 0x54 return(result); - 80045dc: 6d7b ldr r3, [r7, #84] ; 0x54 - 80045de: 2b00 cmp r3, #0 - 80045e0: d1e6 bne.n 80045b0 + 80043e8: 6d7b ldr r3, [r7, #84] ; 0x54 + 80043ea: 2b00 cmp r3, #0 + 80043ec: d1e6 bne.n 80043bc USART_CR1_TXEIE_TXFNFIE)); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 80045e2: 68fb ldr r3, [r7, #12] - 80045e4: 681b ldr r3, [r3, #0] - 80045e6: 3308 adds r3, #8 - 80045e8: 63fb str r3, [r7, #60] ; 0x3c + 80043ee: 68fb ldr r3, [r7, #12] + 80043f0: 681b ldr r3, [r3, #0] + 80043f2: 3308 adds r3, #8 + 80043f4: 63fb str r3, [r7, #60] ; 0x3c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 80045ea: 6bfb ldr r3, [r7, #60] ; 0x3c - 80045ec: e853 3f00 ldrex r3, [r3] - 80045f0: 63bb str r3, [r7, #56] ; 0x38 + 80043f6: 6bfb ldr r3, [r7, #60] ; 0x3c + 80043f8: e853 3f00 ldrex r3, [r3] + 80043fc: 63bb str r3, [r7, #56] ; 0x38 return(result); - 80045f2: 6bbb ldr r3, [r7, #56] ; 0x38 - 80045f4: f023 0301 bic.w r3, r3, #1 - 80045f8: 663b str r3, [r7, #96] ; 0x60 - 80045fa: 68fb ldr r3, [r7, #12] - 80045fc: 681b ldr r3, [r3, #0] - 80045fe: 3308 adds r3, #8 - 8004600: 6e3a ldr r2, [r7, #96] ; 0x60 - 8004602: 64ba str r2, [r7, #72] ; 0x48 - 8004604: 647b str r3, [r7, #68] ; 0x44 + 80043fe: 6bbb ldr r3, [r7, #56] ; 0x38 + 8004400: f023 0301 bic.w r3, r3, #1 + 8004404: 663b str r3, [r7, #96] ; 0x60 + 8004406: 68fb ldr r3, [r7, #12] + 8004408: 681b ldr r3, [r3, #0] + 800440a: 3308 adds r3, #8 + 800440c: 6e3a ldr r2, [r7, #96] ; 0x60 + 800440e: 64ba str r2, [r7, #72] ; 0x48 + 8004410: 647b str r3, [r7, #68] ; 0x44 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8004606: 6c79 ldr r1, [r7, #68] ; 0x44 - 8004608: 6cba ldr r2, [r7, #72] ; 0x48 - 800460a: e841 2300 strex r3, r2, [r1] - 800460e: 643b str r3, [r7, #64] ; 0x40 + 8004412: 6c79 ldr r1, [r7, #68] ; 0x44 + 8004414: 6cba ldr r2, [r7, #72] ; 0x48 + 8004416: e841 2300 strex r3, r2, [r1] + 800441a: 643b str r3, [r7, #64] ; 0x40 return(result); - 8004610: 6c3b ldr r3, [r7, #64] ; 0x40 - 8004612: 2b00 cmp r3, #0 - 8004614: d1e5 bne.n 80045e2 + 800441c: 6c3b ldr r3, [r7, #64] ; 0x40 + 800441e: 2b00 cmp r3, #0 + 8004420: d1e5 bne.n 80043ee huart->gState = HAL_UART_STATE_READY; - 8004616: 68fb ldr r3, [r7, #12] - 8004618: 2220 movs r2, #32 - 800461a: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + 8004422: 68fb ldr r3, [r7, #12] + 8004424: 2220 movs r2, #32 + 8004426: f8c3 2088 str.w r2, [r3, #136] ; 0x88 huart->RxState = HAL_UART_STATE_READY; - 800461e: 68fb ldr r3, [r7, #12] - 8004620: 2220 movs r2, #32 - 8004622: f8c3 208c str.w r2, [r3, #140] ; 0x8c + 800442a: 68fb ldr r3, [r7, #12] + 800442c: 2220 movs r2, #32 + 800442e: f8c3 208c str.w r2, [r3, #140] ; 0x8c __HAL_UNLOCK(huart); - 8004626: 68fb ldr r3, [r7, #12] - 8004628: 2200 movs r2, #0 - 800462a: f883 2084 strb.w r2, [r3, #132] ; 0x84 + 8004432: 68fb ldr r3, [r7, #12] + 8004434: 2200 movs r2, #0 + 8004436: f883 2084 strb.w r2, [r3, #132] ; 0x84 return HAL_TIMEOUT; - 800462e: 2303 movs r3, #3 - 8004630: e069 b.n 8004706 + 800443a: 2303 movs r3, #3 + 800443c: e069 b.n 8004512 } if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) - 8004632: 68fb ldr r3, [r7, #12] - 8004634: 681b ldr r3, [r3, #0] - 8004636: 681b ldr r3, [r3, #0] - 8004638: f003 0304 and.w r3, r3, #4 - 800463c: 2b00 cmp r3, #0 - 800463e: d051 beq.n 80046e4 + 800443e: 68fb ldr r3, [r7, #12] + 8004440: 681b ldr r3, [r3, #0] + 8004442: 681b ldr r3, [r3, #0] + 8004444: f003 0304 and.w r3, r3, #4 + 8004448: 2b00 cmp r3, #0 + 800444a: d051 beq.n 80044f0 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) - 8004640: 68fb ldr r3, [r7, #12] - 8004642: 681b ldr r3, [r3, #0] - 8004644: 69db ldr r3, [r3, #28] - 8004646: f403 6300 and.w r3, r3, #2048 ; 0x800 - 800464a: f5b3 6f00 cmp.w r3, #2048 ; 0x800 - 800464e: d149 bne.n 80046e4 + 800444c: 68fb ldr r3, [r7, #12] + 800444e: 681b ldr r3, [r3, #0] + 8004450: 69db ldr r3, [r3, #28] + 8004452: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8004456: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 800445a: d149 bne.n 80044f0 { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - 8004650: 68fb ldr r3, [r7, #12] - 8004652: 681b ldr r3, [r3, #0] - 8004654: f44f 6200 mov.w r2, #2048 ; 0x800 - 8004658: 621a str r2, [r3, #32] + 800445c: 68fb ldr r3, [r7, #12] + 800445e: 681b ldr r3, [r3, #0] + 8004460: f44f 6200 mov.w r2, #2048 ; 0x800 + 8004464: 621a str r2, [r3, #32] /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | - 800465a: 68fb ldr r3, [r7, #12] - 800465c: 681b ldr r3, [r3, #0] - 800465e: 62bb str r3, [r7, #40] ; 0x28 + 8004466: 68fb ldr r3, [r7, #12] + 8004468: 681b ldr r3, [r3, #0] + 800446a: 62bb str r3, [r7, #40] ; 0x28 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8004660: 6abb ldr r3, [r7, #40] ; 0x28 - 8004662: e853 3f00 ldrex r3, [r3] - 8004666: 627b str r3, [r7, #36] ; 0x24 + 800446c: 6abb ldr r3, [r7, #40] ; 0x28 + 800446e: e853 3f00 ldrex r3, [r3] + 8004472: 627b str r3, [r7, #36] ; 0x24 return(result); - 8004668: 6a7b ldr r3, [r7, #36] ; 0x24 - 800466a: f423 73d0 bic.w r3, r3, #416 ; 0x1a0 - 800466e: 66fb str r3, [r7, #108] ; 0x6c - 8004670: 68fb ldr r3, [r7, #12] - 8004672: 681b ldr r3, [r3, #0] - 8004674: 461a mov r2, r3 - 8004676: 6efb ldr r3, [r7, #108] ; 0x6c - 8004678: 637b str r3, [r7, #52] ; 0x34 - 800467a: 633a str r2, [r7, #48] ; 0x30 + 8004474: 6a7b ldr r3, [r7, #36] ; 0x24 + 8004476: f423 73d0 bic.w r3, r3, #416 ; 0x1a0 + 800447a: 66fb str r3, [r7, #108] ; 0x6c + 800447c: 68fb ldr r3, [r7, #12] + 800447e: 681b ldr r3, [r3, #0] + 8004480: 461a mov r2, r3 + 8004482: 6efb ldr r3, [r7, #108] ; 0x6c + 8004484: 637b str r3, [r7, #52] ; 0x34 + 8004486: 633a str r2, [r7, #48] ; 0x30 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800467c: 6b39 ldr r1, [r7, #48] ; 0x30 - 800467e: 6b7a ldr r2, [r7, #52] ; 0x34 - 8004680: e841 2300 strex r3, r2, [r1] - 8004684: 62fb str r3, [r7, #44] ; 0x2c + 8004488: 6b39 ldr r1, [r7, #48] ; 0x30 + 800448a: 6b7a ldr r2, [r7, #52] ; 0x34 + 800448c: e841 2300 strex r3, r2, [r1] + 8004490: 62fb str r3, [r7, #44] ; 0x2c return(result); - 8004686: 6afb ldr r3, [r7, #44] ; 0x2c - 8004688: 2b00 cmp r3, #0 - 800468a: d1e6 bne.n 800465a + 8004492: 6afb ldr r3, [r7, #44] ; 0x2c + 8004494: 2b00 cmp r3, #0 + 8004496: d1e6 bne.n 8004466 USART_CR1_TXEIE_TXFNFIE)); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 800468c: 68fb ldr r3, [r7, #12] - 800468e: 681b ldr r3, [r3, #0] - 8004690: 3308 adds r3, #8 - 8004692: 617b str r3, [r7, #20] + 8004498: 68fb ldr r3, [r7, #12] + 800449a: 681b ldr r3, [r3, #0] + 800449c: 3308 adds r3, #8 + 800449e: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8004694: 697b ldr r3, [r7, #20] - 8004696: e853 3f00 ldrex r3, [r3] - 800469a: 613b str r3, [r7, #16] + 80044a0: 697b ldr r3, [r7, #20] + 80044a2: e853 3f00 ldrex r3, [r3] + 80044a6: 613b str r3, [r7, #16] return(result); - 800469c: 693b ldr r3, [r7, #16] - 800469e: f023 0301 bic.w r3, r3, #1 - 80046a2: 66bb str r3, [r7, #104] ; 0x68 - 80046a4: 68fb ldr r3, [r7, #12] - 80046a6: 681b ldr r3, [r3, #0] - 80046a8: 3308 adds r3, #8 - 80046aa: 6eba ldr r2, [r7, #104] ; 0x68 - 80046ac: 623a str r2, [r7, #32] - 80046ae: 61fb str r3, [r7, #28] + 80044a8: 693b ldr r3, [r7, #16] + 80044aa: f023 0301 bic.w r3, r3, #1 + 80044ae: 66bb str r3, [r7, #104] ; 0x68 + 80044b0: 68fb ldr r3, [r7, #12] + 80044b2: 681b ldr r3, [r3, #0] + 80044b4: 3308 adds r3, #8 + 80044b6: 6eba ldr r2, [r7, #104] ; 0x68 + 80044b8: 623a str r2, [r7, #32] + 80044ba: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 80046b0: 69f9 ldr r1, [r7, #28] - 80046b2: 6a3a ldr r2, [r7, #32] - 80046b4: e841 2300 strex r3, r2, [r1] - 80046b8: 61bb str r3, [r7, #24] + 80044bc: 69f9 ldr r1, [r7, #28] + 80044be: 6a3a ldr r2, [r7, #32] + 80044c0: e841 2300 strex r3, r2, [r1] + 80044c4: 61bb str r3, [r7, #24] return(result); - 80046ba: 69bb ldr r3, [r7, #24] - 80046bc: 2b00 cmp r3, #0 - 80046be: d1e5 bne.n 800468c + 80044c6: 69bb ldr r3, [r7, #24] + 80044c8: 2b00 cmp r3, #0 + 80044ca: d1e5 bne.n 8004498 huart->gState = HAL_UART_STATE_READY; - 80046c0: 68fb ldr r3, [r7, #12] - 80046c2: 2220 movs r2, #32 - 80046c4: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + 80044cc: 68fb ldr r3, [r7, #12] + 80044ce: 2220 movs r2, #32 + 80044d0: f8c3 2088 str.w r2, [r3, #136] ; 0x88 huart->RxState = HAL_UART_STATE_READY; - 80046c8: 68fb ldr r3, [r7, #12] - 80046ca: 2220 movs r2, #32 - 80046cc: f8c3 208c str.w r2, [r3, #140] ; 0x8c + 80044d4: 68fb ldr r3, [r7, #12] + 80044d6: 2220 movs r2, #32 + 80044d8: f8c3 208c str.w r2, [r3, #140] ; 0x8c huart->ErrorCode = HAL_UART_ERROR_RTO; - 80046d0: 68fb ldr r3, [r7, #12] - 80046d2: 2220 movs r2, #32 - 80046d4: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + 80044dc: 68fb ldr r3, [r7, #12] + 80044de: 2220 movs r2, #32 + 80044e0: f8c3 2090 str.w r2, [r3, #144] ; 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); - 80046d8: 68fb ldr r3, [r7, #12] - 80046da: 2200 movs r2, #0 - 80046dc: f883 2084 strb.w r2, [r3, #132] ; 0x84 + 80044e4: 68fb ldr r3, [r7, #12] + 80044e6: 2200 movs r2, #0 + 80044e8: f883 2084 strb.w r2, [r3, #132] ; 0x84 return HAL_TIMEOUT; - 80046e0: 2303 movs r3, #3 - 80046e2: e010 b.n 8004706 + 80044ec: 2303 movs r3, #3 + 80044ee: e010 b.n 8004512 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 80046e4: 68fb ldr r3, [r7, #12] - 80046e6: 681b ldr r3, [r3, #0] - 80046e8: 69da ldr r2, [r3, #28] - 80046ea: 68bb ldr r3, [r7, #8] - 80046ec: 4013 ands r3, r2 - 80046ee: 68ba ldr r2, [r7, #8] - 80046f0: 429a cmp r2, r3 - 80046f2: bf0c ite eq - 80046f4: 2301 moveq r3, #1 - 80046f6: 2300 movne r3, #0 - 80046f8: b2db uxtb r3, r3 - 80046fa: 461a mov r2, r3 - 80046fc: 79fb ldrb r3, [r7, #7] - 80046fe: 429a cmp r2, r3 - 8004700: f43f af46 beq.w 8004590 + 80044f0: 68fb ldr r3, [r7, #12] + 80044f2: 681b ldr r3, [r3, #0] + 80044f4: 69da ldr r2, [r3, #28] + 80044f6: 68bb ldr r3, [r7, #8] + 80044f8: 4013 ands r3, r2 + 80044fa: 68ba ldr r2, [r7, #8] + 80044fc: 429a cmp r2, r3 + 80044fe: bf0c ite eq + 8004500: 2301 moveq r3, #1 + 8004502: 2300 movne r3, #0 + 8004504: b2db uxtb r3, r3 + 8004506: 461a mov r2, r3 + 8004508: 79fb ldrb r3, [r7, #7] + 800450a: 429a cmp r2, r3 + 800450c: f43f af46 beq.w 800439c } } } } return HAL_OK; - 8004704: 2300 movs r3, #0 + 8004510: 2300 movs r3, #0 } - 8004706: 4618 mov r0, r3 - 8004708: 3770 adds r7, #112 ; 0x70 - 800470a: 46bd mov sp, r7 - 800470c: bd80 pop {r7, pc} + 8004512: 4618 mov r0, r3 + 8004514: 3770 adds r7, #112 ; 0x70 + 8004516: 46bd mov sp, r7 + 8004518: bd80 pop {r7, pc} -0800470e : +0800451a : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { - 800470e: b480 push {r7} - 8004710: b085 sub sp, #20 - 8004712: af00 add r7, sp, #0 - 8004714: 6078 str r0, [r7, #4] + 800451a: b480 push {r7} + 800451c: b085 sub sp, #20 + 800451e: af00 add r7, sp, #0 + 8004520: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); - 8004716: 687b ldr r3, [r7, #4] - 8004718: f893 3084 ldrb.w r3, [r3, #132] ; 0x84 - 800471c: 2b01 cmp r3, #1 - 800471e: d101 bne.n 8004724 - 8004720: 2302 movs r3, #2 - 8004722: e027 b.n 8004774 - 8004724: 687b ldr r3, [r7, #4] - 8004726: 2201 movs r2, #1 - 8004728: f883 2084 strb.w r2, [r3, #132] ; 0x84 + 8004522: 687b ldr r3, [r7, #4] + 8004524: f893 3084 ldrb.w r3, [r3, #132] ; 0x84 + 8004528: 2b01 cmp r3, #1 + 800452a: d101 bne.n 8004530 + 800452c: 2302 movs r3, #2 + 800452e: e027 b.n 8004580 + 8004530: 687b ldr r3, [r7, #4] + 8004532: 2201 movs r2, #1 + 8004534: f883 2084 strb.w r2, [r3, #132] ; 0x84 huart->gState = HAL_UART_STATE_BUSY; - 800472c: 687b ldr r3, [r7, #4] - 800472e: 2224 movs r2, #36 ; 0x24 - 8004730: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + 8004538: 687b ldr r3, [r7, #4] + 800453a: 2224 movs r2, #36 ; 0x24 + 800453c: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - 8004734: 687b ldr r3, [r7, #4] - 8004736: 681b ldr r3, [r3, #0] - 8004738: 681b ldr r3, [r3, #0] - 800473a: 60fb str r3, [r7, #12] + 8004540: 687b ldr r3, [r7, #4] + 8004542: 681b ldr r3, [r3, #0] + 8004544: 681b ldr r3, [r3, #0] + 8004546: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); - 800473c: 687b ldr r3, [r7, #4] - 800473e: 681b ldr r3, [r3, #0] - 8004740: 681a ldr r2, [r3, #0] - 8004742: 687b ldr r3, [r7, #4] - 8004744: 681b ldr r3, [r3, #0] - 8004746: f022 0201 bic.w r2, r2, #1 - 800474a: 601a str r2, [r3, #0] + 8004548: 687b ldr r3, [r7, #4] + 800454a: 681b ldr r3, [r3, #0] + 800454c: 681a ldr r2, [r3, #0] + 800454e: 687b ldr r3, [r7, #4] + 8004550: 681b ldr r3, [r3, #0] + 8004552: f022 0201 bic.w r2, r2, #1 + 8004556: 601a str r2, [r3, #0] /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); - 800474c: 68fb ldr r3, [r7, #12] - 800474e: f023 5300 bic.w r3, r3, #536870912 ; 0x20000000 - 8004752: 60fb str r3, [r7, #12] + 8004558: 68fb ldr r3, [r7, #12] + 800455a: f023 5300 bic.w r3, r3, #536870912 ; 0x20000000 + 800455e: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; - 8004754: 687b ldr r3, [r7, #4] - 8004756: 2200 movs r2, #0 - 8004758: 665a str r2, [r3, #100] ; 0x64 + 8004560: 687b ldr r3, [r7, #4] + 8004562: 2200 movs r2, #0 + 8004564: 665a str r2, [r3, #100] ; 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); - 800475a: 687b ldr r3, [r7, #4] - 800475c: 681b ldr r3, [r3, #0] - 800475e: 68fa ldr r2, [r7, #12] - 8004760: 601a str r2, [r3, #0] + 8004566: 687b ldr r3, [r7, #4] + 8004568: 681b ldr r3, [r3, #0] + 800456a: 68fa ldr r2, [r7, #12] + 800456c: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; - 8004762: 687b ldr r3, [r7, #4] - 8004764: 2220 movs r2, #32 - 8004766: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + 800456e: 687b ldr r3, [r7, #4] + 8004570: 2220 movs r2, #32 + 8004572: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); - 800476a: 687b ldr r3, [r7, #4] - 800476c: 2200 movs r2, #0 - 800476e: f883 2084 strb.w r2, [r3, #132] ; 0x84 + 8004576: 687b ldr r3, [r7, #4] + 8004578: 2200 movs r2, #0 + 800457a: f883 2084 strb.w r2, [r3, #132] ; 0x84 return HAL_OK; - 8004772: 2300 movs r3, #0 + 800457e: 2300 movs r3, #0 } - 8004774: 4618 mov r0, r3 - 8004776: 3714 adds r7, #20 - 8004778: 46bd mov sp, r7 - 800477a: bc80 pop {r7} - 800477c: 4770 bx lr + 8004580: 4618 mov r0, r3 + 8004582: 3714 adds r7, #20 + 8004584: 46bd mov sp, r7 + 8004586: bc80 pop {r7} + 8004588: 4770 bx lr -0800477e : +0800458a : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { - 800477e: b580 push {r7, lr} - 8004780: b084 sub sp, #16 - 8004782: af00 add r7, sp, #0 - 8004784: 6078 str r0, [r7, #4] - 8004786: 6039 str r1, [r7, #0] + 800458a: b580 push {r7, lr} + 800458c: b084 sub sp, #16 + 800458e: af00 add r7, sp, #0 + 8004590: 6078 str r0, [r7, #4] + 8004592: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); - 8004788: 687b ldr r3, [r7, #4] - 800478a: f893 3084 ldrb.w r3, [r3, #132] ; 0x84 - 800478e: 2b01 cmp r3, #1 - 8004790: d101 bne.n 8004796 - 8004792: 2302 movs r3, #2 - 8004794: e02d b.n 80047f2 - 8004796: 687b ldr r3, [r7, #4] - 8004798: 2201 movs r2, #1 - 800479a: f883 2084 strb.w r2, [r3, #132] ; 0x84 + 8004594: 687b ldr r3, [r7, #4] + 8004596: f893 3084 ldrb.w r3, [r3, #132] ; 0x84 + 800459a: 2b01 cmp r3, #1 + 800459c: d101 bne.n 80045a2 + 800459e: 2302 movs r3, #2 + 80045a0: e02d b.n 80045fe + 80045a2: 687b ldr r3, [r7, #4] + 80045a4: 2201 movs r2, #1 + 80045a6: f883 2084 strb.w r2, [r3, #132] ; 0x84 huart->gState = HAL_UART_STATE_BUSY; - 800479e: 687b ldr r3, [r7, #4] - 80047a0: 2224 movs r2, #36 ; 0x24 - 80047a2: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + 80045aa: 687b ldr r3, [r7, #4] + 80045ac: 2224 movs r2, #36 ; 0x24 + 80045ae: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - 80047a6: 687b ldr r3, [r7, #4] - 80047a8: 681b ldr r3, [r3, #0] - 80047aa: 681b ldr r3, [r3, #0] - 80047ac: 60fb str r3, [r7, #12] + 80045b2: 687b ldr r3, [r7, #4] + 80045b4: 681b ldr r3, [r3, #0] + 80045b6: 681b ldr r3, [r3, #0] + 80045b8: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); - 80047ae: 687b ldr r3, [r7, #4] - 80047b0: 681b ldr r3, [r3, #0] - 80047b2: 681a ldr r2, [r3, #0] - 80047b4: 687b ldr r3, [r7, #4] - 80047b6: 681b ldr r3, [r3, #0] - 80047b8: f022 0201 bic.w r2, r2, #1 - 80047bc: 601a str r2, [r3, #0] + 80045ba: 687b ldr r3, [r7, #4] + 80045bc: 681b ldr r3, [r3, #0] + 80045be: 681a ldr r2, [r3, #0] + 80045c0: 687b ldr r3, [r7, #4] + 80045c2: 681b ldr r3, [r3, #0] + 80045c4: f022 0201 bic.w r2, r2, #1 + 80045c8: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); - 80047be: 687b ldr r3, [r7, #4] - 80047c0: 681b ldr r3, [r3, #0] - 80047c2: 689b ldr r3, [r3, #8] - 80047c4: f023 4160 bic.w r1, r3, #3758096384 ; 0xe0000000 - 80047c8: 687b ldr r3, [r7, #4] - 80047ca: 681b ldr r3, [r3, #0] - 80047cc: 683a ldr r2, [r7, #0] - 80047ce: 430a orrs r2, r1 - 80047d0: 609a str r2, [r3, #8] + 80045ca: 687b ldr r3, [r7, #4] + 80045cc: 681b ldr r3, [r3, #0] + 80045ce: 689b ldr r3, [r3, #8] + 80045d0: f023 4160 bic.w r1, r3, #3758096384 ; 0xe0000000 + 80045d4: 687b ldr r3, [r7, #4] + 80045d6: 681b ldr r3, [r3, #0] + 80045d8: 683a ldr r2, [r7, #0] + 80045da: 430a orrs r2, r1 + 80045dc: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); - 80047d2: 6878 ldr r0, [r7, #4] - 80047d4: f000 f850 bl 8004878 + 80045de: 6878 ldr r0, [r7, #4] + 80045e0: f000 f850 bl 8004684 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); - 80047d8: 687b ldr r3, [r7, #4] - 80047da: 681b ldr r3, [r3, #0] - 80047dc: 68fa ldr r2, [r7, #12] - 80047de: 601a str r2, [r3, #0] + 80045e4: 687b ldr r3, [r7, #4] + 80045e6: 681b ldr r3, [r3, #0] + 80045e8: 68fa ldr r2, [r7, #12] + 80045ea: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; - 80047e0: 687b ldr r3, [r7, #4] - 80047e2: 2220 movs r2, #32 - 80047e4: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + 80045ec: 687b ldr r3, [r7, #4] + 80045ee: 2220 movs r2, #32 + 80045f0: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); - 80047e8: 687b ldr r3, [r7, #4] - 80047ea: 2200 movs r2, #0 - 80047ec: f883 2084 strb.w r2, [r3, #132] ; 0x84 + 80045f4: 687b ldr r3, [r7, #4] + 80045f6: 2200 movs r2, #0 + 80045f8: f883 2084 strb.w r2, [r3, #132] ; 0x84 return HAL_OK; - 80047f0: 2300 movs r3, #0 + 80045fc: 2300 movs r3, #0 } - 80047f2: 4618 mov r0, r3 - 80047f4: 3710 adds r7, #16 - 80047f6: 46bd mov sp, r7 - 80047f8: bd80 pop {r7, pc} + 80045fe: 4618 mov r0, r3 + 8004600: 3710 adds r7, #16 + 8004602: 46bd mov sp, r7 + 8004604: bd80 pop {r7, pc} -080047fa : +08004606 : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { - 80047fa: b580 push {r7, lr} - 80047fc: b084 sub sp, #16 - 80047fe: af00 add r7, sp, #0 - 8004800: 6078 str r0, [r7, #4] - 8004802: 6039 str r1, [r7, #0] + 8004606: b580 push {r7, lr} + 8004608: b084 sub sp, #16 + 800460a: af00 add r7, sp, #0 + 800460c: 6078 str r0, [r7, #4] + 800460e: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); - 8004804: 687b ldr r3, [r7, #4] - 8004806: f893 3084 ldrb.w r3, [r3, #132] ; 0x84 - 800480a: 2b01 cmp r3, #1 - 800480c: d101 bne.n 8004812 - 800480e: 2302 movs r3, #2 - 8004810: e02d b.n 800486e - 8004812: 687b ldr r3, [r7, #4] - 8004814: 2201 movs r2, #1 - 8004816: f883 2084 strb.w r2, [r3, #132] ; 0x84 + 8004610: 687b ldr r3, [r7, #4] + 8004612: f893 3084 ldrb.w r3, [r3, #132] ; 0x84 + 8004616: 2b01 cmp r3, #1 + 8004618: d101 bne.n 800461e + 800461a: 2302 movs r3, #2 + 800461c: e02d b.n 800467a + 800461e: 687b ldr r3, [r7, #4] + 8004620: 2201 movs r2, #1 + 8004622: f883 2084 strb.w r2, [r3, #132] ; 0x84 huart->gState = HAL_UART_STATE_BUSY; - 800481a: 687b ldr r3, [r7, #4] - 800481c: 2224 movs r2, #36 ; 0x24 - 800481e: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + 8004626: 687b ldr r3, [r7, #4] + 8004628: 2224 movs r2, #36 ; 0x24 + 800462a: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - 8004822: 687b ldr r3, [r7, #4] - 8004824: 681b ldr r3, [r3, #0] - 8004826: 681b ldr r3, [r3, #0] - 8004828: 60fb str r3, [r7, #12] + 800462e: 687b ldr r3, [r7, #4] + 8004630: 681b ldr r3, [r3, #0] + 8004632: 681b ldr r3, [r3, #0] + 8004634: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); - 800482a: 687b ldr r3, [r7, #4] - 800482c: 681b ldr r3, [r3, #0] - 800482e: 681a ldr r2, [r3, #0] - 8004830: 687b ldr r3, [r7, #4] - 8004832: 681b ldr r3, [r3, #0] - 8004834: f022 0201 bic.w r2, r2, #1 - 8004838: 601a str r2, [r3, #0] + 8004636: 687b ldr r3, [r7, #4] + 8004638: 681b ldr r3, [r3, #0] + 800463a: 681a ldr r2, [r3, #0] + 800463c: 687b ldr r3, [r7, #4] + 800463e: 681b ldr r3, [r3, #0] + 8004640: f022 0201 bic.w r2, r2, #1 + 8004644: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); - 800483a: 687b ldr r3, [r7, #4] - 800483c: 681b ldr r3, [r3, #0] - 800483e: 689b ldr r3, [r3, #8] - 8004840: f023 6160 bic.w r1, r3, #234881024 ; 0xe000000 - 8004844: 687b ldr r3, [r7, #4] - 8004846: 681b ldr r3, [r3, #0] - 8004848: 683a ldr r2, [r7, #0] - 800484a: 430a orrs r2, r1 - 800484c: 609a str r2, [r3, #8] + 8004646: 687b ldr r3, [r7, #4] + 8004648: 681b ldr r3, [r3, #0] + 800464a: 689b ldr r3, [r3, #8] + 800464c: f023 6160 bic.w r1, r3, #234881024 ; 0xe000000 + 8004650: 687b ldr r3, [r7, #4] + 8004652: 681b ldr r3, [r3, #0] + 8004654: 683a ldr r2, [r7, #0] + 8004656: 430a orrs r2, r1 + 8004658: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); - 800484e: 6878 ldr r0, [r7, #4] - 8004850: f000 f812 bl 8004878 + 800465a: 6878 ldr r0, [r7, #4] + 800465c: f000 f812 bl 8004684 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); - 8004854: 687b ldr r3, [r7, #4] - 8004856: 681b ldr r3, [r3, #0] - 8004858: 68fa ldr r2, [r7, #12] - 800485a: 601a str r2, [r3, #0] + 8004660: 687b ldr r3, [r7, #4] + 8004662: 681b ldr r3, [r3, #0] + 8004664: 68fa ldr r2, [r7, #12] + 8004666: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; - 800485c: 687b ldr r3, [r7, #4] - 800485e: 2220 movs r2, #32 - 8004860: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + 8004668: 687b ldr r3, [r7, #4] + 800466a: 2220 movs r2, #32 + 800466c: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); - 8004864: 687b ldr r3, [r7, #4] - 8004866: 2200 movs r2, #0 - 8004868: f883 2084 strb.w r2, [r3, #132] ; 0x84 + 8004670: 687b ldr r3, [r7, #4] + 8004672: 2200 movs r2, #0 + 8004674: f883 2084 strb.w r2, [r3, #132] ; 0x84 return HAL_OK; - 800486c: 2300 movs r3, #0 + 8004678: 2300 movs r3, #0 } - 800486e: 4618 mov r0, r3 - 8004870: 3710 adds r7, #16 - 8004872: 46bd mov sp, r7 - 8004874: bd80 pop {r7, pc} + 800467a: 4618 mov r0, r3 + 800467c: 3710 adds r7, #16 + 800467e: 46bd mov sp, r7 + 8004680: bd80 pop {r7, pc} ... -08004878 : +08004684 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { - 8004878: b480 push {r7} - 800487a: b085 sub sp, #20 - 800487c: af00 add r7, sp, #0 - 800487e: 6078 str r0, [r7, #4] + 8004684: b480 push {r7} + 8004686: b085 sub sp, #20 + 8004688: af00 add r7, sp, #0 + 800468a: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) - 8004880: 687b ldr r3, [r7, #4] - 8004882: 6e5b ldr r3, [r3, #100] ; 0x64 - 8004884: 2b00 cmp r3, #0 - 8004886: d108 bne.n 800489a + 800468c: 687b ldr r3, [r7, #4] + 800468e: 6e5b ldr r3, [r3, #100] ; 0x64 + 8004690: 2b00 cmp r3, #0 + 8004692: d108 bne.n 80046a6 { huart->NbTxDataToProcess = 1U; - 8004888: 687b ldr r3, [r7, #4] - 800488a: 2201 movs r2, #1 - 800488c: f8a3 206a strh.w r2, [r3, #106] ; 0x6a + 8004694: 687b ldr r3, [r7, #4] + 8004696: 2201 movs r2, #1 + 8004698: f8a3 206a strh.w r2, [r3, #106] ; 0x6a huart->NbRxDataToProcess = 1U; - 8004890: 687b ldr r3, [r7, #4] - 8004892: 2201 movs r2, #1 - 8004894: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 + 800469c: 687b ldr r3, [r7, #4] + 800469e: 2201 movs r2, #1 + 80046a0: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } - 8004898: e031 b.n 80048fe + 80046a4: e031 b.n 800470a rx_fifo_depth = RX_FIFO_DEPTH; - 800489a: 2308 movs r3, #8 - 800489c: 73fb strb r3, [r7, #15] + 80046a6: 2308 movs r3, #8 + 80046a8: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; - 800489e: 2308 movs r3, #8 - 80048a0: 73bb strb r3, [r7, #14] + 80046aa: 2308 movs r3, #8 + 80046ac: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); - 80048a2: 687b ldr r3, [r7, #4] - 80048a4: 681b ldr r3, [r3, #0] - 80048a6: 689b ldr r3, [r3, #8] - 80048a8: 0e5b lsrs r3, r3, #25 - 80048aa: b2db uxtb r3, r3 - 80048ac: f003 0307 and.w r3, r3, #7 - 80048b0: 737b strb r3, [r7, #13] + 80046ae: 687b ldr r3, [r7, #4] + 80046b0: 681b ldr r3, [r3, #0] + 80046b2: 689b ldr r3, [r3, #8] + 80046b4: 0e5b lsrs r3, r3, #25 + 80046b6: b2db uxtb r3, r3 + 80046b8: f003 0307 and.w r3, r3, #7 + 80046bc: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - 80048b2: 687b ldr r3, [r7, #4] - 80048b4: 681b ldr r3, [r3, #0] - 80048b6: 689b ldr r3, [r3, #8] - 80048b8: 0f5b lsrs r3, r3, #29 - 80048ba: b2db uxtb r3, r3 - 80048bc: f003 0307 and.w r3, r3, #7 - 80048c0: 733b strb r3, [r7, #12] + 80046be: 687b ldr r3, [r7, #4] + 80046c0: 681b ldr r3, [r3, #0] + 80046c2: 689b ldr r3, [r3, #8] + 80046c4: 0f5b lsrs r3, r3, #29 + 80046c6: b2db uxtb r3, r3 + 80046c8: f003 0307 and.w r3, r3, #7 + 80046cc: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / - 80048c2: 7bbb ldrb r3, [r7, #14] - 80048c4: 7b3a ldrb r2, [r7, #12] - 80048c6: 4910 ldr r1, [pc, #64] ; (8004908 ) - 80048c8: 5c8a ldrb r2, [r1, r2] - 80048ca: fb02 f303 mul.w r3, r2, r3 + 80046ce: 7bbb ldrb r3, [r7, #14] + 80046d0: 7b3a ldrb r2, [r7, #12] + 80046d2: 4910 ldr r1, [pc, #64] ; (8004714 ) + 80046d4: 5c8a ldrb r2, [r1, r2] + 80046d6: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; - 80048ce: 7b3a ldrb r2, [r7, #12] - 80048d0: 490e ldr r1, [pc, #56] ; (800490c ) - 80048d2: 5c8a ldrb r2, [r1, r2] + 80046da: 7b3a ldrb r2, [r7, #12] + 80046dc: 490e ldr r1, [pc, #56] ; (8004718 ) + 80046de: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / - 80048d4: fb93 f3f2 sdiv r3, r3, r2 - 80048d8: b29a uxth r2, r3 - 80048da: 687b ldr r3, [r7, #4] - 80048dc: f8a3 206a strh.w r2, [r3, #106] ; 0x6a + 80046e0: fb93 f3f2 sdiv r3, r3, r2 + 80046e4: b29a uxth r2, r3 + 80046e6: 687b ldr r3, [r7, #4] + 80046e8: f8a3 206a strh.w r2, [r3, #106] ; 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / - 80048e0: 7bfb ldrb r3, [r7, #15] - 80048e2: 7b7a ldrb r2, [r7, #13] - 80048e4: 4908 ldr r1, [pc, #32] ; (8004908 ) - 80048e6: 5c8a ldrb r2, [r1, r2] - 80048e8: fb02 f303 mul.w r3, r2, r3 + 80046ec: 7bfb ldrb r3, [r7, #15] + 80046ee: 7b7a ldrb r2, [r7, #13] + 80046f0: 4908 ldr r1, [pc, #32] ; (8004714 ) + 80046f2: 5c8a ldrb r2, [r1, r2] + 80046f4: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; - 80048ec: 7b7a ldrb r2, [r7, #13] - 80048ee: 4907 ldr r1, [pc, #28] ; (800490c ) - 80048f0: 5c8a ldrb r2, [r1, r2] + 80046f8: 7b7a ldrb r2, [r7, #13] + 80046fa: 4907 ldr r1, [pc, #28] ; (8004718 ) + 80046fc: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / - 80048f2: fb93 f3f2 sdiv r3, r3, r2 - 80048f6: b29a uxth r2, r3 - 80048f8: 687b ldr r3, [r7, #4] - 80048fa: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 -} - 80048fe: bf00 nop - 8004900: 3714 adds r7, #20 - 8004902: 46bd mov sp, r7 - 8004904: bc80 pop {r7} - 8004906: 4770 bx lr - 8004908: 08004acc .word 0x08004acc - 800490c: 08004ad4 .word 0x08004ad4 - -08004910 <__libc_init_array>: - 8004910: b570 push {r4, r5, r6, lr} - 8004912: 4d0d ldr r5, [pc, #52] ; (8004948 <__libc_init_array+0x38>) - 8004914: 4c0d ldr r4, [pc, #52] ; (800494c <__libc_init_array+0x3c>) - 8004916: 1b64 subs r4, r4, r5 - 8004918: 10a4 asrs r4, r4, #2 - 800491a: 2600 movs r6, #0 - 800491c: 42a6 cmp r6, r4 - 800491e: d109 bne.n 8004934 <__libc_init_array+0x24> - 8004920: 4d0b ldr r5, [pc, #44] ; (8004950 <__libc_init_array+0x40>) - 8004922: 4c0c ldr r4, [pc, #48] ; (8004954 <__libc_init_array+0x44>) - 8004924: f000 f820 bl 8004968 <_init> - 8004928: 1b64 subs r4, r4, r5 - 800492a: 10a4 asrs r4, r4, #2 - 800492c: 2600 movs r6, #0 - 800492e: 42a6 cmp r6, r4 - 8004930: d105 bne.n 800493e <__libc_init_array+0x2e> - 8004932: bd70 pop {r4, r5, r6, pc} - 8004934: f855 3b04 ldr.w r3, [r5], #4 - 8004938: 4798 blx r3 - 800493a: 3601 adds r6, #1 - 800493c: e7ee b.n 800491c <__libc_init_array+0xc> - 800493e: f855 3b04 ldr.w r3, [r5], #4 - 8004942: 4798 blx r3 - 8004944: 3601 adds r6, #1 - 8004946: e7f2 b.n 800492e <__libc_init_array+0x1e> - 8004948: 08004ae4 .word 0x08004ae4 - 800494c: 08004ae4 .word 0x08004ae4 - 8004950: 08004ae4 .word 0x08004ae4 - 8004954: 08004ae8 .word 0x08004ae8 - -08004958 : - 8004958: 4402 add r2, r0 - 800495a: 4603 mov r3, r0 - 800495c: 4293 cmp r3, r2 - 800495e: d100 bne.n 8004962 - 8004960: 4770 bx lr - 8004962: f803 1b01 strb.w r1, [r3], #1 - 8004966: e7f9 b.n 800495c - -08004968 <_init>: - 8004968: b5f8 push {r3, r4, r5, r6, r7, lr} - 800496a: bf00 nop - 800496c: bcf8 pop {r3, r4, r5, r6, r7} - 800496e: bc08 pop {r3} - 8004970: 469e mov lr, r3 - 8004972: 4770 bx lr - -08004974 <_fini>: - 8004974: b5f8 push {r3, r4, r5, r6, r7, lr} - 8004976: bf00 nop - 8004978: bcf8 pop {r3, r4, r5, r6, r7} - 800497a: bc08 pop {r3} - 800497c: 469e mov lr, r3 - 800497e: 4770 bx lr + 80046fe: fb93 f3f2 sdiv r3, r3, r2 + 8004702: b29a uxth r2, r3 + 8004704: 687b ldr r3, [r7, #4] + 8004706: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 +} + 800470a: bf00 nop + 800470c: 3714 adds r7, #20 + 800470e: 46bd mov sp, r7 + 8004710: bc80 pop {r7} + 8004712: 4770 bx lr + 8004714: 08004870 .word 0x08004870 + 8004718: 08004878 .word 0x08004878 + +0800471c <__libc_init_array>: + 800471c: b570 push {r4, r5, r6, lr} + 800471e: 4d0d ldr r5, [pc, #52] ; (8004754 <__libc_init_array+0x38>) + 8004720: 4c0d ldr r4, [pc, #52] ; (8004758 <__libc_init_array+0x3c>) + 8004722: 1b64 subs r4, r4, r5 + 8004724: 10a4 asrs r4, r4, #2 + 8004726: 2600 movs r6, #0 + 8004728: 42a6 cmp r6, r4 + 800472a: d109 bne.n 8004740 <__libc_init_array+0x24> + 800472c: 4d0b ldr r5, [pc, #44] ; (800475c <__libc_init_array+0x40>) + 800472e: 4c0c ldr r4, [pc, #48] ; (8004760 <__libc_init_array+0x44>) + 8004730: f000 f820 bl 8004774 <_init> + 8004734: 1b64 subs r4, r4, r5 + 8004736: 10a4 asrs r4, r4, #2 + 8004738: 2600 movs r6, #0 + 800473a: 42a6 cmp r6, r4 + 800473c: d105 bne.n 800474a <__libc_init_array+0x2e> + 800473e: bd70 pop {r4, r5, r6, pc} + 8004740: f855 3b04 ldr.w r3, [r5], #4 + 8004744: 4798 blx r3 + 8004746: 3601 adds r6, #1 + 8004748: e7ee b.n 8004728 <__libc_init_array+0xc> + 800474a: f855 3b04 ldr.w r3, [r5], #4 + 800474e: 4798 blx r3 + 8004750: 3601 adds r6, #1 + 8004752: e7f2 b.n 800473a <__libc_init_array+0x1e> + 8004754: 08004888 .word 0x08004888 + 8004758: 08004888 .word 0x08004888 + 800475c: 08004888 .word 0x08004888 + 8004760: 0800488c .word 0x0800488c + +08004764 : + 8004764: 4402 add r2, r0 + 8004766: 4603 mov r3, r0 + 8004768: 4293 cmp r3, r2 + 800476a: d100 bne.n 800476e + 800476c: 4770 bx lr + 800476e: f803 1b01 strb.w r1, [r3], #1 + 8004772: e7f9 b.n 8004768 + +08004774 <_init>: + 8004774: b5f8 push {r3, r4, r5, r6, r7, lr} + 8004776: bf00 nop + 8004778: bcf8 pop {r3, r4, r5, r6, r7} + 800477a: bc08 pop {r3} + 800477c: 469e mov lr, r3 + 800477e: 4770 bx lr + +08004780 <_fini>: + 8004780: b5f8 push {r3, r4, r5, r6, r7, lr} + 8004782: bf00 nop + 8004784: bcf8 pop {r3, r4, r5, r6, r7} + 8004786: bc08 pop {r3} + 8004788: 469e mov lr, r3 + 800478a: 4770 bx lr diff --git a/Firmware/Debug/rocketbeacon.map b/Firmware/Debug/rocketbeacon.map index e8899f3..46bf58d 100644 --- a/Firmware/Debug/rocketbeacon.map +++ b/Firmware/Debug/rocketbeacon.map @@ -102,14 +102,32 @@ Discarded input sections .bss 0x0000000000000000 0x0 ./Core/Src/main.o .rodata.CHANNEL_OFFSET_TAB 0x0000000000000000 0x7 ./Core/Src/main.o + .rodata.LPD433 + 0x0000000000000000 0x228 ./Core/Src/main.o + .rodata.PMR446 + 0x0000000000000000 0x80 ./Core/Src/main.o + .rodata.FRS 0x0000000000000000 0xb0 ./Core/Src/main.o + .rodata.morse_chars + 0x0000000000000000 0x5b ./Core/Src/main.o + .data.morse_unit_ms + 0x0000000000000000 0x4 ./Core/Src/main.o + .data.morse_power + 0x0000000000000000 0x1 ./Core/Src/main.o + .text.play_morse_char + 0x0000000000000000 0x134 ./Core/Src/main.o + .text.play_morse_word + 0x0000000000000000 0x6c ./Core/Src/main.o .text.SetPaLowPower 0x0000000000000000 0x34 ./Core/Src/main.o + .text.SetContinuousWave + 0x0000000000000000 0x24 ./Core/Src/main.o .text.SetTx 0x0000000000000000 0x40 ./Core/Src/main.o .text.SetRx 0x0000000000000000 0x40 ./Core/Src/main.o .text.SetModulationParamsLora 0x0000000000000000 0x40 ./Core/Src/main.o .text.SetPacketParamsLora 0x0000000000000000 0x60 ./Core/Src/main.o + .text.CWBeep 0x0000000000000000 0x3e ./Core/Src/main.o .group 0x0000000000000000 0xc ./Core/Src/stm32wlxx_hal_msp.o .group 0x0000000000000000 0xc ./Core/Src/stm32wlxx_hal_msp.o .group 0x0000000000000000 0xc ./Core/Src/stm32wlxx_hal_msp.o @@ -3866,7 +3884,7 @@ LOAD c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.ext 0x0000000008000000 g_pfnVectors 0x0000000008000138 . = ALIGN (0x4) -.text 0x0000000008000138 0x4848 +.text 0x0000000008000138 0x4654 0x0000000008000138 . = ALIGN (0x4) *(.text) .text 0x0000000008000138 0x40 c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m/nofp/crtbegin.o @@ -3906,630 +3924,609 @@ LOAD c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.ext 0x0000000008000c58 0x1c ./Core/Src/main.o .text.LL_AHB2_GRP1_EnableClock 0x0000000008000c74 0x30 ./Core/Src/main.o + .text.LED_on 0x0000000008000ca4 0x16 ./Core/Src/main.o + 0x0000000008000ca4 LED_on + .text.LED_off 0x0000000008000cba 0x16 ./Core/Src/main.o + 0x0000000008000cba LED_off + .text.main 0x0000000008000cd0 0xf8 ./Core/Src/main.o + 0x0000000008000cd0 main + .text.SystemClock_Config + 0x0000000008000dc8 0xa8 ./Core/Src/main.o + 0x0000000008000dc8 SystemClock_Config + .text.MX_ADC_Init + 0x0000000008000e70 0x9c ./Core/Src/main.o + .text.MX_CRC_Init + 0x0000000008000f0c 0x44 ./Core/Src/main.o + .text.MX_SUBGHZ_Init + 0x0000000008000f50 0x24 ./Core/Src/main.o + .text.MX_USART2_UART_Init + 0x0000000008000f74 0x98 ./Core/Src/main.o + .text.MX_GPIO_Init + 0x000000000800100c 0x90 ./Core/Src/main.o .text.SetStandbyXOSC - 0x0000000008000ca4 0x28 ./Core/Src/main.o - 0x0000000008000ca4 SetStandbyXOSC + 0x000000000800109c 0x28 ./Core/Src/main.o + 0x000000000800109c SetStandbyXOSC .text.SetPacketTypeLora - 0x0000000008000ccc 0x28 ./Core/Src/main.o - 0x0000000008000ccc SetPacketTypeLora + 0x00000000080010c4 0x28 ./Core/Src/main.o + 0x00000000080010c4 SetPacketTypeLora .text.SetPacketTypeFSK - 0x0000000008000cf4 0x24 ./Core/Src/main.o - 0x0000000008000cf4 SetPacketTypeFSK + 0x00000000080010ec 0x24 ./Core/Src/main.o + 0x00000000080010ec SetPacketTypeFSK .text.ComputeRfFreq - 0x0000000008000d18 0x34 ./Core/Src/main.o - 0x0000000008000d18 ComputeRfFreq + 0x0000000008001110 0x34 ./Core/Src/main.o + 0x0000000008001110 ComputeRfFreq .text.SetRfFreq - 0x0000000008000d4c 0x48 ./Core/Src/main.o - 0x0000000008000d4c SetRfFreq + 0x0000000008001144 0x48 ./Core/Src/main.o + 0x0000000008001144 SetRfFreq .text.SetPa22dB - 0x0000000008000d94 0x34 ./Core/Src/main.o - 0x0000000008000d94 SetPa22dB + 0x000000000800118c 0x34 ./Core/Src/main.o + 0x000000000800118c SetPa22dB .text.SetTxPower - 0x0000000008000dc8 0x34 ./Core/Src/main.o - 0x0000000008000dc8 SetTxPower - .text.SetContinuousWave - 0x0000000008000dfc 0x24 ./Core/Src/main.o - 0x0000000008000dfc SetContinuousWave + 0x00000000080011c0 0x34 ./Core/Src/main.o + 0x00000000080011c0 SetTxPower .text.SetTxInfinitePreamble - 0x0000000008000e20 0x24 ./Core/Src/main.o - 0x0000000008000e20 SetTxInfinitePreamble - *fill* 0x0000000008000e44 0x4 + 0x00000000080011f4 0x24 ./Core/Src/main.o + 0x00000000080011f4 SetTxInfinitePreamble .text.SetModulationParamsFSK - 0x0000000008000e48 0xbc ./Core/Src/main.o - 0x0000000008000e48 SetModulationParamsFSK - .text.FSKBeep 0x0000000008000f04 0x50 ./Core/Src/main.o - 0x0000000008000f04 FSKBeep - .text.CWBeep 0x0000000008000f54 0x3e ./Core/Src/main.o - 0x0000000008000f54 CWBeep - *fill* 0x0000000008000f92 0x2 - .text.play_morse_char - 0x0000000008000f94 0x134 ./Core/Src/main.o - 0x0000000008000f94 play_morse_char - .text.play_morse_word - 0x00000000080010c8 0x6c ./Core/Src/main.o - 0x00000000080010c8 play_morse_word - *fill* 0x0000000008001134 0x4 - .text.main 0x0000000008001138 0x10c ./Core/Src/main.o - 0x0000000008001138 main - .text.SystemClock_Config - 0x0000000008001244 0xa8 ./Core/Src/main.o - 0x0000000008001244 SystemClock_Config - .text.MX_ADC_Init - 0x00000000080012ec 0x9c ./Core/Src/main.o - .text.MX_CRC_Init - 0x0000000008001388 0x44 ./Core/Src/main.o - .text.MX_SUBGHZ_Init - 0x00000000080013cc 0x24 ./Core/Src/main.o - .text.MX_USART2_UART_Init - 0x00000000080013f0 0x98 ./Core/Src/main.o - .text.MX_GPIO_Init - 0x0000000008001488 0x90 ./Core/Src/main.o + 0x0000000008001218 0xbc ./Core/Src/main.o + 0x0000000008001218 SetModulationParamsFSK + .text.FSKBeep 0x00000000080012d4 0x50 ./Core/Src/main.o + 0x00000000080012d4 FSKBeep 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c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m/nofp/crtbegin.o + .fini_array 0x000000000800488c 0x4 c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m/nofp/crtbegin.o [!provide] PROVIDE (__fini_array_end = .) - 0x0000000008004aec . = ALIGN (0x4) - 0x0000000008004aec _sidata = LOADADDR (.data) + 0x0000000008004890 . = ALIGN (0x4) + 0x0000000008004890 _sidata = LOADADDR (.data) -.data 0x0000000020000000 0x14 load address 0x0000000008004aec +.data 0x0000000020000000 0xc load address 0x0000000008004890 0x0000000020000000 . = ALIGN (0x4) 0x0000000020000000 _sdata = . *(.data) *(.data*) - .data.morse_unit_ms - 0x0000000020000000 0x4 ./Core/Src/main.o - 0x0000000020000000 morse_unit_ms - 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0x000000002000000c _edata = . -.igot.plt 0x0000000020000014 0x0 load address 0x0000000008004b00 - .igot.plt 0x0000000020000014 0x0 c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m/nofp/crtbegin.o - 0x0000000020000014 . = ALIGN (0x4) +.igot.plt 0x000000002000000c 0x0 load address 0x000000000800489c + .igot.plt 0x000000002000000c 0x0 c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m/nofp/crtbegin.o + 0x000000002000000c . = ALIGN (0x4) -.bss 0x0000000020000014 0x148 load address 0x0000000008004b00 - 0x0000000020000014 _sbss = . - 0x0000000020000014 __bss_start__ = _sbss +.bss 0x000000002000000c 0x148 load address 0x000000000800489c + 0x000000002000000c _sbss = . + 0x000000002000000c __bss_start__ = _sbss *(.bss) - .bss 0x0000000020000014 0x1c c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m/nofp/crtbegin.o + .bss 0x000000002000000c 0x1c c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m/nofp/crtbegin.o *(.bss*) - .bss.hadc 0x0000000020000030 0x64 ./Core/Src/main.o - 0x0000000020000030 hadc - .bss.hcrc 0x0000000020000094 0x24 ./Core/Src/main.o - 0x0000000020000094 hcrc - .bss.hsubghz 0x00000000200000b8 0xc ./Core/Src/main.o - 0x00000000200000b8 hsubghz - .bss.huart2 0x00000000200000c4 0x94 ./Core/Src/main.o - 0x00000000200000c4 huart2 - .bss.uwTick 0x0000000020000158 0x4 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o - 0x0000000020000158 uwTick + .bss.hadc 0x0000000020000028 0x64 ./Core/Src/main.o + 0x0000000020000028 hadc + .bss.hcrc 0x000000002000008c 0x24 ./Core/Src/main.o + 0x000000002000008c hcrc + .bss.hsubghz 0x00000000200000b0 0xc ./Core/Src/main.o + 0x00000000200000b0 hsubghz + .bss.huart2 0x00000000200000bc 0x94 ./Core/Src/main.o + 0x00000000200000bc huart2 + .bss.uwTick 0x0000000020000150 0x4 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + 0x0000000020000150 uwTick *(COMMON) - 0x000000002000015c . = ALIGN (0x4) - 0x000000002000015c _ebss = . - 0x000000002000015c __bss_end__ = _ebss + 0x0000000020000154 . = ALIGN (0x4) + 0x0000000020000154 _ebss = . + 0x0000000020000154 __bss_end__ = _ebss ._user_heap_stack - 0x000000002000015c 0x604 load address 0x0000000008004b00 - 0x0000000020000160 . = ALIGN (0x8) - *fill* 0x000000002000015c 0x4 + 0x0000000020000154 0x604 load address 0x000000000800489c + 0x0000000020000158 . = ALIGN (0x8) + *fill* 0x0000000020000154 0x4 [!provide] PROVIDE (end = .) - 0x0000000020000160 PROVIDE (_end = .) - 0x0000000020000360 . = (. + _Min_Heap_Size) - *fill* 0x0000000020000160 0x200 - 0x0000000020000760 . = (. + _Min_Stack_Size) - *fill* 0x0000000020000360 0x400 - 0x0000000020000760 . = ALIGN (0x8) + 0x0000000020000158 PROVIDE (_end = .) + 0x0000000020000358 . = (. + _Min_Heap_Size) + *fill* 0x0000000020000158 0x200 + 0x0000000020000758 . = (. + _Min_Stack_Size) + *fill* 0x0000000020000358 0x400 + 0x0000000020000758 . = ALIGN (0x8) /DISCARD/ libc.a(*) @@ -4603,103 +4600,103 @@ LOAD c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.ext LOAD c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp\libm.a LOAD c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m/nofp\libgcc.a -.debug_info 0x0000000000000000 0x12268 - .debug_info 0x0000000000000000 0x1d83 ./Core/Src/main.o - .debug_info 0x0000000000001d83 0x1523 ./Core/Src/stm32wlxx_hal_msp.o - .debug_info 0x00000000000032a6 0x166 ./Core/Src/stm32wlxx_it.o - .debug_info 0x000000000000340c 0x452 ./Core/Src/system_stm32wlxx.o - .debug_info 0x000000000000385e 0x22 ./Core/Startup/startup_stm32wle5cbux.o - .debug_info 0x0000000000003880 0xf14 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o - .debug_info 0x0000000000004794 0x176c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.o - .debug_info 0x0000000000005f00 0xdb1 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o - .debug_info 0x0000000000006cb1 0x57f ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc.o - .debug_info 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./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o - .debug_ranges 0x0000000000000870 0x1c0 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o - .debug_ranges 0x0000000000000a30 0x200 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o - .debug_ranges 0x0000000000000c30 0x1d8 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o - .debug_ranges 0x0000000000000e08 0x158 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o - .debug_ranges 0x0000000000000f60 0x278 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o - .debug_ranges 0x00000000000011d8 0x98 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o +.debug_ranges 0x0000000000000000 0x1280 + .debug_ranges 0x0000000000000000 0x100 ./Core/Src/main.o + .debug_ranges 0x0000000000000100 0x98 ./Core/Src/stm32wlxx_hal_msp.o + .debug_ranges 0x0000000000000198 0x50 ./Core/Src/stm32wlxx_it.o + .debug_ranges 0x00000000000001e8 0x18 ./Core/Src/system_stm32wlxx.o + .debug_ranges 0x0000000000000200 0x20 ./Core/Startup/startup_stm32wle5cbux.o + .debug_ranges 0x0000000000000220 0x200 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + .debug_ranges 0x0000000000000420 0x1e0 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.o + .debug_ranges 0x0000000000000600 0x108 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .debug_ranges 0x0000000000000708 0x50 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc.o + .debug_ranges 0x0000000000000758 0x20 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc_ex.o + .debug_ranges 0x0000000000000778 0x50 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o + .debug_ranges 0x00000000000007c8 0xb8 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o + .debug_ranges 0x0000000000000880 0x1c0 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o + .debug_ranges 0x0000000000000a40 0x200 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o + .debug_ranges 0x0000000000000c40 0x1d8 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o + .debug_ranges 0x0000000000000e18 0x158 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + .debug_ranges 0x0000000000000f70 0x278 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .debug_ranges 0x00000000000011e8 0x98 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o .debug_macro 0x0000000000000000 0x1ab62 .debug_macro 0x0000000000000000 0x2ae ./Core/Src/main.o @@ -4778,62 +4775,62 @@ LOAD c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.ext .debug_macro 0x000000000001a681 0x280 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o .debug_macro 0x000000000001a901 0x261 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o -.debug_line 0x0000000000000000 0x11d8a - .debug_line 0x0000000000000000 0xe2b ./Core/Src/main.o - .debug_line 0x0000000000000e2b 0xa73 ./Core/Src/stm32wlxx_hal_msp.o - .debug_line 0x000000000000189e 0x924 ./Core/Src/stm32wlxx_it.o - .debug_line 0x00000000000021c2 0x869 ./Core/Src/system_stm32wlxx.o - .debug_line 0x0000000000002a2b 0x89 ./Core/Startup/startup_stm32wle5cbux.o - .debug_line 0x0000000000002ab4 0xece ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o - .debug_line 0x0000000000003982 0x1787 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.o - .debug_line 0x0000000000005109 0xd69 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o - .debug_line 0x0000000000005e72 0xb16 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc.o - .debug_line 0x0000000000006988 0x892 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc_ex.o - .debug_line 0x000000000000721a 0xbde ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o - .debug_line 0x0000000000007df8 0xa68 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o - .debug_line 0x0000000000008860 0xea8 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o - .debug_line 0x0000000000009708 0x16ea ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o - .debug_line 0x000000000000adf2 0x13da ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o - .debug_line 0x000000000000c1cc 0x10d4 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o - .debug_line 0x000000000000d2a0 0x3cc3 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o - .debug_line 0x0000000000010f63 0xe27 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o +.debug_line 0x0000000000000000 0x11daa + .debug_line 0x0000000000000000 0xe4b ./Core/Src/main.o + .debug_line 0x0000000000000e4b 0xa73 ./Core/Src/stm32wlxx_hal_msp.o + .debug_line 0x00000000000018be 0x924 ./Core/Src/stm32wlxx_it.o + .debug_line 0x00000000000021e2 0x869 ./Core/Src/system_stm32wlxx.o + .debug_line 0x0000000000002a4b 0x89 ./Core/Startup/startup_stm32wle5cbux.o + .debug_line 0x0000000000002ad4 0xece ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + .debug_line 0x00000000000039a2 0x1787 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.o + .debug_line 0x0000000000005129 0xd69 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .debug_line 0x0000000000005e92 0xb16 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc.o + .debug_line 0x00000000000069a8 0x892 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc_ex.o + .debug_line 0x000000000000723a 0xbde ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o + .debug_line 0x0000000000007e18 0xa68 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o + .debug_line 0x0000000000008880 0xea8 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o + .debug_line 0x0000000000009728 0x16ea ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o + .debug_line 0x000000000000ae12 0x13da ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o + .debug_line 0x000000000000c1ec 0x10d4 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + .debug_line 0x000000000000d2c0 0x3cc3 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .debug_line 0x0000000000010f83 0xe27 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o -.debug_str 0x0000000000000000 0xa7721 - .debug_str 0x0000000000000000 0xa2a8e ./Core/Src/main.o - 0xa32de (size before relaxing) - .debug_str 0x00000000000a2a8e 0x2fb ./Core/Src/stm32wlxx_hal_msp.o +.debug_str 0x0000000000000000 0xa7745 + .debug_str 0x0000000000000000 0xa2ab2 ./Core/Src/main.o + 0xa3302 (size before relaxing) + .debug_str 0x00000000000a2ab2 0x2fb ./Core/Src/stm32wlxx_hal_msp.o 0xa2d73 (size before relaxing) - .debug_str 0x00000000000a2d89 0xc9 ./Core/Src/stm32wlxx_it.o + .debug_str 0x00000000000a2dad 0xc9 ./Core/Src/stm32wlxx_it.o 0xa1f6c (size before relaxing) - .debug_str 0x00000000000a2e52 0x9e ./Core/Src/system_stm32wlxx.o + .debug_str 0x00000000000a2e76 0x9e ./Core/Src/system_stm32wlxx.o 0xa1405 (size before relaxing) - .debug_str 0x00000000000a2ef0 0x36 ./Core/Startup/startup_stm32wle5cbux.o + .debug_str 0x00000000000a2f14 0x36 ./Core/Startup/startup_stm32wle5cbux.o 0x64 (size before relaxing) - .debug_str 0x00000000000a2f26 0xbd5 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + .debug_str 0x00000000000a2f4a 0xbd5 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o 0xa20b7 (size before relaxing) - .debug_str 0x00000000000a3afb 0x921 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.o + .debug_str 0x00000000000a3b1f 0x921 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.o 0xa2151 (size before relaxing) - .debug_str 0x00000000000a441c 0x393 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .debug_str 0x00000000000a4440 0x393 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o 0xa1b75 (size before relaxing) - .debug_str 0x00000000000a47af 0xc6 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc.o + .debug_str 0x00000000000a47d3 0xc6 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc.o 0xa14f7 (size before relaxing) - .debug_str 0x00000000000a4875 0x69 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc_ex.o + .debug_str 0x00000000000a4899 0x69 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc_ex.o 0xa149d (size before relaxing) - .debug_str 0x00000000000a48de 0x152 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o + .debug_str 0x00000000000a4902 0x152 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o 0xa14eb (size before relaxing) - .debug_str 0x00000000000a4a30 0x4ca ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o + .debug_str 0x00000000000a4a54 0x4ca ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o 0xa185c (size before relaxing) - .debug_str 0x00000000000a4efa 0x625 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o + .debug_str 0x00000000000a4f1e 0x625 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o 0xa1ba9 (size before relaxing) - .debug_str 0x00000000000a551f 0xa2d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o + .debug_str 0x00000000000a5543 0xa2d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o 0xa2120 (size before relaxing) - .debug_str 0x00000000000a5f4c 0x564 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o + .debug_str 0x00000000000a5f70 0x564 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o 0xa1cf4 (size before relaxing) - .debug_str 0x00000000000a64b0 0x614 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + .debug_str 0x00000000000a64d4 0x614 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o 0xa1ed2 (size before relaxing) - .debug_str 0x00000000000a6ac4 0x9f2 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .debug_str 0x00000000000a6ae8 0x9f2 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o 0xa2443 (size before relaxing) - .debug_str 0x00000000000a74b6 0x26b ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + .debug_str 0x00000000000a74da 0x26b ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o 0xa1bf9 (size before relaxing) .comment 0x0000000000000000 0x50 @@ -4856,28 +4853,28 @@ LOAD c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.ext .comment 0x0000000000000050 0x51 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o .comment 0x0000000000000050 0x51 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o -.debug_frame 0x0000000000000000 0x5250 - .debug_frame 0x0000000000000000 0x3f8 ./Core/Src/main.o - .debug_frame 0x00000000000003f8 0x2b8 ./Core/Src/stm32wlxx_hal_msp.o - .debug_frame 0x00000000000006b0 0x104 ./Core/Src/stm32wlxx_it.o - .debug_frame 0x00000000000007b4 0x58 ./Core/Src/system_stm32wlxx.o - .debug_frame 0x000000000000080c 0x860 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o - .debug_frame 0x000000000000106c 0x90c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.o - .debug_frame 0x0000000000001978 0x498 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o - .debug_frame 0x0000000000001e10 0x168 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc.o - .debug_frame 0x0000000000001f78 0x88 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc_ex.o - .debug_frame 0x0000000000002000 0x174 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o - .debug_frame 0x0000000000002174 0x31c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o - .debug_frame 0x0000000000002490 0x7cc ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o - .debug_frame 0x0000000000002c5c 0x874 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o - .debug_frame 0x00000000000034d0 0x7ec ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o - .debug_frame 0x0000000000003cbc 0x624 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o - .debug_frame 0x00000000000042e0 0xae4 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o - .debug_frame 0x0000000000004dc4 0x2c0 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o - .debug_frame 0x0000000000005084 0x2c c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp\libc_nano.a(lib_a-init.o) - .debug_frame 0x00000000000050b0 0x20 c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp\libc_nano.a(lib_a-memset.o) - .debug_frame 0x00000000000050d0 0xac c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m/nofp\libgcc.a(_arm_addsubdf3.o) - .debug_frame 0x000000000000517c 0x50 c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m/nofp\libgcc.a(_arm_muldivdf3.o) - .debug_frame 0x00000000000051cc 0x24 c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m/nofp\libgcc.a(_arm_fixunsdfsi.o) - .debug_frame 0x00000000000051f0 0x2c c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m/nofp\libgcc.a(_aeabi_uldivmod.o) - .debug_frame 0x000000000000521c 0x34 c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m/nofp\libgcc.a(_udivmoddi4.o) +.debug_frame 0x0000000000000000 0x5288 + .debug_frame 0x0000000000000000 0x430 ./Core/Src/main.o + .debug_frame 0x0000000000000430 0x2b8 ./Core/Src/stm32wlxx_hal_msp.o + .debug_frame 0x00000000000006e8 0x104 ./Core/Src/stm32wlxx_it.o + .debug_frame 0x00000000000007ec 0x58 ./Core/Src/system_stm32wlxx.o + .debug_frame 0x0000000000000844 0x860 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o + .debug_frame 0x00000000000010a4 0x90c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.o + .debug_frame 0x00000000000019b0 0x498 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o + .debug_frame 0x0000000000001e48 0x168 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc.o + .debug_frame 0x0000000000001fb0 0x88 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc_ex.o + .debug_frame 0x0000000000002038 0x174 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o + .debug_frame 0x00000000000021ac 0x31c ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o + .debug_frame 0x00000000000024c8 0x7cc ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o + .debug_frame 0x0000000000002c94 0x874 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o + .debug_frame 0x0000000000003508 0x7ec ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o + .debug_frame 0x0000000000003cf4 0x624 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o + .debug_frame 0x0000000000004318 0xae4 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o + .debug_frame 0x0000000000004dfc 0x2c0 ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o + .debug_frame 0x00000000000050bc 0x2c c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp\libc_nano.a(lib_a-init.o) + .debug_frame 0x00000000000050e8 0x20 c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp\libc_nano.a(lib_a-memset.o) + .debug_frame 0x0000000000005108 0xac c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m/nofp\libgcc.a(_arm_addsubdf3.o) + .debug_frame 0x00000000000051b4 0x50 c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m/nofp\libgcc.a(_arm_muldivdf3.o) + .debug_frame 0x0000000000005204 0x24 c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m/nofp\libgcc.a(_arm_fixunsdfsi.o) + .debug_frame 0x0000000000005228 0x2c c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m/nofp\libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x0000000000005254 0x34 c:/st/stm32cubeide_1.11.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.win32_1.0.100.202210260954/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m/nofp\libgcc.a(_udivmoddi4.o)