Adds a test project for the verilator cmake bindings (#4)

Author: cchaine

.github/workflows/tests.yml

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+name: Tests
+
+on:
+  push:
+    branches: [ "main", "release/**" ]
+  pull_request:
+    branches: [ "main", "release/**" ]
+
+jobs:
+  tests:
+    runs-on: self-hosted
+
+    steps:
+    - uses: actions/checkout@v4.1.1
+
+    - name: Configure CMake
+      run: cmake -S ${{github.workspace}}/tests -B ${{github.workspace}}/build -GNinja
+
+    - name: Run tests
+      run: ninja -C ${{github.workspace}}/build tests

.gitignore

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+build

tests/CMakeLists.txt

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+cmake_minimum_required(VERSION 3.12)
+
+project(verilator-cmake-test VERSION 1.0)
+
+include(${CMAKE_CURRENT_LIST_DIR}/../cmake/verilator-config.cmake)
+
+add_executable(tests src/top.cpp)
+verilate(tests
+  PREFIX Vtop
+  SOURCES src/top.sv
+  TRACE
+  PUBLIC)

tests/src/top.cpp

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+/*           __        _
+ *  ________/ /  ___ _(_)__  ___
+ * / __/ __/ _ \/ _ `/ / _ \/ -_)
+ * \__/\__/_//_/\_,_/_/_//_/\__/
+ * 
+ * Copyright (C) Clément Chaine
+ * This file is part of verilator-cmake <https://github.com/ecap5/verilator-cmake>
+ *
+ * verilator-cmake is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * verilator-cmake is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with verilator-cmake.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <time.h>
+#include <verilated.h>
+#include <verilated_vcd_c.h>
+#include <svdpi.h>
+
+#include "Vtop.h"
+
+int main(int argc, char ** argv, char ** env) {
+  srand(time(NULL));
+  Verilated::traceEverOn(true);
+
+  /************************************************************/
+
+  /************************************************************/
+
+  exit(EXIT_SUCCESS);
+}

tests/src/top.sv

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+module top (
+  input   logic        clk_i,     
+  output  logic        clk_o
+);
+
+assign clk_o = clk_i;
+
+endmodule