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Merge pull request riscv-software-src#534 from lz-bro/fix_triggerDmode
Check the mcontrol triggers, no other triggers.
2 parents fd01e46 + f83ba40 commit 6b1d737

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debug/gdbserver.py

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Original file line numberDiff line numberDiff line change
@@ -1416,7 +1416,7 @@ def check_triggers(self, tdata1_lsbs, tdata2):
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i = 0
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for i in range(16):
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tdata1 = self.gdb.p(f"(({xlen_type} *)&data)[{2*i}]")
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if tdata1 == 0:
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if (tdata1 == 0) or (tdata1 >> (self.hart.xlen-4) == 15):
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break
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tdata2 = self.gdb.p(f"(({xlen_type} *)&data)[{2*i+1}]")
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