From 503a12dfc555d41794ef11d2422195489089bd06 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= Date: Thu, 9 May 2024 08:27:01 +0000 Subject: [PATCH 1/3] Updates functional requirements --- docs/src/spec/2_overall-description.rst | 7 +++++-- docs/src/spec/3_requirements.rst | 25 ++++++++++--------------- 2 files changed, 15 insertions(+), 17 deletions(-) diff --git a/docs/src/spec/2_overall-description.rst b/docs/src/spec/2_overall-description.rst index dca2e00..f6199f7 100644 --- a/docs/src/spec/2_overall-description.rst +++ b/docs/src/spec/2_overall-description.rst @@ -19,6 +19,10 @@ Serial Interface The peripheral shall perform parallel-to-serial conversion of the received data. +.. requirement:: U_UART_03 + + The peripheral shall support full-duplex communications. + Configuration ^^^^^^^^^^^^^ @@ -45,13 +49,12 @@ Memory-Mapped Interface .. requirement:: U_REGISTERS_01 - The peripheral shall provide memory-mapped registers described in the table below. + The peripheral shall provide the memory-mapped registers described in the table below. .. requirement:: U_MEMORY_INTERFACE_01 The peripheral memory-mapped registers shall be accessible through a wishbone interface. - .. _Memory_Mapping_and_Registers: .. list-table:: Memory Mapping and Registers :header-rows: 1 :widths: 1 94 1 1 1 1 diff --git a/docs/src/spec/3_requirements.rst b/docs/src/spec/3_requirements.rst index 07e4d18..96afe20 100644 --- a/docs/src/spec/3_requirements.rst +++ b/docs/src/spec/3_requirements.rst @@ -105,11 +105,6 @@ Functional Requirements The uart_tx_o signal shall be asserted while rst_i is asserted. -.. requirement:: F_ENABLE_01 - - The uart_tx_o signal shall be asserted while the EN field of UART_CR is deasserted. - - Memory interface ^^^^^^^^^^^^^^^^ @@ -117,13 +112,13 @@ Memory interface The UART_RXDR register shall be reset after being read and the RXNE field of UART_SR shall be deasserted. -.. requirement:: F_ENABLE_02 - - Any read to the registers shall return 0 while the EN field of UART_CR is deasserted. +.. requirement:: F_READ_02 + + The following fields of UART_SR shall be reset after being read : PE, FE and RXOE. .. requirement:: F_RESET_03 - Any change to UART_SR shall reset the peripheral. + Any change to UART_SR shall cancel both ongoing tranmissions and receptions. .. todo:: Add wishbone requirements @@ -137,11 +132,11 @@ Receive .. requirement:: F_RECEIVE_01 - The peripheral shall sample the uart_rx_i signal with an sample interval defined in number of clk_i edges by the field CLK_DIV field of UART_CR. + The peripheral shall sample the uart_rx_i signal with a sample interval defined in number of clk_i edges by the field CLK_DIV field of UART_CR. .. requirement:: F_RECEIVE_02 - The peripheral shall set the value of the RXD field of UART_RXDR when it latches the stop bit. + The peripheral shall set the value of the RXD field of UART_RXDR after latching the stop bit. .. requirement:: F_RECEIVE_03 @@ -149,22 +144,22 @@ Receive .. requirement:: F_RECEIVE_ERROR_01 - The peripheral shall assert the PE field of UART_SR when the 1-bit sum of the received bits is not equal to the received parity bit. + The peripheral shall assert the PE field of UART_SR when the result of the xor of all the received bits is not equal to the received parity bit. .. requirement:: F_RECEIVE_ERROR_02 - The peripheral shall assert the FE field of UART_SR when received stop bit is deasserted. + The peripheral shall assert the FE field of UART_SR when the received stop bit is zero instead of one. .. requirement:: F_RECEIVE_ERROR_03 - The peripheral shall assert the RXOE field of UART_SR when it latches the stop bit while the RXNE field of UART_SR is asserted. + The peripheral shall assert the RXOE field of UART_SR after latching the stop bit while the RXNE field of UART_SR is asserted. Transmit ^^^^^^^^ .. requirement:: F_TRANSMIT_01 - The peripheral shall transmit the TXD field of UART_TXDR after a write to UART_TXDR when the TXE field of UART_SR is deasserted, with a sample interval defined in number of clk_i edges by the field CLK_DIV field of UART_CR + The peripheral shall transmit the TXD field of UART_TXDR after a write to UART_TXDR when the TXE field of UART_SR is deasserted, with a sample interval defined in number of clk_i edges by the field CLK_DIV field of UART_CR. .. requirement:: F_TRANSMIT_02 From 4cb93d8df5b40b768ea32b10fe6ab0294b53554b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= Date: Thu, 9 May 2024 09:20:12 +0000 Subject: [PATCH 2/3] Adds more functional requirements --- docs/CMakeLists.txt | 2 + docs/src/assets/favicon.ico | Bin 0 -> 15282 bytes docs/src/assets/uart.drawio | 187 ++++++++++++++++++++++++ docs/src/assets/uart.svg | 3 + docs/src/conf.py | 1 + docs/src/spec/2_overall-description.rst | 67 ++------- docs/src/spec/3_requirements.rst | 81 +++++++++- docs/src/spec/content/uart_sr.rst | 4 +- 8 files changed, 290 insertions(+), 55 deletions(-) create mode 100644 docs/src/assets/favicon.ico create mode 100644 docs/src/assets/uart.drawio create mode 100644 docs/src/assets/uart.svg diff --git a/docs/CMakeLists.txt b/docs/CMakeLists.txt index 3c8c504..6eaaeda 100644 --- a/docs/CMakeLists.txt +++ b/docs/CMakeLists.txt @@ -8,7 +8,9 @@ if(Sphinx_FOUND) "${CMAKE_CURRENT_LIST_DIR}/src/_ext/requirement.py" "${CMAKE_CURRENT_LIST_DIR}/src/_static/css/custom.css" "${CMAKE_CURRENT_LIST_DIR}/src/assets/logo.svg" + "${CMAKE_CURRENT_LIST_DIR}/src/assets/favicon.ico" "${CMAKE_CURRENT_LIST_DIR}/src/assets/architecture.svg" + "${CMAKE_CURRENT_LIST_DIR}/src/assets/uart.svg" "${CMAKE_CURRENT_LIST_DIR}/src/guide/registers.rst" "${CMAKE_CURRENT_LIST_DIR}/src/index.rst" "${CMAKE_CURRENT_LIST_DIR}/src/spec/content/uart_sr.rst" diff --git a/docs/src/assets/favicon.ico b/docs/src/assets/favicon.ico new file mode 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/docs/src/assets/uart.svg b/docs/src/assets/uart.svg new file mode 100644 index 0000000..1d669da --- /dev/null +++ b/docs/src/assets/uart.svg @@ -0,0 +1,3 @@ + + +
rx/tx
start
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 \ No newline at end of file diff --git a/docs/src/conf.py b/docs/src/conf.py index 45faacb..610e77f 100644 --- a/docs/src/conf.py +++ b/docs/src/conf.py @@ -42,6 +42,7 @@ html_css_files = [ 'css/custom.css' ] +html_favicon = 'assets/favicon.ico' todo_include_todos = True diff --git a/docs/src/spec/2_overall-description.rst b/docs/src/spec/2_overall-description.rst index f6199f7..bce5863 100644 --- a/docs/src/spec/2_overall-description.rst +++ b/docs/src/spec/2_overall-description.rst @@ -13,16 +13,28 @@ Serial Interface .. requirement:: U_UART_01 - The peripheral shall perform serial-to-parallel conversion of the provided data. + The peripheral shall perform parallel-to-serial conversion of the provided data. .. requirement:: U_UART_02 - The peripheral shall perform parallel-to-serial conversion of the received data. + The peripheral shall perform serial-to-parallel conversion of the received data. .. requirement:: U_UART_03 The peripheral shall support full-duplex communications. +.. requirement:: U_UART_04 + + The peripheral shall detect parity errors. + +.. requirement:: U_UART_05 + + The peripheral shall detect framing errors. + +.. requirement:: U_UART_06 + + The peripheral shall detect overrrun errors. + Configuration ^^^^^^^^^^^^^ @@ -49,61 +61,12 @@ Memory-Mapped Interface .. requirement:: U_REGISTERS_01 - The peripheral shall provide the memory-mapped registers described in the table below. + The peripheral shall provide memory-mapped configuration and status registers. .. requirement:: U_MEMORY_INTERFACE_01 The peripheral memory-mapped registers shall be accessible through a wishbone interface. -.. list-table:: Memory Mapping and Registers - :header-rows: 1 - :widths: 1 94 1 1 1 1 - - * - Address Offset - - Register name - - Width (in bits) - - Access - - Reset value - - Section/page - - * - 0000_0000h - - Status register (UART_SR) - - 32 - - R - - 0000_0000h - - :ref:`UART_SR ` - * - 0000_0004h - - Control register (UART_CR) - - 32 - - R/W - - 0000_0000h - - :ref:`UART_CR ` - * - 0000_0008h - - Receive Data register (UART_RXDR) - - 32 - - R - - 0000_0000h - - :ref:`UART_RXDR ` - * - 0000_000Ch - - Transmit Data register (UART_TXDR) - - 32 - - W - - 0000_0000h - - :ref:`UART_TXDR ` - -.. _SPEC_UART_SR: -.. include:: ../spec/content/uart_sr.rst - -.. _SPEC_UART_CR: -.. include:: ../spec/content/uart_cr.rst - -.. _SPEC_UART_RXDR: -.. include:: ../spec/content/uart_rxdr.rst - -.. _SPEC_UART_TXDR: -.. include:: ../spec/content/uart_txdr.rst - - Assumptions and Dependencies ---------------------------- diff --git a/docs/src/spec/3_requirements.rst b/docs/src/spec/3_requirements.rst index 96afe20..25e75e1 100644 --- a/docs/src/spec/3_requirements.rst +++ b/docs/src/spec/3_requirements.rst @@ -98,25 +98,84 @@ Functional Requirements ----------------------- .. requirement:: F_RESET_01 + :derivedfrom: U_REGISTERS_01 The registers shall all be reset to 0 when rst_i is asserted. .. requirement:: F_RESET_02 + :derivedfrom: U_UART_01 The uart_tx_o signal shall be asserted while rst_i is asserted. Memory interface ^^^^^^^^^^^^^^^^ +.. requirement:: F_REGISTERS_01 + :derivedfrom: U_REGISTERS_01, U_MEMORY_INTERFACE_01, U_BAUD_RATE_01, U_PARITY_BIT_01, U_DATA_SIZE_01, U_STOP_BIT_01 + + The following registers shall be implemented and accessible through the wishbone memory interface. + +.. list-table:: Memory Mapping and Registers + :header-rows: 1 + :widths: 1 94 1 1 1 1 + + * - Address Offset + - Register name + - Width (in bits) + - Access + - Reset value + - Section/page + + * - 0000_0000h + - Status register (UART_SR) + - 32 + - R + - 0000_0000h + - :ref:`UART_SR ` + * - 0000_0004h + - Control register (UART_CR) + - 32 + - R/W + - 0000_0000h + - :ref:`UART_CR ` + * - 0000_0008h + - Receive Data register (UART_RXDR) + - 32 + - R + - 0000_0000h + - :ref:`UART_RXDR ` + * - 0000_000Ch + - Transmit Data register (UART_TXDR) + - 32 + - W + - 0000_0000h + - :ref:`UART_TXDR ` + +.. _SPEC_UART_SR: +.. include:: ../spec/content/uart_sr.rst + +.. _SPEC_UART_CR: +.. include:: ../spec/content/uart_cr.rst + +.. _SPEC_UART_RXDR: +.. include:: ../spec/content/uart_rxdr.rst + +.. _SPEC_UART_TXDR: +.. include:: ../spec/content/uart_txdr.rst + + .. requirement:: F_READ_01 + :derivedfrom: U_REGISTERS_01 The UART_RXDR register shall be reset after being read and the RXNE field of UART_SR shall be deasserted. .. requirement:: F_READ_02 + :derivedfrom: U_REGISTERS_01 The following fields of UART_SR shall be reset after being read : PE, FE and RXOE. .. requirement:: F_RESET_03 + :derivedfrom: U_REGISTERS_01 Any change to UART_SR shall cancel both ongoing tranmissions and receptions. @@ -125,32 +184,50 @@ Memory interface Serial protocol ^^^^^^^^^^^^^^^ -.. todo:: Add UART protocol timing diagram +.. requirement:: F_UART_01 + + The following frame format shall be used to encode and decode transit/receive data. + +.. image:: ../assets/uart.svg + +.. requirement:: F_UART_02 + + The number of data bits, parity bits and stop bits shall match the configuration provided in UART_CR. + +.. requirement:: F_UART_03 + + The time Tbr shall be equal to the product of the CLK_DIV field of UART_CR with the period of clk_i. Receive ^^^^^^^ .. requirement:: F_RECEIVE_01 + :derivedfrom: U_UART_02 The peripheral shall sample the uart_rx_i signal with a sample interval defined in number of clk_i edges by the field CLK_DIV field of UART_CR. .. requirement:: F_RECEIVE_02 + :derivedfrom: U_UART_02 The peripheral shall set the value of the RXD field of UART_RXDR after latching the stop bit. .. requirement:: F_RECEIVE_03 + :derivedfrom: U_UART_02 The peripheral shall assert the RXNE field of UART_SR when setting the value of the RXD field. .. requirement:: F_RECEIVE_ERROR_01 + :derivedfrom: U_UART_04 The peripheral shall assert the PE field of UART_SR when the result of the xor of all the received bits is not equal to the received parity bit. .. requirement:: F_RECEIVE_ERROR_02 + :derivedfrom: U_UART_05 The peripheral shall assert the FE field of UART_SR when the received stop bit is zero instead of one. .. requirement:: F_RECEIVE_ERROR_03 + :derivedfrom: U_UART_06 The peripheral shall assert the RXOE field of UART_SR after latching the stop bit while the RXNE field of UART_SR is asserted. @@ -158,10 +235,12 @@ Transmit ^^^^^^^^ .. requirement:: F_TRANSMIT_01 + :derivedfrom: U_UART_01 The peripheral shall transmit the TXD field of UART_TXDR after a write to UART_TXDR when the TXE field of UART_SR is deasserted, with a sample interval defined in number of clk_i edges by the field CLK_DIV field of UART_CR. .. requirement:: F_TRANSMIT_02 + :derivedfrom: U_UART_01 The peripheral shall reset the UART_TXDR register after transmitting the stop bits and assert the TXE field of UART_SR. diff --git a/docs/src/spec/content/uart_sr.rst b/docs/src/spec/content/uart_sr.rst index 3b0b7a0..6630ae6 100644 --- a/docs/src/spec/content/uart_sr.rst +++ b/docs/src/spec/content/uart_sr.rst @@ -51,11 +51,11 @@ Status register (UART_SR) 1 |tab| Framing error detected * - 2 - RXOE - - *Receive Overflow Error* + - *Receive Overrun Error* This bit is cleared after reading it. - 0 |tab| No received overflow error + 0 |tab| No received overrun error 1 |tab| A packet was received but RXNE is asserted * - 1 From 39c8885f5b275e6384e471c7180dae86319b305b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20Chaine?= Date: Thu, 9 May 2024 14:52:40 +0000 Subject: [PATCH 3/3] Adds traceability --- config/traceability-matrix.csv | 132 ++++++++++++++++++ docs/src/spec/3_requirements.rst | 18 +-- .../benches/ecap5_wbuart/tb_ecap5_wbuart.cpp | 80 ++--------- tests/benches/rx_frontend/tb_rx_frontend.cpp | 6 +- .../benches/wb_interface/tb_wb_interface.cpp | 2 +- 5 files changed, 153 insertions(+), 85 deletions(-) diff --git a/config/traceability-matrix.csv b/config/traceability-matrix.csv index e69de29..1dffbfb 100644 --- a/config/traceability-matrix.csv +++ b/config/traceability-matrix.csv @@ -0,0 +1,132 @@ +tb_ecap5_wbuart.idle.01 +tb_ecap5_wbuart.idle.02 +tb_ecap5_wbuart.idle.03 +tb_ecap5_wbuart.idle.04;F_RESET_02 +tb_ecap5_wbuart.idle.05;F_RESET_01;F_REGISTERS_01 +tb_ecap5_wbuart.write_cr.01;F_RESET_03 +tb_ecap5_wbuart.write_cr.02 +tb_ecap5_wbuart.write_cr.03;F_REGISTERS_01 +tb_ecap5_wbuart.write_txdr.01 +tb_ecap5_wbuart.write_txdr.02 +tb_ecap5_wbuart.write_txdr.03 +tb_ecap5_wbuart.write_txdr.04;F_REGISTERS_01 +tb_ecap5_wbuart.read_rxdr.01;F_UART_01;F_UART_02;F_UART_03 +tb_ecap5_wbuart.read_rxdr.02 +tb_ecap5_wbuart.read_rxdr.03;F_REGISTERS_01;F_READ_01;F_RECEIVE_02;F_RECEIVE_03 +tb_ecap5_wbuart.rxoe.01 +tb_ecap5_wbuart.rxoe.02 +tb_ecap5_wbuart.rxoe.03;F_REGISTERS_01;F_READ_02;F_RECEIVE_ERROR_03 +tb_ecap5_wbuart.pe.01 +tb_ecap5_wbuart.pe.02;F_REGISTERS_01;F_READ_02;F_RECEIVE_ERROR_01 +tb_ecap5_wbuart.fe.01 +tb_ecap5_wbuart.fe.02;F_REGISTERS_01;F_READ_02;F_RECEIVE_ERROR_02 +tb_ecap5_wbuart.full_duplex.01;F_UART_04 +tb_ecap5_wbuart.full_duplex.02;F_UART_04 +tb_ecap5_wbuart.full_duplex.03;F_REGISTERS_01;F_UART_04 +tb_rx_frontend.idle.01 +tb_rx_frontend.idle.02 +tb_rx_frontend.valid.7N1_01 +tb_rx_frontend.valid.7N1_02;F_UART_01;F_UART_02;F_RECEIVE_01 +tb_rx_frontend.valid.7N1_03 +tb_rx_frontend.valid.7N1_04;F_UART_02;F_UART_03;F_RECEIVE_02 +tb_rx_frontend.valid.7N2_01 +tb_rx_frontend.valid.7N2_02;F_UART_01;F_UART_02;F_RECEIVE_01 +tb_rx_frontend.valid.7N2_03 +tb_rx_frontend.valid.7N2_04;F_UART_02;F_UART_03;F_RECEIVE_02 +tb_rx_frontend.valid.7E1_01 +tb_rx_frontend.valid.7E1_02;F_UART_01;F_UART_02;F_RECEIVE_01 +tb_rx_frontend.valid.7E1_03 +tb_rx_frontend.valid.7E1_04;F_UART_02;F_UART_03;F_RECEIVE_02 +tb_rx_frontend.valid.7E2_01 +tb_rx_frontend.valid.7E2_02;F_UART_01;F_UART_02;F_RECEIVE_01 +tb_rx_frontend.valid.7E2_03 +tb_rx_frontend.valid.7E2_04;F_UART_02;F_UART_03;F_RECEIVE_02 +tb_rx_frontend.valid.7O1_01 +tb_rx_frontend.valid.7O1_02;F_UART_01;F_UART_02;F_RECEIVE_01 +tb_rx_frontend.valid.7O1_03 +tb_rx_frontend.valid.7O1_04;F_UART_02;F_UART_03;F_RECEIVE_02 +tb_rx_frontend.valid.7O2_01 +tb_rx_frontend.valid.7O2_02;F_UART_01;F_UART_02;F_RECEIVE_01 +tb_rx_frontend.valid.7O2_03 +tb_rx_frontend.valid.7O2_04;F_UART_02;F_UART_03;F_RECEIVE_02 +tb_rx_frontend.valid.8N1_01 +tb_rx_frontend.valid.8N1_02;F_UART_01;F_UART_02;F_RECEIVE_01 +tb_rx_frontend.valid.8N1_03 +tb_rx_frontend.valid.8N1_04;F_UART_02;F_UART_03;F_RECEIVE_02 +tb_rx_frontend.valid.8N2_01 +tb_rx_frontend.valid.8N2_02;F_UART_01;F_UART_02;F_RECEIVE_01 +tb_rx_frontend.valid.8N2_03 +tb_rx_frontend.valid.8N2_04;F_UART_02;F_UART_03;F_RECEIVE_02 +tb_rx_frontend.valid.8E1_01 +tb_rx_frontend.valid.8E1_02;F_UART_01;F_UART_02;F_RECEIVE_01 +tb_rx_frontend.valid.8E1_03 +tb_rx_frontend.valid.8E1_04;F_UART_02;F_UART_03;F_RECEIVE_02 +tb_rx_frontend.valid.8E2_01 +tb_rx_frontend.valid.8E2_02;F_UART_01;F_UART_02;F_RECEIVE_01 +tb_rx_frontend.valid.8E2_03 +tb_rx_frontend.valid.8E2_04;F_UART_02;F_UART_03;F_RECEIVE_02 +tb_rx_frontend.valid.8O1_01 +tb_rx_frontend.valid.8O1_02;F_UART_01;F_UART_02;F_RECEIVE_01 +tb_rx_frontend.valid.8O1_03 +tb_rx_frontend.valid.8O1_04;F_UART_02;F_UART_03;F_RECEIVE_02 +tb_rx_frontend.valid.8O2_01 +tb_rx_frontend.valid.8O2_02;F_UART_01;F_UART_02;F_RECEIVE_01 +tb_rx_frontend.valid.8O2_03 +tb_rx_frontend.valid.8O2_04;F_UART_02;F_UART_03;F_RECEIVE_02 +tb_rx_frontend.baudrate.01 +tb_rx_frontend.baudrate.02;F_UART_01;F_UART_02;F_RECEIVE_01 +tb_rx_frontend.baudrate.03 +tb_rx_frontend.baudrate.04;F_UART_02;F_UART_03;F_RECEIVE_02 +tb_rx_frontend.parity.EVEN_01;F_RECEIVE_ERROR_01 +tb_rx_frontend.parity.EVEN_02 +tb_rx_frontend.parity.ODD_01;F_RECEIVE_ERROR_01 +tb_rx_frontend.parity.ODD_02 +tb_rx_frontend.framing.01 +tb_rx_frontend.framing.02;F_RECEIVE_ERROR_02 +tb_rx_frontend.framing.03 +tb_tx_frontend.idle.01 +tb_tx_frontend.idle.02 +tb_tx_frontend.idle.03 +tb_tx_frontend.7N1.01 +tb_tx_frontend.7N1.02;F_UART_01;F_UART_02;F_TRANSMIT_01 +tb_tx_frontend.7N1.03;F_UART_02;F_UART_03;F_TRANSMIT_01 +tb_tx_frontend.7N2.01 +tb_tx_frontend.7N2.02;F_UART_01;F_UART_02;F_TRANSMIT_01 +tb_tx_frontend.7N2.03;F_UART_02;F_UART_03;F_TRANSMIT_01 +tb_tx_frontend.7E1.01 +tb_tx_frontend.7E1.02;F_UART_01;F_UART_02;F_TRANSMIT_01 +tb_tx_frontend.7E1.03;F_UART_02;F_UART_03;F_TRANSMIT_01 +tb_tx_frontend.7E2.01 +tb_tx_frontend.7E2.02;F_UART_01;F_UART_02;F_TRANSMIT_01 +tb_tx_frontend.7E2.03;F_UART_02;F_UART_03;F_TRANSMIT_01 +tb_tx_frontend.7O1.01 +tb_tx_frontend.7O1.02;F_UART_01;F_UART_02;F_TRANSMIT_01 +tb_tx_frontend.7O1.03;F_UART_02;F_UART_03;F_TRANSMIT_01 +tb_tx_frontend.7O2.01 +tb_tx_frontend.7O2.02;F_UART_01;F_UART_02;F_TRANSMIT_01 +tb_tx_frontend.7O2.03;F_UART_02;F_UART_03;F_TRANSMIT_01 +tb_tx_frontend.8N1.01 +tb_tx_frontend.8N1.02;F_UART_01;F_UART_02;F_TRANSMIT_01 +tb_tx_frontend.8N1.03;F_UART_02;F_UART_03;F_TRANSMIT_01 +tb_tx_frontend.8N2.01 +tb_tx_frontend.8N2.02;F_UART_01;F_UART_02;F_TRANSMIT_01 +tb_tx_frontend.8N2.03;F_UART_02;F_UART_03;F_TRANSMIT_01 +tb_tx_frontend.8E1.01 +tb_tx_frontend.8E1.02;F_UART_01;F_UART_02;F_TRANSMIT_01 +tb_tx_frontend.8E1.03;F_UART_02;F_UART_03;F_TRANSMIT_01 +tb_tx_frontend.8E2.01 +tb_tx_frontend.8E2.02;F_UART_01;F_UART_02;F_TRANSMIT_01 +tb_tx_frontend.8E2.03;F_UART_02;F_UART_03;F_TRANSMIT_01 +tb_tx_frontend.8O1.01 +tb_tx_frontend.8O1.02;F_UART_01;F_UART_02;F_TRANSMIT_01 +tb_tx_frontend.8O1.03;F_UART_02;F_UART_03;F_TRANSMIT_01 +tb_tx_frontend.8O2.01 +tb_tx_frontend.8O2.02;F_UART_01;F_UART_02;F_TRANSMIT_01 +tb_tx_frontend.8O2.03;F_UART_02;F_UART_03;F_TRANSMIT_01 +tb_tx_frontend.baudrate.01 +tb_tx_frontend.baudrate.02;F_UART_01;F_UART_02;F_TRANSMIT_01 +tb_tx_frontend.baudrate.03;F_UART_02;F_UART_03;F_TRANSMIT_01 +tb_wb_interface.read.01;I_MEMORY_INTERFACE_01 +tb_wb_interface.read.02;I_MEMORY_INTERFACE_01 +tb_wb_interface.write.01;I_MEMORY_INTERFACE_01 +tb_wb_interface.write.02;I_MEMORY_INTERFACE_01 diff --git a/docs/src/spec/3_requirements.rst b/docs/src/spec/3_requirements.rst index 25e75e1..919eb45 100644 --- a/docs/src/spec/3_requirements.rst +++ b/docs/src/spec/3_requirements.rst @@ -177,27 +177,32 @@ Memory interface .. requirement:: F_RESET_03 :derivedfrom: U_REGISTERS_01 - Any change to UART_SR shall cancel both ongoing tranmissions and receptions. - -.. todo:: Add wishbone requirements + Any change to UART_CR shall cancel both ongoing tranmissions and receptions. Serial protocol ^^^^^^^^^^^^^^^ .. requirement:: F_UART_01 - + :derivedfrom: U_UART_01, U_UART_02 The following frame format shall be used to encode and decode transit/receive data. .. image:: ../assets/uart.svg .. requirement:: F_UART_02 + :derivedfrom: U_PARITY_BIT_01, U_DATA_SIZE_01, U_STOP_BIT_01 The number of data bits, parity bits and stop bits shall match the configuration provided in UART_CR. .. requirement:: F_UART_03 + :derivedfrom: U_BAUD_RATE_01 The time Tbr shall be equal to the product of the CLK_DIV field of UART_CR with the period of clk_i. +.. requirement:: F_UART_04 + :derivedfrom: U_UART_03 + + Parallel transmission/reception shall be supported. + Receive ^^^^^^^ @@ -239,11 +244,6 @@ Transmit The peripheral shall transmit the TXD field of UART_TXDR after a write to UART_TXDR when the TXE field of UART_SR is deasserted, with a sample interval defined in number of clk_i edges by the field CLK_DIV field of UART_CR. -.. requirement:: F_TRANSMIT_02 - :derivedfrom: U_UART_01 - - The peripheral shall reset the UART_TXDR register after transmitting the stop bits and assert the TXE field of UART_SR. - Non-functional Requirements --------------------------- diff --git a/tests/benches/ecap5_wbuart/tb_ecap5_wbuart.cpp b/tests/benches/ecap5_wbuart/tb_ecap5_wbuart.cpp index c7ff5fc..2878c38 100644 --- a/tests/benches/ecap5_wbuart/tb_ecap5_wbuart.cpp +++ b/tests/benches/ecap5_wbuart/tb_ecap5_wbuart.cpp @@ -299,14 +299,6 @@ void tb_ecap5_wbuart_write_cr(TB_Ecap5_wbuart * tb) { "Failed to integrate the memory", tb->err_cycles[COND_mem]); CHECK("tb_ecap5_wbuart.write_cr.03", - tb->conditions[COND_rx], - "Failed to integrate the rx frontend", tb->err_cycles[COND_rx]); - - CHECK("tb_ecap5_wbuart.write_cr.04", - tb->conditions[COND_tx], - "Failed to integrate the tx frontend", tb->err_cycles[COND_tx]); - - CHECK("tb_ecap5_wbuart.write_cr.05", tb->conditions[COND_registers], "Failed to implement the memory-mapped registers", tb->err_cycles[COND_registers]); } @@ -470,14 +462,10 @@ void tb_ecap5_wbuart_write_txdr(TB_Ecap5_wbuart * tb) { "Failed to integrate the memory", tb->err_cycles[COND_mem]); CHECK("tb_ecap5_wbuart.write_txdr.03", - tb->conditions[COND_rx], - "Failed to integrate the rx frontend", tb->err_cycles[COND_rx]); - - CHECK("tb_ecap5_wbuart.write_txdr.04", tb->conditions[COND_tx], "Failed to integrate the tx frontend", tb->err_cycles[COND_tx]); - CHECK("tb_ecap5_wbuart.write_txdr.05", + CHECK("tb_ecap5_wbuart.write_txdr.04", tb->conditions[COND_registers], "Failed to implement the memory-mapped registers", tb->err_cycles[COND_registers]); } @@ -643,23 +631,15 @@ void tb_ecap5_wbuart_read_rxdr(TB_Ecap5_wbuart * tb) { //````````````````````````````````` // Formal Checks - CHECK("tb_ecap5_wbuart.write_rxdr.01", - tb->conditions[COND_reset], - "Failed to implement the frontend reset", tb->err_cycles[COND_reset]); - - CHECK("tb_ecap5_wbuart.write_rxdr.02", + CHECK("tb_ecap5_wbuart.read_rxdr.01", tb->conditions[COND_mem], "Failed to integrate the memory", tb->err_cycles[COND_mem]); - CHECK("tb_ecap5_wbuart.write_rxdr.03", + CHECK("tb_ecap5_wbuart.read_rxdr.02", tb->conditions[COND_rx], "Failed to integrate the rx frontend", tb->err_cycles[COND_rx]); - CHECK("tb_ecap5_wbuart.write_rxdr.04", - tb->conditions[COND_tx], - "Failed to integrate the tx frontend", tb->err_cycles[COND_tx]); - - CHECK("tb_ecap5_wbuart.write_rxdr.05", + CHECK("tb_ecap5_wbuart.read_rxdr.03", tb->conditions[COND_registers], "Failed to implement the memory-mapped registers", tb->err_cycles[COND_registers]); } @@ -839,22 +819,14 @@ void tb_ecap5_wbuart_rxoe(TB_Ecap5_wbuart * tb) { // Formal Checks CHECK("tb_ecap5_wbuart.rxoe.01", - tb->conditions[COND_reset], - "Failed to implement the frontend reset", tb->err_cycles[COND_reset]); - - CHECK("tb_ecap5_wbuart.rxoe.02", tb->conditions[COND_mem], "Failed to integrate the memory", tb->err_cycles[COND_mem]); - CHECK("tb_ecap5_wbuart.rxoe.03", + CHECK("tb_ecap5_wbuart.rxoe.02", tb->conditions[COND_rx], "Failed to integrate the rx frontend", tb->err_cycles[COND_rx]); - CHECK("tb_ecap5_wbuart.rxoe.04", - tb->conditions[COND_tx], - "Failed to integrate the tx frontend", tb->err_cycles[COND_tx]); - - CHECK("tb_ecap5_wbuart.rxoe.05", + CHECK("tb_ecap5_wbuart.rxoe.03", tb->conditions[COND_registers], "Failed to implement the memory-mapped registers", tb->err_cycles[COND_registers]); } @@ -958,22 +930,10 @@ void tb_ecap5_wbuart_pe(TB_Ecap5_wbuart * tb) { // Formal Checks CHECK("tb_ecap5_wbuart.pe.01", - tb->conditions[COND_reset], - "Failed to implement the frontend reset", tb->err_cycles[COND_reset]); - - CHECK("tb_ecap5_wbuart.pe.02", tb->conditions[COND_mem], "Failed to integrate the memory", tb->err_cycles[COND_mem]); - CHECK("tb_ecap5_wbuart.pe.03", - tb->conditions[COND_rx], - "Failed to integrate the rx frontend", tb->err_cycles[COND_rx]); - - CHECK("tb_ecap5_wbuart.pe.04", - tb->conditions[COND_tx], - "Failed to integrate the tx frontend", tb->err_cycles[COND_tx]); - - CHECK("tb_ecap5_wbuart.pe.05", + CHECK("tb_ecap5_wbuart.pe.02", tb->conditions[COND_registers], "Failed to implement the memory-mapped registers", tb->err_cycles[COND_registers]); } @@ -1077,22 +1037,10 @@ void tb_ecap5_wbuart_fe(TB_Ecap5_wbuart * tb) { // Formal Checks CHECK("tb_ecap5_wbuart.fe.01", - tb->conditions[COND_reset], - "Failed to implement the frontend reset", tb->err_cycles[COND_reset]); - - CHECK("tb_ecap5_wbuart.fe.02", tb->conditions[COND_mem], "Failed to integrate the memory", tb->err_cycles[COND_mem]); - CHECK("tb_ecap5_wbuart.fe.03", - tb->conditions[COND_rx], - "Failed to integrate the rx frontend", tb->err_cycles[COND_rx]); - - CHECK("tb_ecap5_wbuart.fe.04", - tb->conditions[COND_tx], - "Failed to integrate the tx frontend", tb->err_cycles[COND_tx]); - - CHECK("tb_ecap5_wbuart.fe.05", + CHECK("tb_ecap5_wbuart.fe.02", tb->conditions[COND_registers], "Failed to implement the memory-mapped registers", tb->err_cycles[COND_registers]); } @@ -1239,22 +1187,14 @@ void tb_ecap5_wbuart_full_duplex(TB_Ecap5_wbuart * tb) { // Formal Checks CHECK("tb_ecap5_wbuart.full_duplex.01", - tb->conditions[COND_reset], - "Failed to implement the frontend reset", tb->err_cycles[COND_reset]); - - CHECK("tb_ecap5_wbuart.full_duplex.02", - tb->conditions[COND_mem], - "Failed to integrate the memory", tb->err_cycles[COND_mem]); - - CHECK("tb_ecap5_wbuart.full_duplex.03", tb->conditions[COND_rx], "Failed to integrate the rx frontend", tb->err_cycles[COND_rx]); - CHECK("tb_ecap5_wbuart.full_duplex.04", + CHECK("tb_ecap5_wbuart.full_duplex.02", tb->conditions[COND_tx], "Failed to integrate the tx frontend", tb->err_cycles[COND_tx]); - CHECK("tb_ecap5_wbuart.full_duplex.05", + CHECK("tb_ecap5_wbuart.full_duplex.03", tb->conditions[COND_registers], "Failed to implement the memory-mapped registers", tb->err_cycles[COND_registers]); } diff --git a/tests/benches/rx_frontend/tb_rx_frontend.cpp b/tests/benches/rx_frontend/tb_rx_frontend.cpp index ca49b17..a4c610e 100644 --- a/tests/benches/rx_frontend/tb_rx_frontend.cpp +++ b/tests/benches/rx_frontend/tb_rx_frontend.cpp @@ -3576,14 +3576,10 @@ void tb_rx_frontend_framing(TB_Rx_frontend * tb) { "Failed to implement the state machine", tb->err_cycles[COND_state]); CHECK("tb_rx_frontend.framing.02", - tb->conditions[COND_frame], - "Failed to implement the frame output", tb->err_cycles[COND_frame]); - - CHECK("tb_rx_frontend.framing.03", tb->conditions[COND_errors], "Failed to implement the errors computation", tb->err_cycles[COND_errors]); - CHECK("tb_rx_frontend.framing.04", + CHECK("tb_rx_frontend.framing.03", tb->conditions[COND_valid], "Failed to implement the valid signal", tb->err_cycles[COND_valid]); } diff --git a/tests/benches/wb_interface/tb_wb_interface.cpp b/tests/benches/wb_interface/tb_wb_interface.cpp index da1b53c..cd9ba70 100644 --- a/tests/benches/wb_interface/tb_wb_interface.cpp +++ b/tests/benches/wb_interface/tb_wb_interface.cpp @@ -96,7 +96,7 @@ void tb_wb_interface_read(TB_Wb_interface * tb) { // Set inputs tb->check(COND_output, (core->read_o == 0) && - (core->write_o == 0)); + (core->write_o == 0)); uint32_t addr = rand(); tb->read(addr);