🍱 Added the MNT logo to the README and RtD (cda-tum#215)

* 🍱 Added the MNT logo to the README and RtD

* 🍱 Changed the colors for the sidebar logo

* 📄 Updated copyright and authorship

Author: marcelwa

LICENSE.txt

@@ -1,4 +1,5 @@
-Copyright 2022 Marcel Walter, Technical University of Munich (TUM)
+Copyright 2018-2023 Marcel Walter
+Copyright 2023-present, Chair for Design Automation, Technical University of Munich
 
 Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated
 documentation files (the "Software"), to deal in the Software without restriction, including without limitation the

README.md

@@ -11,6 +11,13 @@
 [![Release](https://img.shields.io/github/v/release/marcelwa/fiction?label=fiction&style=flat-square)](https://github.com/marcelwa/fiction/releases)
 [![arXiv](https://img.shields.io/static/v1?label=arXiv&message=1905.02477&color=informational&style=flat-square)](https://arxiv.org/abs/1905.02477)
 
+<p align="center">
+  <picture>
+    <source media="(prefers-color-scheme: dark)" srcset="docs/_static/mnt_light.svg" width="60%">
+    <img src="docs/_static/mnt_dark.svg" width="60%">
+  </picture>
+</p>
+
 This code base provides a framework for **fi**eld-**c**oupled **t**echnology-**i**ndependent **o**pen **n**anocomputing
 in C++17 using the [EPFL Logic Synthesis Libraries](https://github.com/lsils/lstools-showcase). Thereby, *fiction*
 focuses on the logic synthesis, placement, routing, clocking, and verification of emerging nanotechnologies. As a
@@ -177,7 +184,8 @@ Among these algorithms are
 - SMT-based [exact placement and routing](https://ieeexplore.ieee.org/document/8342060)
 - OGD-based [scalable placement and routing](https://dl.acm.org/citation.cfm?id=3287705)
 - SAT-based [one-pass synthesis](https://ieeexplore.ieee.org/document/9371573)
-- SAT-based [multi-path routing](https://www.cda.cit.tum.de/files/eda/2022_nanoarch_efficient_multi-path_signal_routing_for_fcn.pdf)
+-
+SAT-based [multi-path routing](https://www.cda.cit.tum.de/files/eda/2022_nanoarch_efficient_multi-path_signal_routing_for_fcn.pdf)
 
 plus several path finding algorithms that work on generic layouts:
 
@@ -199,8 +207,8 @@ When a layout is compiled to the cell-level via the application of a technology-
 simulated using a physical model. Currently, the following simulation algorithms are implemented in *fiction*:
 
 - Silicon Dangling Bonds (SiDBs)
-  - [Exhaustive Groundstate Simulation (ExGS)](https://fiction.readthedocs.io/en/latest/algorithms/sidb_simulation.html#_CPPv4I0EN7fiction34exhaustive_ground_state_simulationEvRK3LytRK26sidb_simulation_parametersP10exgs_statsI3LytE)
-  - [*QuickSim* Groundstate Simulation](https://arxiv.org/abs/2303.03422)
+    - [Exhaustive Groundstate Simulation (ExGS)](https://fiction.readthedocs.io/en/latest/algorithms/sidb_simulation.html#_CPPv4I0EN7fiction34exhaustive_ground_state_simulationEvRK3LytRK26sidb_simulation_parametersP10exgs_statsI3LytE)
+    - [*QuickSim* Groundstate Simulation](https://arxiv.org/abs/2303.03422)
 
 ## Clocking Schemes
 
@@ -265,7 +273,6 @@ tiles, [synchronization elements](https://ieeexplore.ieee.org/document/8626294)
 multiple clock cycles. These artificial latches are able to feed information to any other clock number, but their usage
 reduces the overall throughput of the layout. In return, long wire detours for signal synchronization can be prevented.
 
-
 ## Cost Metrics
 
 Designed layouts can be evaluated with regard to several cost functions. The following metrics are currently