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6.31 #49

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xhnatiuk opened this issue Dec 13, 2019 · 1 comment

xhnatiuk commented Dec 13, 2019 •

edited

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I believe cache access is a miss because the valid bit is 0.

Ltw10 commented Mar 31, 2021

There is also another cache with tag 38 and valid bit set so I think the solution is correct

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