diff --git a/PC.v b/PC.v new file mode 100644 index 0000000..6ccbb65 --- /dev/null +++ b/PC.v @@ -0,0 +1,25 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 13:30:46 05/02/2022 +// Design Name: +// Module Name: PC +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module PC( + ); + + +endmodule diff --git a/PC_Adder.v b/PC_Adder.v new file mode 100644 index 0000000..2ea654e --- /dev/null +++ b/PC_Adder.v @@ -0,0 +1,25 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 13:29:58 05/02/2022 +// Design Name: +// Module Name: PC_Adder +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module PC_Adder( + ); + + +endmodule diff --git a/Pipeline_processor.gise b/Pipeline_processor.gise new file mode 100644 index 0000000..76d75a7 --- /dev/null +++ b/Pipeline_processor.gise @@ -0,0 +1,28 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + diff --git a/Pipeline_processor.xise b/Pipeline_processor.xise new file mode 100644 index 0000000..146ae4c --- /dev/null +++ b/Pipeline_processor.xise @@ -0,0 +1,406 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Sign_Extend.v b/Sign_Extend.v new file mode 100644 index 0000000..dd334c8 --- /dev/null +++ b/Sign_Extend.v @@ -0,0 +1,25 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 13:31:06 05/02/2022 +// Design Name: +// Module Name: Sign_Extend +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Sign_Extend( + ); + + +endmodule diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs new file mode 100644 index 0000000..17e4362 --- /dev/null +++ b/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ + + + + + + + + + + +Analyzing Verilog file "/home/ise/Desktop/shared_folder/PDS_project_pipeline_processor/Pipeline_processor/Sign_Extend.v" into library work + + + + diff --git a/iseconfig/Pipeline_processor.projectmgr b/iseconfig/Pipeline_processor.projectmgr new file mode 100644 index 0000000..8b159ac --- /dev/null +++ b/iseconfig/Pipeline_processor.projectmgr @@ -0,0 +1,88 @@ + + + + + + + + + 2 + + + xc3s500e-5vq100 + + 1 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000fe000000020000000000000000000000000200000064ffffffff000000810000000300000002000000fe0000000100000003000000000000000100000003 + true + xc3s500e-5vq100 + + + + 1 + Design Utilities + + + + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000 + false + + + + + 1 + + + 0 + 0 + 000000ff0000000000000001000000000000000001000000000000000000000000000000000000016f000000040101000100000000000000000000000064ffffffff000000810000000000000004000000510000000100000000000000290000000100000000000000840000000100000000000000710000000100000000 + false + + + + + 1 + work + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000128000000010001000100000000000000000000000064ffffffff000000810000000000000001000001280000000100000000 + false + work + + + + 1 + Configure Target Device + Design Utilities + Implement Design + Synthesize - XST + User Constraints + + + + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000e5000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e50000000100000000 + false + + + + + 1 + + + 0 + 0 + + false + + + 000000ff00000000000000020000014c0000011d01000000060100000002 + Implementation + diff --git a/iseconfig/mux1.xreport b/iseconfig/mux1.xreport new file mode 100644 index 0000000..b3c832f --- /dev/null +++ b/iseconfig/mux1.xreport @@ -0,0 +1,215 @@ + + +
+ 2022-05-02T13:28:46 + mux1 + Unknown + /home/ise/Desktop/shared_folder/PDS_project_pipeline_processor/Pipeline_processor/iseconfig/mux1.xreport + /home/ise/Desktop/shared_folder/PDS_project_pipeline_processor/Pipeline_processor + 2022-05-02T13:28:46 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/mux1.v b/mux1.v new file mode 100644 index 0000000..41bd32d --- /dev/null +++ b/mux1.v @@ -0,0 +1,25 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 13:28:45 05/02/2022 +// Design Name: +// Module Name: mux1 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mux1( + ); + + +endmodule diff --git a/mux1_summary.html b/mux1_summary.html new file mode 100644 index 0000000..4a8f7c1 --- /dev/null +++ b/mux1_summary.html @@ -0,0 +1,79 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
mux1 Project Status
Project File:Pipeline_processor.xiseParser Errors: No Errors
Module Name:mux1Implementation State:New
Target Device:xc3s500e-5vq100
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 + 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: 
  • Final Timing Score:
  
+ + + + + + + + + + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + +
Secondary Reports [-]
Report NameStatusGenerated
+ + +
Date Generated: 05/02/2022 - 13:28:46
+ \ No newline at end of file diff --git a/mux2.v b/mux2.v new file mode 100644 index 0000000..d7427a8 --- /dev/null +++ b/mux2.v @@ -0,0 +1,25 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 13:29:16 05/02/2022 +// Design Name: +// Module Name: mux2 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mux2( + ); + + +endmodule diff --git a/mux2.vhd b/mux2.vhd new file mode 100644 index 0000000..b324034 --- /dev/null +++ b/mux2.vhd @@ -0,0 +1,41 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:29:00 05/02/2022 +-- Design Name: +-- Module Name: mux2 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity mux2 is +end mux2; + +architecture Behavioral of mux2 is + +begin + + +end Behavioral; + diff --git a/mux3.v b/mux3.v new file mode 100644 index 0000000..3b6becd --- /dev/null +++ b/mux3.v @@ -0,0 +1,25 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 13:29:29 05/02/2022 +// Design Name: +// Module Name: mux3 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mux3( + ); + + +endmodule diff --git a/mux4.v b/mux4.v new file mode 100644 index 0000000..2fa2649 --- /dev/null +++ b/mux4.v @@ -0,0 +1,25 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 13:29:40 05/02/2022 +// Design Name: +// Module Name: mux4 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mux4( + ); + + +endmodule