diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 510897a3a31..4c59a398ea4 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -75,7 +75,7 @@ jobs: strategy: matrix: vendor: [ protectli ] - model: [ vp46xx, V1210, V1410, V1610 ] + model: [ vp46xx, V1210, V1410, V1610, FW6 ] steps: - name: Checkout repository uses: actions/checkout@v3 diff --git a/build.sh b/build.sh index 42b532f2d61..9ec7a867226 100755 --- a/build.sh +++ b/build.sh @@ -160,6 +160,47 @@ function build_v1x10 { fi } +function build_fw6 { + DEFCONFIG="configs/config.protectli_fw6" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + + if [ ! -d 3rdparty/blobs/mainboard ]; then + git submodule update --init --checkout + fi + + if [ ! -d 3rdparty/blobs/mainboard/protectli/vault_kbl ]; then + if [ -f protectli_blobs.zip ]; then + unzip protectli_blobs.zip -d 3rdparty/blobs/mainboard + else + echo "Platform blobs missing! You must obtain them first." + exit 1 + fi + fi + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:2021-09-23_b0d87f753c \ + /bin/bash -c "make distclean" + + cp $DEFCONFIG .config + + echo "Building Dasharo for Protectli FW6 (version $FW_VERSION)" + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \ + /bin/bash -c "make olddefconfig && make -j$(nproc)" + + cp build/coreboot.rom protectli_fw6_${FW_VERSION}.rom + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/protectli_fw6_${FW_VERSION}.rom" + sha256sum protectli_fw6_${FW_VERSION}.rom > protectli_fw6_${FW_VERSION}.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + CMD="$1" @@ -192,6 +233,9 @@ case "$CMD" in "v1610" | "V1610" ) build_v1x10 "v1610" ;; + "fw6" | "FW6" ) + build_fw6 + ;; *) echo "Invalid command: \"$CMD\"" usage diff --git a/configs/config.protectli_fw6 b/configs/config.protectli_fw6 new file mode 100644 index 00000000000..40f4e49eeaa --- /dev/null +++ b/configs/config.protectli_fw6 @@ -0,0 +1,46 @@ +CONFIG_LOCALVERSION="v1.1.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PROTECTLI_FW6=y +CONFIG_EDK2_BOOTSPLASH_FILE="$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR)/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX=y +CONFIG_HAVE_ME_BIN=y +CONFIG_RUN_FSP_GOP=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_POST_DEVICE_LPC=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="1174634037dc986a2221176657407ea3447cf6a6" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +CONFIG_EDK2_SECURE_BOOT=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_INTEL_ME_DISABLED_HECI=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_PXE_ADD_SCRIPT=y +CONFIG_PXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_PXE_CUSTOM_BUILD_ID="0123456789" diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index da28b80847c..aad49ae542d 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -404,7 +404,7 @@ print: echo " Repository: $(CONFIG_EDK2_REPOSITORY)" echo " Branch: $(CONFIG_EDK2_TAG_OR_REV)" echo " Packages path: $(PACKAGES_PATH)" - echo " $(BUILD_STR)" | \ + echo " -a IA32 -a X64 -b $(RELEASE_STR) $(BUILD_STR)" | \ sed -e 's/--/-/g' -e 's/-/\n /g' | sort | sed \ -e 's/a /Architecture: /g' \ -e 's/b /Release: /g' \ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 797ad91ec72..cfd2c4edc55 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4377,6 +4377,8 @@ #define PCI_DID_INTEL_GLK_CSE0 0x319a #define PCI_DID_INTEL_CNL_CSE0 0x9de0 #define PCI_DID_INTEL_SKL_CSE0 0x9d3a +#define PCI_DID_INTEL_SKL_H_CSE0 0xa13a +#define PCI_DID_INTEL_KBL_H_CSE0 0xa2ba #define PCI_DID_INTEL_LWB_CSE0 0xa1ba #define PCI_DID_INTEL_LWB_CSE1 0xa1bb #define PCI_DID_INTEL_LWB_CSE2 0xa1be diff --git a/src/mainboard/protectli/vault_kbl/Kconfig b/src/mainboard/protectli/vault_kbl/Kconfig index 310a744a651..bd85f17e2a2 100644 --- a/src/mainboard/protectli/vault_kbl/Kconfig +++ b/src/mainboard/protectli/vault_kbl/Kconfig @@ -9,8 +9,9 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LIBGFXINIT select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS select SOC_INTEL_KABYLAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPI_FLASH_MACRONIX - select SUPERIO_ITE_IT8772F + select SUPERIO_ITE_IT8613E select CRB_TPM select HAVE_INTEL_PTT select MAINBOARD_HAS_TPM2 @@ -19,7 +20,10 @@ config MAINBOARD_DIR default "protectli/vault_kbl" config MAINBOARD_PART_NUMBER - default "FW6" + default "FW6" + +config MAINBOARD_FAMILY + default "Vault" config DIMM_MAX default 2 @@ -28,21 +32,33 @@ config DIMM_SPD_SIZE default 512 config MAX_CPUS - int - default 4 + default 8 + +config DEVICETREE + default "devicetree.cb" config VGA_BIOS_ID - string - default "8086,5916" # 8086,5906 for FW6A + default "8086,5916" # FW6A/B/C + +config VGA_BIOS_SECOND_ID + default "8086,5917" # FW6D/E config PXE_ROM_ID - string default "8086,150c" config CBFS_SIZE default 0x600000 -config USE_PM_ACPI_TIMER - default n +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config BEEP_ON_BOOT + bool "Beep on successful boot" + default y + help + Make the platform beep using the PC speaker in final coreboot phase. + May serve as a useful indicator in headless mode that platform is + properly booting. + endif diff --git a/src/mainboard/protectli/vault_kbl/Makefile.inc b/src/mainboard/protectli/vault_kbl/Makefile.inc index 4cd7aaca852..be6bc46effd 100644 --- a/src/mainboard/protectli/vault_kbl/Makefile.inc +++ b/src/mainboard/protectli/vault_kbl/Makefile.inc @@ -2,6 +2,9 @@ bootblock-y += bootblock.c -ramstage-y += ramstage.c - ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += die.c +romstage-y += die.c +ramstage-y += die.c +smm-y += die.c diff --git a/src/mainboard/protectli/vault_kbl/acpi/ec.asl b/src/mainboard/protectli/vault_kbl/acpi/ec.asl index 16990d45f42..73fa78ef14e 100644 --- a/src/mainboard/protectli/vault_kbl/acpi/ec.asl +++ b/src/mainboard/protectli/vault_kbl/acpi/ec.asl @@ -1,3 +1 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/protectli/vault_kbl/acpi/superio.asl b/src/mainboard/protectli/vault_kbl/acpi/superio.asl index 16990d45f42..555422b3374 100644 --- a/src/mainboard/protectli/vault_kbl/acpi/superio.asl +++ b/src/mainboard/protectli/vault_kbl/acpi/superio.asl @@ -1,3 +1,7 @@ -/* SPDX-License-Identifier: CC-PDDC */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* Please update the license if adding licensable material. */ +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8786E_SHOW_UARTA + +#include diff --git a/src/mainboard/protectli/vault_kbl/board.fmd b/src/mainboard/protectli/vault_kbl/board.fmd new file mode 100644 index 00000000000..f5db010bd9a --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/board.fmd @@ -0,0 +1,14 @@ +FLASH@0xff800000 8M { + SI_ALL 2M { + SI_DESC 4K + SI_ME + } + + SMMSTORE(PRESERVE) 256K + RW_MRC_CACHE 64K + BOOTSPLASH(CBFS) 512K + WP_RO { + FMAP 0x800 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/protectli/vault_kbl/board_info.txt b/src/mainboard/protectli/vault_kbl/board_info.txt index 70bd1746e29..111ad3099e0 100644 --- a/src/mainboard/protectli/vault_kbl/board_info.txt +++ b/src/mainboard/protectli/vault_kbl/board_info.txt @@ -1,5 +1,5 @@ Vendor name: Protectli -Board name: FW6A/FW6B/FW6C +Board name: FW6A/FW6B/FW6C/FW6D/FW6E Category: sbc ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/protectli/vault_kbl/bootblock.c b/src/mainboard/protectli/vault_kbl/bootblock.c index a11b5fdc3bb..ca81185d319 100644 --- a/src/mainboard/protectli/vault_kbl/bootblock.c +++ b/src/mainboard/protectli/vault_kbl/bootblock.c @@ -1,15 +1,33 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include +#include #include +#include -#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) -#define UART_DEV PNP_DEV(0x2e, IT8772F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) +#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) + +/* Return an id of the installed chip. */ +static uint16_t ite_read_id(void) +{ + pnp_enter_conf_state(GPIO_DEV); + uint16_t id = (pnp_read_config(GPIO_DEV, 0x20) << 8) + | pnp_read_config(GPIO_DEV, 0x21); + pnp_exit_conf_state(GPIO_DEV); + return id; +} void bootblock_mainboard_early_init(void) { - ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24); + if (ite_read_id() == 0x8613){ + ite_reg_write(GPIO_DEV, 0x23, 0x49); /* CLK Select Ext CLKIN, 24MHz */ + ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* Disable k8 power seq */ + ite_reg_write(GPIO_DEV, 0x2d, 0x02); /* PCICLK 25MHz */ + ite_reg_write(GPIO_DEV, 0x71, 0x08); /* Ext CLKIN PCICLK */ + } else { + ite_conf_clkin(GPIO_DEV, ITE_UART_CLK_PREDIVIDE_24); + } ite_enable_3vsbsw(GPIO_DEV); ite_kill_watchdog(GPIO_DEV); ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/protectli/vault_kbl/data.vbt b/src/mainboard/protectli/vault_kbl/data.vbt index 4379ed1a6e8..2046d3109fc 100644 Binary files a/src/mainboard/protectli/vault_kbl/data.vbt and b/src/mainboard/protectli/vault_kbl/data.vbt differ diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 1f17fb13586..8393f8eec7e 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -1,13 +1,4 @@ chip soc/intel/skylake - - # Enable deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" - register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" - register "s0ix_enable" = true - register "gpe0_dw0" = "GPP_B" register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" @@ -17,22 +8,15 @@ chip soc/intel/skylake register "gen3_dec" = "0x000c03e1" register "gen4_dec" = "0x001c02e1" + # Enable "Intel Speed Shift Technology" register "eist_enable" = "1" - # Disable DPTF - register "dptf_enable" = "0" - # Enable SERIRQ continuous register "serirq_mode" = "SERIRQ_CONTINUOUS" - register "tcc_offset" = "5" # TCC of 95C + register "tcc_offset" = "25" # TCC of 75C # FSP Configuration - register "SataSalpSupport" = "0" - register "DspEnable" = "0" - register "IoBufferOwnership" = "0" - register "SsicPortEnable" = "0" - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" register "IslVrCmd" = "2" @@ -143,10 +127,6 @@ chip soc/intel/skylake register "PcieRpLtrEnable[5]" = "1" register "PcieRpLtrEnable[8]" = "1" - # Enable RP 9 CLKREQ# support - register "PcieRpClkReqSupport[8]" = "1" - # RP 9 uses CLKREQ0# - register "PcieRpClkReqNumber[8]" = "0" # Clocks 0-5 for RP 1-6 register "PcieRpClkSrcNumber[0]" = "0" @@ -159,21 +139,30 @@ chip soc/intel/skylake register "PcieRpClkSrcNumber[8]" = "5" - # USB 2.0 enable ports 1-8, disable ports 9-12 + # USB 2.0 enable ports 1-8 and 10, disable ports 9, 11-12 register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port - register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port - register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port - register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port - register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # FUSB1 + register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # FUSB1 + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # FUSB2 + register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # FW6: mPCIe, FW6D: mSATA slot + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[9]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot, WIFI slot + register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disabled + register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disabled # USB 3.0 enable ports 1-4, disable ports 5-6 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled + + register "usb2_wake_enable_bitmap" = "0xf" + register "usb3_wake_enable_bitmap" = "0xf" register "SerialIoDevMode" = "{ \ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ @@ -189,84 +178,48 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ }" + register "LockDownConfigGlobalSmi" = "true" + device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA thermal subsystem - device pci 05.0 off end # SA IMGU - device pci 08.0 off end # Gaussian Mixture Model - device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 off end # Thermal Subsystem - device pci 14.3 off end # Camera I/O Host Controller - device pci 15.0 off end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 on end # SATA - device pci 19.0 off end # UART #2 - device pci 19.1 off end # I2C #5 - device pci 19.2 off end # I2C #4 - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 on end # PCI Express Port 2 - device pci 1c.2 on end # PCI Express Port 3 - device pci 1c.3 on end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 on end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on # PCI Express Port 9 - WiFi + device ref system_agent on end + device ref igpu on end + device ref south_xhci on end + device ref heci1 on end + device ref sata on end + device ref pcie_rp1 on end + device ref pcie_rp2 on end + device ref pcie_rp3 on end + device ref pcie_rp4 on end + device ref pcie_rp5 on end + device ref pcie_rp6 on end + device ref pcie_rp9 on smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X" end - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1e.4 off end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 off end # SDCard - device pci 1f.0 on - chip superio/ite/it8772f - register "peci_tmpin" = "3" - register "tmpin1_mode" = "THERMAL_RESISTOR" - register "tmpin2_mode" = "THERMAL_RESISTOR" - # FAN2 available on fan header but unused - device pnp 2e.0 off end # FDC - device pnp 2e.1 on # Serial Port 1 + device ref lpc_espi on + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.4 on # Environment Controller - io 0x60 = 0xa40 - io 0x62 = 0xa30 - irq 0x70 = 9 - end + device pnp 2e.4 off end # Enviroment Controller device pnp 2e.5 off end # Keyboard device pnp 2e.6 off end # Mouse device pnp 2e.7 off end # GPIO - device pnp 2e.a off end # IR + device pnp 2e.a off end # CIR end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 off end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 off end # PCH SPI - device pci 1f.6 off end # GbE + end + device ref p2sb hidden end + device ref pmc hidden end + device ref hda on end + device ref smbus on end + device ref fast_spi on end end chip drivers/crb device mmio 0xfed40000 on end end + end diff --git a/src/mainboard/protectli/vault_kbl/die.c b/src/mainboard/protectli/vault_kbl/die.c new file mode 100644 index 00000000000..2e733a2bc27 --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/die.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static void beep_and_blink(void) +{ + static uint8_t blink = 0; + static uint8_t beep_count = 0;; + + gpio_set(GPP_E8, blink); + /* Beep 12 times at most, constant beeps may be annoying */ + if (beep_count < 12) { + beep(800, 300); + mdelay(200); + beep_count++; + } else { + mdelay(500); + } + + blink ^= 1; +} + +void die_notify(void) +{ + if (ENV_POSTCAR) + return; + + /* Make SATA LED blink and use PC SPKR */ + gpio_output(GPP_E8, 0); + + while (1) { + beep_and_blink(); + beep_and_blink(); + beep_and_blink(); + beep_and_blink(); + delay(2); + } +} diff --git a/src/mainboard/protectli/vault_kbl/dsdt.asl b/src/mainboard/protectli/vault_kbl/dsdt.asl index 5691f95c4fc..2e36cfced14 100644 --- a/src/mainboard/protectli/vault_kbl/dsdt.asl +++ b/src/mainboard/protectli/vault_kbl/dsdt.asl @@ -7,16 +7,14 @@ DefinitionBlock( ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, - 0x20110725 + 0x20110725 /* OEM revision */ ) { #include - #include #include #include - Device (\_SB.PCI0) - { + Device (\_SB.PCI0) { #include #include } diff --git a/src/mainboard/protectli/vault_kbl/gpio.h b/src/mainboard/protectli/vault_kbl/gpio.h index 8e59db91c2e..531dc5f5886 100644 --- a/src/mainboard/protectli/vault_kbl/gpio.h +++ b/src/mainboard/protectli/vault_kbl/gpio.h @@ -3,6 +3,7 @@ #ifndef _GPIOFW6B_H #define _GPIOFW6B_H +#include #include #ifndef __ACPI__ @@ -17,13 +18,13 @@ static const struct pad_config gpio_table[] = { /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PIRQA_N*/ PAD_CFG_TERM_GPO(GPP_A7, 1, NONE, DEEP), -/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* LPC_CLKRUN */ PAD_NC(GPP_A8, NONE), /* PCH_LPC_CLK0 */ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* PCH_LPC_CLK1 */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* PME# */ PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), /* ISH_GP6 */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PCH_SUSSTAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* PCH_SUSSTAT */ PAD_NC(GPP_A14, NONE), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), /* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN */ PAD_NC(GPP_A17, NONE), @@ -38,7 +39,7 @@ static const struct pad_config gpio_table[] = { /* VRALERT_N */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* CPU_GP2 */ PAD_NC(GPP_B3, NONE), /* CPU_GP3 */ PAD_NC(GPP_B4, NONE), -/* SRCCLKREQ0_N */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), +/* SRCCLKREQ0_N */ PAD_NC(GPP_B5, NONE), /* SRCCLKREQ1_N*/ PAD_NC(GPP_B6, NONE), /* SRCCLKREQ2_N*/ PAD_NC(GPP_B7, NONE), /* SRCCLKREQ3_N*/ PAD_NC(GPP_B8, NONE), @@ -166,7 +167,7 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# (TP7) */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7_RSVD */ PAD_CFG_TERM_GPO(GPD7, 1, NONE, DEEP), +/* GPD7_RSVD */ PAD_NC(GPD7, NONE), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SLP_WLAN# (TP6) */ PAD_NC(GPD9, NONE), /* SLP_S5# (TP3) */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), diff --git a/src/mainboard/protectli/vault_kbl/hda_verb.c b/src/mainboard/protectli/vault_kbl/hda_verb.c new file mode 100644 index 00000000000..4e89e29836c --- /dev/null +++ b/src/mainboard/protectli/vault_kbl/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Convert to macros */ + +#include + +const u32 cim_verb_data[] = { + /* --- KabyLake HDA --- */ + 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ + 0x80860101, /* Subsystem ID */ + 5, /* Number of jacks (NID entries) */ + + /* Enable the third converter and pin first */ + 0x20878101, + 0x20878101, + 0x20878101, + 0x20878101, + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), + + /* Disable the third converter and third pin */ + 0x20878100, + 0x20878100, + 0x20878100, + 0x20878100, +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/protectli/vault_kbl/ramstage.c b/src/mainboard/protectli/vault_kbl/mainboard.c similarity index 58% rename from src/mainboard/protectli/vault_kbl/ramstage.c rename to src/mainboard/protectli/vault_kbl/mainboard.c index 9518b1d721d..1658ed68b09 100644 --- a/src/mainboard/protectli/vault_kbl/ramstage.c +++ b/src/mainboard/protectli/vault_kbl/mainboard.c @@ -1,6 +1,11 @@ + /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include +#include +#include #include +#include #include "gpio.h" @@ -12,7 +17,16 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - params->TurboMode = 1; params->PchPort61hEnable = 1; - params->CdClock = 3; } + + +static void mainboard_final(void *unused) +{ + if (CONFIG(BEEP_ON_BOOT)) + beep(1500, 100); +} + +struct chip_operations mainboard_ops = { + .final = mainboard_final, +}; diff --git a/src/mainboard/protectli/vault_kbl/romstage.c b/src/mainboard/protectli/vault_kbl/romstage.c index 2b68e1aa1ee..e508a40bc32 100644 --- a/src/mainboard/protectli/vault_kbl/romstage.c +++ b/src/mainboard/protectli/vault_kbl/romstage.c @@ -5,26 +5,6 @@ #include #include -static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) -{ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, - 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); - memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); -} - -static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) -{ - const u8 dqs_map[2][8] = { - { 0, 1, 2, 3, 4, 5, 6, 7 }, - { 1, 0, 2, 3, 4, 5, 6, 7 } }; - memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); - memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); -} - static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) { const u16 RcompResistor[3] = { 121, 81, 100 }; @@ -42,10 +22,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) FSP_M_CONFIG *mem_cfg; mem_cfg = &mupd->FspmConfig; - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, - &mem_cfg->DqByteMapCh1); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, - &mem_cfg->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); @@ -55,7 +31,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) mem_cfg->DqPinsInterleaved = 1; mem_cfg->CaVrefConfig = 2; - get_spd_smbus(&blk); dump_spd_info(&blk); diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index f373bd9c8c8..cedb02853ce 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -297,6 +297,13 @@ config SOC_INTEL_CSE_HAVE_SPEC_SUPPORT common code. Enabling this option will use those CSE defined ME specification for the SoC. User should select pertinent ME spec version along with this option. +config SOC_INTEL_COMMON_BLOCK_ME_SPEC_11 + bool + select SOC_INTEL_CSE_HAVE_SPEC_SUPPORT + help + This config will enable 'ME specification version 11'. It will ensure ME specific + declaration and uses of required data structures for Host firmware status registers. + config SOC_INTEL_COMMON_BLOCK_ME_SPEC_12 bool select SOC_INTEL_CSE_HAVE_SPEC_SUPPORT @@ -336,6 +343,7 @@ if SOC_INTEL_CSE_HAVE_SPEC_SUPPORT config ME_SPEC int + default 11 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_11 default 12 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_12 default 13 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_13 default 15 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_15 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 684619b61f5..fecb3afee47 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1595,6 +1595,9 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_CNL_CSE0, PCI_DID_INTEL_LWB_CSE0, PCI_DID_INTEL_LWB_CSE0_SUPER, + PCI_DID_INTEL_SKL_CSE0, + PCI_DID_INTEL_SKL_H_CSE0, + PCI_DID_INTEL_KBL_H_CSE0, PCI_DID_INTEL_CNP_H_CSE0, PCI_DID_INTEL_CMP_CSE0, PCI_DID_INTEL_CMP_H_CSE0, diff --git a/src/soc/intel/common/block/cse/cse_spec.c b/src/soc/intel/common/block/cse/cse_spec.c index 74155cd1501..c6129e0b53a 100644 --- a/src/soc/intel/common/block/cse/cse_spec.c +++ b/src/soc/intel/common/block/cse/cse_spec.c @@ -88,6 +88,10 @@ static void dump_me_status(void *unused) hfsts1.fields.operation_mode); printk(BIOS_DEBUG, "ME: Error Code : %u\n", hfsts1.fields.error_code); +#if CONFIG_ME_SPEC == 11 + printk(BIOS_DEBUG, "ME: FPFs Committed : %s\n", + hfsts6.fields.fpf_nvars & 1 ? "YES" : "NO"); +#endif #if CONFIG_ME_SPEC >= 15 printk(BIOS_DEBUG, "ME: FPFs Committed : %s\n", hfsts6.fields.fpf_soc_lock ? "YES" : "NO"); @@ -98,8 +102,10 @@ static void dump_me_status(void *unused) #if CONFIG_ME_SPEC <= 16 printk(BIOS_DEBUG, "ME: CPU Debug Disabled : %s\n", hfsts6.fields.cpu_debug_disable ? "YES" : "NO"); +#if CONFIG_ME_SPEC >= 12 printk(BIOS_DEBUG, "ME: TXT Support : %s\n", hfsts6.fields.txt_support ? "YES" : "NO"); +#endif #else printk(BIOS_DEBUG, "ME: CPU Debug Disabled : %s\n", hfsts5.fields.cpu_debug_disabled ? "YES" : "NO"); diff --git a/src/soc/intel/common/block/include/intelblocks/me.h b/src/soc/intel/common/block/include/intelblocks/me.h index c55d147f13a..8266ae3e3e9 100644 --- a/src/soc/intel/common/block/include/intelblocks/me.h +++ b/src/soc/intel/common/block/include/intelblocks/me.h @@ -6,7 +6,9 @@ #include #if CONFIG(SOC_INTEL_CSE_HAVE_SPEC_SUPPORT) -#if CONFIG_ME_SPEC == 12 +#if CONFIG_ME_SPEC == 11 +#include "me_11.h" +#elif CONFIG_ME_SPEC == 12 #include "me_12.h" #elif CONFIG_ME_SPEC == 13 #include "me_13.h" diff --git a/src/soc/intel/common/block/include/intelblocks/me_11.h b/src/soc/intel/common/block/include/intelblocks/me_11.h new file mode 100644 index 00000000000..6b007c293b6 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/me_11.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_COMMON_ME_SPEC_11_H_ +#define _SOC_INTEL_COMMON_ME_SPEC_11_H_ + +/* ME Host Firmware Status register 1 */ +union me_hfsts1 { + uint32_t data; + struct { + uint32_t working_state : 4; + uint32_t mfg_mode : 1; + uint32_t fpt_bad : 1; + uint32_t operation_state : 3; + uint32_t fw_init_complete : 1; + uint32_t ft_bup_ld_flr : 1; + uint32_t update_in_progress : 1; + uint32_t error_code : 4; + uint32_t operation_mode : 4; + uint32_t reserved_0 : 4; + uint32_t boot_options_present : 1; + uint32_t reserved_1 : 5; + uint32_t d3_support_valid : 1; + uint32_t d0i3_support_valid : 1; + } __packed fields; +}; + +/* ME Host Firmware Status register 2 */ +union me_hfsts2 { + uint32_t data; + struct { + uint32_t reserved_0 : 4; + uint32_t cpu_replaced : 1; + uint32_t reserved_1 : 3; + uint32_t cpu_replaced_valid : 1; + uint32_t low_power_state : 1; + uint32_t reserved_2 : 6; + uint32_t current_state : 8; + uint32_t current_pmevent : 4; + uint32_t progress_code : 4; + } __packed fields; +}; + +/* ME Host Firmware Status register 3 */ +union me_hfsts3 { + uint32_t data; + struct { + uint32_t reserved_0 : 4; + uint32_t fw_sku : 3; + uint32_t encrypt_key_check : 1; + uint32_t pch_config_change : 1; + uint32_t reserved_1 : 21; + uint32_t encrypt_key_override : 1; + uint32_t power_down_mitigation : 1; + } __packed fields; +}; + +/* ME Host Firmware Status register 4 */ +union me_hfsts4 { + uint32_t data; + struct { + uint32_t reserved_0; + } __packed fields; +}; + +/* ME Host Firmware Status register 5 */ +union me_hfsts5 { + uint32_t data; + struct { + uint32_t reserved_0; + } __packed fields; +}; + +/* ME Host Firmware Status register 6 */ +union me_hfsts6 { + uint32_t data; + struct { + uint32_t reserved_0 : 1; + uint32_t cpu_debug_disable : 1; + uint32_t reserved_1 : 29; + uint32_t fpf_nvars : 2; + } __packed fields; +}; + +#endif /* _SOC_INTEL_COMMON_ME_SPEC_11_H_ */ diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d6a11363ee2..e422eaece65 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -61,6 +61,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_CONFIGURE_DDI_A_4_LANES + select SOC_INTEL_COMMON_BLOCK_ME_SPEC_11 select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index ffeb2f055ae..4d713ec112e 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -3,6 +3,8 @@ #ifndef _SKYLAKE_ME_H_ #define _SKYLAKE_ME_H_ +#include + /* * Management Engine PCI registers */ @@ -112,82 +114,6 @@ #define ME_HFS6_FPF_NOT_COMMITTED 0x0 #define ME_HFS6_FPF_ERROR 0x2 -/* ME Host Firmware Status register 1 */ -union me_hfsts1 { - uint32_t data; - struct { - uint32_t working_state : 4; - uint32_t mfg_mode : 1; - uint32_t fpt_bad : 1; - uint32_t operation_state : 3; - uint32_t fw_init_complete : 1; - uint32_t ft_bup_ld_flr : 1; - uint32_t update_in_progress : 1; - uint32_t error_code : 4; - uint32_t operation_mode : 4; - uint32_t reserved_0 : 4; - uint32_t boot_options_present : 1; - uint32_t reserved_1 : 5; - uint32_t d3_support_valid : 1; - uint32_t d0i3_support_valid : 1; - } __packed fields; -}; - -/* ME Host Firmware Status register 2 */ -union me_hfsts2 { - uint32_t data; - struct { - uint32_t reserved_0 : 4; - uint32_t cpu_replaced_sts : 1; - uint32_t reserved_1 : 3; - uint32_t cpu_replaced_valid : 1; - uint32_t low_power_state : 1; - uint32_t reserved_2 : 6; - uint32_t current_state : 8; - uint32_t current_pmevent : 4; - uint32_t progress_code : 4; - } __packed fields; -}; - -/* ME Host Firmware Status register 3 */ -union me_hfsts3 { - uint32_t data; - struct { - uint32_t reserved_0 : 4; - uint32_t fw_sku : 3; - uint32_t encrypt_key_check : 1; - uint32_t pch_config_change : 1; - uint32_t reserved_1 : 21; - uint32_t encrypt_key_override : 1; - uint32_t power_down_mitigation : 1; - } __packed fields; -}; - -/* ME Host Firmware Status register 4 */ -union me_hfsts4 { - uint32_t data; - struct { - uint32_t reserved_0; - } __packed fields; -}; - -/* ME Host Firmware Status register 5 */ -union me_hfsts5 { - uint32_t data; - struct { - uint32_t reserved_0; - } __packed fields; -}; - -/* ME Host Firmware Status register 6 */ -union me_hfsts6 { - uint32_t data; - struct { - uint32_t reserved1 : 30; - uint32_t fpf_nvars : 2; - } __packed fields; -}; - void intel_me_status(void); int send_global_reset(void); diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 89491f89c37..9b58a7ce39c 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -228,7 +228,7 @@ void intel_me_status(void) printk(BIOS_DEBUG, "ME: Low Power State Enabled : %s\n", hfs2.fields.low_power_state ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: CPU Replaced : %s\n", - hfs2.fields.cpu_replaced_sts ? "YES" : "NO"); + hfs2.fields.cpu_replaced ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: CPU Replacement Valid : %s\n", hfs2.fields.cpu_replaced_valid ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Current Working State : %s\n",