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-Wframe-larger-than in display/dc/dml/dcn20/display_rq_dlg_calc_20.c #694

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tpgxyz opened this issue Sep 24, 2019 · 4 comments
Closed

-Wframe-larger-than in display/dc/dml/dcn20/display_rq_dlg_calc_20.c #694

tpgxyz opened this issue Sep 24, 2019 · 4 comments
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-Wframe-larger-than= [ARCH] x86 This bug impacts ARCH=i386 duplicate This issue or pull request already exists low priority This bug is not critical and not a priority

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@tpgxyz
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tpgxyz commented Sep 24, 2019

Building kernel 5.3.1 with LLVM/clang-9.0.0 on i686

  CC [M]  drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.o
BUILDSTDERR: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:1563:6: warning: stack frame size of 1580 bytes in function 'dml20_rq_dlg_get_dlg_reg' [-Wframe-larger-than=]
BUILDSTDERR: void dml20_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
BUILDSTDERR:      ^
BUILDSTDERR: 1 warning generated
@nickdesaulniers nickdesaulniers added low priority This bug is not critical and not a priority -Wframe-larger-than= labels Sep 24, 2019
@tpgxyz tpgxyz added the [ARCH] x86 This bug impacts ARCH=i386 label Sep 26, 2019
@nathanchance
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Still reproducible with Linux @ https://git.kernel.org/linus/16fc44d6387e260f4932e9248b985837324705d8 and LLVM @ llvm/llvm-project@1c10201.

$ make -skj"$(nproc)" LLVM=1 LLVM_IAS=1 i386_defconfig

$ scripts/config -e DRM_AMDGPU

$ make -skj"$(nproc)" LLVM=1 LLVM_IAS=1 olddefconfig drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.o
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:1531:6: warning: stack frame size of 1276 bytes in function 'dml20_rq_dlg_get_dlg_reg' [-Wframe-larger-than=]
void dml20_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
     ^
1 warning generated.

Running the object file through frame-larger-than.py:

$ python3 ../../github/frame-larger-than/frame_larger_than.py drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.o
dml20_rq_dlg_get_dlg_reg:
	196	display_rq_params_st          	rq_param
	68	display_dlg_sys_params_st     	dlg_sys_param
dml20_rq_dlg_get_dlg_params:
	8	double                        	dppclk_freq_in_mhz
	8	double                        	refclk_freq_in_mhz
	8	double                        	pclk_freq_in_mhz
	8	double                        	ref_freq_to_pix_freq
	4	const display_pipe_dest_params_st*	dst
	4	unsigned int                  	htotal
	4	unsigned int                  	hblank_end
	4	unsigned int                  	vblank_start
	4	unsigned int                  	vblank_end
	8	double                        	min_ttu_vblank
	4	unsigned int                  	dlg_vblank_start
	1	bool                          	mode_422
	4	unsigned int                  	vp_height_l
	4	unsigned int                  	vp_width_l
	4	unsigned int                  	vp_height_c
	8	double                        	hratio_l
	8	double                        	hratio_c
	8	double                        	vratio_l
	4	unsigned int                  	meta_chunks_per_row_ub_c
	4	unsigned int                  	meta_chunks_per_row_ub_l
	4	unsigned int                  	dpte_groups_per_row_ub_c
	4	unsigned int                  	swath_width_ub_c
	4	unsigned int                  	dpte_groups_per_row_ub_l
	4	unsigned int                  	swath_width_ub_l
	8	double                        	vratio_c
	4	unsigned int                  	vp_width_c
	4	unsigned int                  	htaps_l
	4	unsigned int                  	htaps_c
	4	unsigned int                  	vupdate_offset
	4	unsigned int                  	vupdate_width
	4	unsigned int                  	vready_offset
	4	unsigned int                  	dst_x_after_scaler
	4	unsigned int                  	dst_y_after_scaler
	8	double                        	line_wait
	8	double                        	dst_y_prefetch
	8	double                        	dst_y_per_vm_vblank
	8	double                        	dst_y_per_row_vblank
	8	double                        	dst_y_per_vm_flip
	8	double                        	min_dst_y_per_row_vblank
	8	double                        	min_dst_y_per_vm_vblank
	8	double                        	dst_y_per_row_flip
	8	double                        	vratio_pre_l
	8	double                        	vratio_pre_c
	8	double                        	min_hratio_fact_c
	8	double                        	min_hratio_fact_l
	8	double                        	hscale_pixel_rate_c
	8	double                        	hscale_pixel_rate_l
	4	unsigned int                  	dpte_row_height_c
	4	unsigned int                  	dpte_row_height_l
	4	unsigned int                  	scaler_rec_in_width_c
	4	unsigned int                  	scaler_rec_in_width_l
	4	unsigned int                  	swath_width_pixels_ub_c
	4	unsigned int                  	swath_width_pixels_ub_l
	4	unsigned int                  	meta_row_height_c
	4	unsigned int                  	meta_row_height_l
	4	unsigned int                  	req_per_swath_ub_c
	4	unsigned int                  	req_per_swath_ub_l
	4	unsigned int                  	full_recout_width
	8	double                        	refcyc_per_req_delivery_c
	8	double                        	refcyc_per_req_delivery_l
	8	double                        	refcyc_per_req_delivery_pre_c
	8	double                        	refcyc_per_req_delivery_pre_l
	8	double                        	refcyc_per_line_delivery_c
	8	double                        	refcyc_per_line_delivery_l
	8	double                        	refcyc_per_line_delivery_pre_c
	8	double                        	refcyc_per_line_delivery_pre_l
	8	double                        	refcyc_per_req_delivery_pre_cur0
	8	double                        	refcyc_per_req_delivery_cur0
	8	double                        	refcyc_per_req_delivery_pre_cur1
	8	double                        	refcyc_per_req_delivery_cur1
	4	const display_pipe_source_params_st*	src
	4	const display_output_params_st*	dout
	4	const display_clocks_and_cfg_st*	clks
	4	const scaler_ratio_depth_st*  	scl
	4	const scaler_taps_st*         	taps
	4	unsigned int                  	min_vblank
	8	double                        	dispclk_freq_in_mhz
	1	bool                          	interlaced
	8	double                        	min_dcfclk_mhz
	8	double                        	t_calc_us
	8	double                        	min_dst_y_ttu_vblank
	1	bool                          	dual_plane
	4	unsigned int                  	access_dir
	1	bool                          	scl_enable
	8	double                        	line_time_in_us
	4	unsigned int                  	dppclk_delay_subtotal
	4	unsigned int                  	dispclk_delay_subtotal
	4	unsigned int                  	pixel_rate_delay_subtotal
	4	unsigned int                  	vstartup_start
	8	double                        	lsw
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	8	double                        	dsc_delay
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	4	int                           	__ret_warn_on
	8	double                        	dppclk_freq_in_mhz
	8	double                        	refclk_freq_in_mhz
	8	double                        	pclk_freq_in_mhz
	8	double                        	ref_freq_to_pix_freq
	4	const display_pipe_dest_params_st*	dst
	4	unsigned int                  	htotal
	4	unsigned int                  	hblank_end
	4	unsigned int                  	vblank_start
	4	unsigned int                  	vblank_end
	8	double                        	min_ttu_vblank
	4	unsigned int                  	dlg_vblank_start
	1	bool                          	mode_422
	4	unsigned int                  	vp_height_l
	4	unsigned int                  	vp_width_l
	4	unsigned int                  	vp_height_c
	8	double                        	hratio_l
	8	double                        	hratio_c
	8	double                        	vratio_l
	4	unsigned int                  	meta_chunks_per_row_ub_c
	4	unsigned int                  	meta_chunks_per_row_ub_l
	4	unsigned int                  	dpte_groups_per_row_ub_c
	4	unsigned int                  	swath_width_ub_c
	4	unsigned int                  	dpte_groups_per_row_ub_l
	4	unsigned int                  	swath_width_ub_l
	8	double                        	vratio_c
	4	unsigned int                  	vp_width_c
	4	unsigned int                  	htaps_l
	4	unsigned int                  	htaps_c
	4	unsigned int                  	vupdate_offset
	4	unsigned int                  	vupdate_width
	4	unsigned int                  	vready_offset
	4	unsigned int                  	dst_x_after_scaler
	4	unsigned int                  	dst_y_after_scaler
	8	double                        	line_wait
	8	double                        	dst_y_prefetch
	8	double                        	dst_y_per_vm_vblank
	8	double                        	dst_y_per_row_vblank
	8	double                        	dst_y_per_vm_flip
	8	double                        	min_dst_y_per_row_vblank
	8	double                        	min_dst_y_per_vm_vblank
	8	double                        	dst_y_per_row_flip
	8	double                        	vratio_pre_l
	8	double                        	vratio_pre_c
	8	double                        	min_hratio_fact_c
	8	double                        	min_hratio_fact_l
	8	double                        	hscale_pixel_rate_c
	8	double                        	hscale_pixel_rate_l
	4	unsigned int                  	dpte_row_height_c
	4	unsigned int                  	dpte_row_height_l
	4	unsigned int                  	scaler_rec_in_width_c
	4	unsigned int                  	scaler_rec_in_width_l
	4	unsigned int                  	swath_width_pixels_ub_c
	4	unsigned int                  	swath_width_pixels_ub_l
	4	unsigned int                  	meta_row_height_c
	4	unsigned int                  	meta_row_height_l
	4	unsigned int                  	req_per_swath_ub_c
	4	unsigned int                  	req_per_swath_ub_l
	4	unsigned int                  	full_recout_width
	8	double                        	refcyc_per_req_delivery_c
	8	double                        	refcyc_per_req_delivery_l
	8	double                        	refcyc_per_req_delivery_pre_c
	8	double                        	refcyc_per_req_delivery_pre_l
	8	double                        	refcyc_per_line_delivery_c
	8	double                        	refcyc_per_line_delivery_l
	8	double                        	refcyc_per_line_delivery_pre_c
	8	double                        	refcyc_per_line_delivery_pre_l
	8	double                        	refcyc_per_req_delivery_pre_cur0
	8	double                        	refcyc_per_req_delivery_cur0
	8	double                        	refcyc_per_req_delivery_pre_cur1
	8	double                        	refcyc_per_req_delivery_cur1
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_max:
dml_max:
get_refcyc_per_delivery:
	8	double                        	refcyc_per_delivery
	8	double                        	refcyc_per_delivery
dml_min:
get_refcyc_per_delivery:
	8	double                        	refcyc_per_delivery
	8	double                        	refcyc_per_delivery
dml_min:
is_dual_plane:
	1	bool                          	ret_val
get_refcyc_per_delivery:
	8	double                        	refcyc_per_delivery
	8	double                        	refcyc_per_delivery
dml_min:
get_refcyc_per_delivery:
	8	double                        	refcyc_per_delivery
	8	double                        	refcyc_per_delivery
dml_min:
get_refcyc_per_delivery:
	8	double                        	refcyc_per_delivery
	8	double                        	refcyc_per_delivery
dml_min:
get_refcyc_per_delivery:
	8	double                        	refcyc_per_delivery
	8	double                        	refcyc_per_delivery
dml_min:
dml_pow:
dml_pow:
get_refcyc_per_delivery:
	8	double                        	refcyc_per_delivery
	8	double                        	refcyc_per_delivery
dml_min:
get_refcyc_per_delivery:
	8	double                        	refcyc_per_delivery
	8	double                        	refcyc_per_delivery
dml_min:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_floor:
dml_floor:
dml_pow:
dml_pow:
dml_floor:
dml_floor:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:
dml_pow:

@nickdesaulniers
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6f6cb17 needs to be reverted to reproduce this now, but I observe the issue still in clang-18 (after llvm/llvm-project@e698695).

drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:1549:6: error: stack frame size (1340) exceeds limit (1024) in 'dml20_rq_dlg_get_dlg_reg' [-Werror,-Wframe-larger-than]
 1549 | void dml20_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
      |      ^

adding KCFLAGS=-Rpass-analysis=stack-frame-layout to the make invocation and debug info configured on:

drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:1560:1: remark: 
Function: dml20_rq_dlg_get_dlg_reg
Offset: [SP+32], Type: Variable, Align: 4, Size: 1
Offset: [SP+28], Type: Variable, Align: 4, Size: 1
Offset: [SP+24], Type: Variable, Align: 4, Size: 1
Offset: [SP+20], Type: Variable, Align: 4, Size: 1
Offset: [SP+16], Type: Variable, Align: 4, Size: 1
Offset: [SP+12], Type: Variable, Align: 4, Size: 4
Offset: [SP+8], Type: Variable, Align: 4, Size: 4
Offset: [SP+4], Type: Variable, Align: 4, Size: 4
Offset: [SP-4], Type: Spill, Align: 4, Size: 4
Offset: [SP-8], Type: Spill, Align: 4, Size: 4
Offset: [SP-12], Type: Spill, Align: 4, Size: 4
Offset: [SP-16], Type: Spill, Align: 4, Size: 4
Offset: [SP-20], Type: Protector, Align: 4, Size: 4
    dlg_sys_param @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:1562
Offset: [SP-28], Type: Variable, Align: 8, Size: 8
Offset: [SP-36], Type: Variable, Align: 8, Size: 8
Offset: [SP-44], Type: Variable, Align: 8, Size: 8
Offset: [SP-52], Type: Variable, Align: 8, Size: 8
Offset: [SP-248], Type: Variable, Align: 4, Size: 196
    rq_param @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:1561
Offset: [SP-308], Type: Variable, Align: 8, Size: 60
Offset: [SP-332], Type: Spill, Align: 16, Size: 16
    dst_y_per_vm_flip @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:879
Offset: [SP-348], Type: Spill, Align: 16, Size: 16
    dst_y_per_row_flip @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:880
Offset: [SP-364], Type: Spill, Align: 16, Size: 16
    dst_y_prefetch @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:876
Offset: [SP-372], Type: Variable, Align: 8, Size: 8
Offset: [SP-380], Type: Variable, Align: 8, Size: 8
Offset: [SP-388], Type: Variable, Align: 8, Size: 8
Offset: [SP-396], Type: Variable, Align: 8, Size: 8
Offset: [SP-404], Type: Variable, Align: 8, Size: 8
Offset: [SP-412], Type: Variable, Align: 8, Size: 8
Offset: [SP-420], Type: Variable, Align: 8, Size: 8
Offset: [SP-428], Type: Variable, Align: 8, Size: 8
Offset: [SP-436], Type: Variable, Align: 8, Size: 8
Offset: [SP-444], Type: Variable, Align: 8, Size: 8
Offset: [SP-452], Type: Variable, Align: 8, Size: 8
Offset: [SP-460], Type: Variable, Align: 8, Size: 8
Offset: [SP-468], Type: Variable, Align: 8, Size: 8
Offset: [SP-476], Type: Variable, Align: 8, Size: 8
Offset: [SP-484], Type: Variable, Align: 8, Size: 8
Offset: [SP-492], Type: Variable, Align: 8, Size: 8
Offset: [SP-500], Type: Variable, Align: 8, Size: 8
Offset: [SP-508], Type: Variable, Align: 8, Size: 8
Offset: [SP-516], Type: Variable, Align: 8, Size: 8
Offset: [SP-524], Type: Variable, Align: 8, Size: 8
Offset: [SP-532], Type: Variable, Align: 8, Size: 8
Offset: [SP-540], Type: Variable, Align: 8, Size: 8
Offset: [SP-548], Type: Variable, Align: 8, Size: 8
Offset: [SP-556], Type: Variable, Align: 8, Size: 8
Offset: [SP-564], Type: Variable, Align: 8, Size: 8
Offset: [SP-572], Type: Variable, Align: 8, Size: 8
Offset: [SP-580], Type: Variable, Align: 8, Size: 8
Offset: [SP-588], Type: Variable, Align: 8, Size: 8
Offset: [SP-596], Type: Variable, Align: 8, Size: 8
Offset: [SP-604], Type: Variable, Align: 8, Size: 8
Offset: [SP-612], Type: Variable, Align: 8, Size: 8
Offset: [SP-620], Type: Variable, Align: 8, Size: 8
Offset: [SP-628], Type: Variable, Align: 8, Size: 8
Offset: [SP-636], Type: Variable, Align: 8, Size: 8
Offset: [SP-644], Type: Variable, Align: 8, Size: 8
Offset: [SP-652], Type: Variable, Align: 8, Size: 8
Offset: [SP-660], Type: Variable, Align: 8, Size: 8
Offset: [SP-668], Type: Variable, Align: 8, Size: 8
Offset: [SP-676], Type: Variable, Align: 8, Size: 8
Offset: [SP-684], Type: Variable, Align: 8, Size: 8
Offset: [SP-692], Type: Variable, Align: 8, Size: 8
Offset: [SP-700], Type: Variable, Align: 8, Size: 8
Offset: [SP-708], Type: Variable, Align: 8, Size: 8
Offset: [SP-716], Type: Variable, Align: 8, Size: 8
Offset: [SP-724], Type: Variable, Align: 8, Size: 8
Offset: [SP-732], Type: Variable, Align: 8, Size: 8
Offset: [SP-740], Type: Variable, Align: 8, Size: 8
Offset: [SP-748], Type: Variable, Align: 8, Size: 8
Offset: [SP-756], Type: Variable, Align: 8, Size: 8
Offset: [SP-764], Type: Variable, Align: 8, Size: 8
Offset: [SP-772], Type: Spill, Align: 8, Size: 8
    min_ttu_vblank @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:823
Offset: [SP-796], Type: Spill, Align: 16, Size: 16
    vp_width_l @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:831
    refcyc_per_delivery @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:129
    hscale_pixel_rate @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:125
    vratio @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:124
    pclk_freq_in_mhz @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:120
    refclk_freq_in_mhz @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:119
    mode_lib @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:118
    refcyc_per_req_delivery_pre_l @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:905
Offset: [SP-812], Type: Spill, Align: 16, Size: 16
    htaps_l @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:836
    vratio_pre_c @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:885
Offset: [SP-828], Type: Spill, Align: 16, Size: 16
    dst_y_per_vm_vblank @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:877
Offset: [SP-844], Type: Spill, Align: 16, Size: 16
    vp_height_l @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:830
    hscale_pixel_rate @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:125
    vratio @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:124
    pclk_freq_in_mhz @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:120
    refclk_freq_in_mhz @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:119
    mode_lib @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:118
    refcyc_per_delivery @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:129
Offset: [SP-860], Type: Spill, Align: 16, Size: 16
    hratio_l @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:838
    refcyc_per_line_delivery_pre_c @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:901
Offset: [SP-864], Type: Variable, Align: 4, Size: 4
Offset: [SP-868], Type: Variable, Align: 4, Size: 4
Offset: [SP-872], Type: Variable, Align: 4, Size: 4
Offset: [SP-876], Type: Variable, Align: 4, Size: 4
Offset: [SP-880], Type: Variable, Align: 4, Size: 4
Offset: [SP-884], Type: Variable, Align: 4, Size: 4
Offset: [SP-888], Type: Variable, Align: 4, Size: 4
Offset: [SP-892], Type: Variable, Align: 4, Size: 4
Offset: [SP-896], Type: Variable, Align: 4, Size: 4
Offset: [SP-900], Type: Variable, Align: 4, Size: 4
Offset: [SP-904], Type: Variable, Align: 4, Size: 4
Offset: [SP-908], Type: Variable, Align: 4, Size: 4
Offset: [SP-912], Type: Variable, Align: 4, Size: 4
Offset: [SP-916], Type: Variable, Align: 4, Size: 4
Offset: [SP-920], Type: Variable, Align: 4, Size: 4
Offset: [SP-924], Type: Variable, Align: 4, Size: 4
Offset: [SP-928], Type: Variable, Align: 4, Size: 4
Offset: [SP-932], Type: Variable, Align: 4, Size: 4
Offset: [SP-936], Type: Variable, Align: 4, Size: 4
Offset: [SP-940], Type: Variable, Align: 4, Size: 4
Offset: [SP-944], Type: Variable, Align: 4, Size: 4
Offset: [SP-948], Type: Spill, Align: 4, Size: 4
Offset: [SP-952], Type: Spill, Align: 4, Size: 4
    meta_row_height_l @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:888
Offset: [SP-956], Type: Spill, Align: 4, Size: 4
    dpte_row_height_c @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:895
Offset: [SP-960], Type: Spill, Align: 4, Size: 4
    dpte_row_height_l @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:894
Offset: [SP-964], Type: Spill, Align: 4, Size: 4
    meta_row_height_c @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:889
Offset: [SP-968], Type: Spill, Align: 4, Size: 4
    req_per_swath_ub_c @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:887
Offset: [SP-980], Type: Spill, Align: 8, Size: 8
Offset: [SP-988], Type: Spill, Align: 8, Size: 8
Offset: [SP-1004], Type: Spill, Align: 16, Size: 16
Offset: [SP-1020], Type: Spill, Align: 16, Size: 16
    refcyc_per_delivery @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:129
Offset: [SP-1036], Type: Spill, Align: 16, Size: 16
    dst_x_after_scaler @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:873
Offset: [SP-1052], Type: Spill, Align: 16, Size: 16
Offset: [SP-1068], Type: Spill, Align: 16, Size: 16
    dppclk_freq_in_mhz @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:813
    hscale_pixel_rate_c @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:897
Offset: [SP-1084], Type: Spill, Align: 16, Size: 16
    hblank_end @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:808
    vratio_pre_l @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:884
Offset: [SP-1100], Type: Spill, Align: 16, Size: 16
    htotal @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:806
    refcyc_per_delivery @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:129
    refcyc_per_line_delivery_l @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:902
Offset: [SP-1116], Type: Spill, Align: 16, Size: 16
    hratio_c @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:839
    min_hratio_fact_c @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:899
    refcyc_per_line_delivery_c @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:903
Offset: [SP-1120], Type: Spill, Align: 4, Size: 4
    ttu_regs @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:1551
Offset: [SP-1124], Type: Spill, Align: 4, Size: 4
    dpte_groups_per_row_ub_l @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:853
Offset: [SP-1128], Type: Spill, Align: 4, Size: 4
    dpte_groups_per_row_ub_c @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:860
Offset: [SP-1132], Type: Spill, Align: 4, Size: 4
    meta_chunks_per_row_ub_c @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:863
Offset: [SP-1136], Type: Spill, Align: 4, Size: 4
Offset: [SP-1148], Type: Spill, Align: 8, Size: 8
    vratio_c @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:841
Offset: [SP-1164], Type: Spill, Align: 16, Size: 16
    refclk_freq_in_mhz @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:815
Offset: [SP-1180], Type: Spill, Align: 16, Size: 16
    vblank_end @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:810
    dst_y_per_row_vblank @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:878
Offset: [SP-1196], Type: Spill, Align: 16, Size: 16
    vratio_l @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:840
Offset: [SP-1212], Type: Spill, Align: 16, Size: 16
    swath_width_ub_l @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:851
    refcyc_per_line_delivery_pre_l @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:900
Offset: [SP-1216], Type: Spill, Align: 4, Size: 4
    vp_width_c @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:833
Offset: [SP-1228], Type: Spill, Align: 8, Size: 8
    htaps_c @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:837
    hscale_pixel_rate_l @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:896
    mode_lib @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:118
    refclk_freq_in_mhz @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:119
    pclk_freq_in_mhz @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:120
    vratio @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:124
    hscale_pixel_rate @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:125
Offset: [SP-1236], Type: Spill, Align: 8, Size: 8
    swath_width_ub_c @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:858
Offset: [SP-1260], Type: Spill, Align: 16, Size: 16
    pclk_freq_in_mhz @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:816
Offset: [SP-1264], Type: Spill, Align: 4, Size: 4
    vp_height_c @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:832
    refcyc_per_req_delivery_c @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:908
    refcyc_per_req_delivery_pre_c @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:906
    dst_y_after_scaler @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:874
Offset: [SP-1268], Type: Spill, Align: 4, Size: 4
    full_recout_width @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:910
Offset: [SP-1292], Type: Spill, Align: 16, Size: 16
    ref_freq_to_pix_freq @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:819
Offset: [SP-1308], Type: Spill, Align: 16, Size: 16
    vblank_start @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:809
    source_format @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:108
    hscale_pixel_rate @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:125
    vratio @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:124
    pclk_freq_in_mhz @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:120
    refclk_freq_in_mhz @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:119
    mode_lib @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:118
Offset: [SP-1324], Type: Spill, Align: 16, Size: 16
    refcyc_per_delivery @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:129
Offset: [SP-1328], Type: Spill, Align: 4, Size: 4
    dlg_regs @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:1550
Offset: [SP-1332], Type: Spill, Align: 4, Size: 4
    mode_lib @ drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.c:1549 [-Rpass-analysis=stack-frame-layout]
 1560 | {
      | ^

it's neat to observe some spill slots being re-used by different variables (IIUC). What's less cool is that a few variable slots have no info what's in them.

@nickdesaulniers
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Very strange, looking at the optimized IR, I only see 6 allocas in @dml20_rq_dlg_get_dlg_reg:

  • 4 doubles
  • 2 larger structs

Something seems very wrong for that to blow up into so many stack slots...

This was referenced Aug 17, 2023
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@nickdesaulniers
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duplicating this to #39. Once the two issues identified by #39 (comment) are fixed in clang, we can reopen this if necessary.

@nickdesaulniers nickdesaulniers added duplicate This issue or pull request already exists [ARCH] x86 This bug impacts ARCH=i386 -Wframe-larger-than= low priority This bug is not critical and not a priority and removed low priority This bug is not critical and not a priority [ARCH] x86 This bug impacts ARCH=i386 -Wframe-larger-than= labels Oct 13, 2023
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-Wframe-larger-than= [ARCH] x86 This bug impacts ARCH=i386 duplicate This issue or pull request already exists low priority This bug is not critical and not a priority
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