-
Notifications
You must be signed in to change notification settings - Fork 5
/
Copy pathtechnology.cc
1684 lines (1594 loc) · 70.1 KB
/
technology.cc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*------------------------------------------------------------
* CACTI 6.5
* Copyright 2008 Hewlett-Packard Development Corporation
* All Rights Reserved
*
* Permission to use, copy, and modify this software and its documentation is
* hereby granted only under the following terms and conditions. Both the
* above copyright notice and this permission notice must appear in all copies
* of the software, derivative works or modified versions, and any portions
* thereof, and both notices must appear in supporting documentation.
*
* Users of this software agree to the terms and conditions set forth herein, and
* hereby grant back to Hewlett-Packard Company and its affiliated companies ("HP")
* a non-exclusive, unrestricted, royalty-free right and license under any changes,
* enhancements or extensions made to the core functions of the software, including
* but not limited to those affording compatibility with other hardware or software
* environments, but excluding applications which incorporate this software.
* Users further agree to use their best efforts to return to HP any such changes,
* enhancements or extensions that they make and inform HP of noteworthy uses of
* this software. Correspondence should be provided to HP at:
*
* Director of Intellectual Property Licensing
* Office of Strategy and Technology
* Hewlett-Packard Company
* 1501 Page Mill Road
* Palo Alto, California 94304
*
* This software may be distributed (but not offered for sale or transferred
* for compensation) to third parties, provided such third parties agree to
* abide by the terms and conditions of this notice.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND HP DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL HP
* CORPORATION BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS
* ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
* SOFTWARE.
*------------------------------------------------------------*/
#include "basic_circuit.h"
#include "parameter.h"
double wire_resistance(double resistivity, double wire_width, double wire_thickness,
double barrier_thickness, double dishing_thickness, double alpha_scatter)
{
double resistance;
resistance = alpha_scatter * resistivity /((wire_thickness - barrier_thickness - dishing_thickness)*(wire_width - 2 * barrier_thickness));
return(resistance);
}
double wire_capacitance(double wire_width, double wire_thickness, double wire_spacing,
double ild_thickness, double miller_value, double horiz_dielectric_constant,
double vert_dielectric_constant, double fringe_cap)
{
double vertical_cap, sidewall_cap, total_cap;
vertical_cap = 2 * PERMITTIVITY_FREE_SPACE * vert_dielectric_constant * wire_width / ild_thickness;
sidewall_cap = 2 * PERMITTIVITY_FREE_SPACE * miller_value * horiz_dielectric_constant * wire_thickness / wire_spacing;
total_cap = vertical_cap + sidewall_cap + fringe_cap;
return(total_cap);
}
void init_tech_params(double technology, bool is_tag)
{
int iter, tech, tech_lo, tech_hi;
double curr_alpha, curr_vpp;
double aspect_ratio, wire_width, wire_thickness, wire_spacing, barrier_thickness, dishing_thickness,
alpha_scatter, ild_thickness, miller_value = 1.5, horiz_dielectric_constant, vert_dielectric_constant,
fringe_cap, pmos_to_nmos_sizing_r;
double curr_vdd_dram_cell, curr_v_th_dram_access_transistor, curr_I_on_dram_cell, curr_c_dram_cell;
uint32_t ram_cell_tech_type = (is_tag) ? g_ip->tag_arr_ram_cell_tech_type : g_ip->data_arr_ram_cell_tech_type;
uint32_t peri_global_tech_type = (is_tag) ? g_ip->tag_arr_peri_global_tech_type : g_ip->data_arr_peri_global_tech_type;
technology = technology * 1000.0; // in the unit of nm
// initialize parameters
g_tp.reset();
double gmp_to_gmn_multiplier_periph_global = 0;
double curr_Wmemcella_dram, curr_Wmemcellpmos_dram, curr_Wmemcellnmos_dram,
curr_area_cell_dram, curr_asp_ratio_cell_dram, curr_Wmemcella_sram,
curr_Wmemcellpmos_sram, curr_Wmemcellnmos_sram, curr_area_cell_sram,
curr_asp_ratio_cell_sram, curr_I_off_dram_cell_worst_case_length_temp;
double SENSE_AMP_D, SENSE_AMP_P; // J
double area_cell_dram = 0;
double asp_ratio_cell_dram = 0;
double area_cell_sram = 0;
double asp_ratio_cell_sram = 0;
double mobility_eff_periph_global = 0;
double Vdsat_periph_global = 0;
double nmos_effective_resistance_multiplier;
double width_dram_access_transistor;
if (technology < 91 && technology > 89)
{
tech_lo = 90;
tech_hi = 90;
}
else if (technology < 66 && technology > 64)
{
tech_lo = 65;
tech_hi = 65;
}
else if (technology < 46 && technology > 44)
{
tech_lo = 45;
tech_hi = 45;
}
else if (technology < 33 && technology > 31)
{
tech_lo = 32;
tech_hi = 32;
}
else if (technology < 90 && technology > 65)
{
tech_lo = 90;
tech_hi = 65;
}
else if (technology < 65 && technology > 45)
{
tech_lo = 65;
tech_hi = 45;
}
else if (technology < 45 && technology > 32)
{
tech_lo = 45;
tech_hi = 32;
}
double vdd[NUMBER_TECH_FLAVORS];
double Lphy[NUMBER_TECH_FLAVORS];
double Lelec[NUMBER_TECH_FLAVORS];
double t_ox[NUMBER_TECH_FLAVORS];
double v_th[NUMBER_TECH_FLAVORS];
double c_ox[NUMBER_TECH_FLAVORS];
double mobility_eff[NUMBER_TECH_FLAVORS];
double Vdsat[NUMBER_TECH_FLAVORS];
double c_g_ideal[NUMBER_TECH_FLAVORS];
double c_fringe[NUMBER_TECH_FLAVORS];
double c_junc[NUMBER_TECH_FLAVORS];
double I_on_n[NUMBER_TECH_FLAVORS];
double I_on_p[NUMBER_TECH_FLAVORS];
double Rnchannelon[NUMBER_TECH_FLAVORS];
double Rpchannelon[NUMBER_TECH_FLAVORS];
double n_to_p_eff_curr_drv_ratio[NUMBER_TECH_FLAVORS];
double I_off_n[NUMBER_TECH_FLAVORS][101];
//double I_off_p[NUMBER_TECH_FLAVORS][101];
double gmp_to_gmn_multiplier[NUMBER_TECH_FLAVORS];
for (iter = 0; iter <= 1; ++iter)
{
// linear interpolation
if (iter == 0)
{
tech = tech_lo;
if (tech_lo == tech_hi)
{
curr_alpha = 1;
}
else
{
curr_alpha = (technology - tech_hi)/(tech_lo - tech_hi);
}
}
else
{
tech = tech_hi;
if (tech_lo == tech_hi)
{
break;
}
else
{
curr_alpha = (tech_lo - technology)/(tech_lo - tech_hi);
}
}
if (tech == 90)
{
SENSE_AMP_D = .28e-9; // s
SENSE_AMP_P = 14.7e-15; // J
//90nm technology-node. Corresponds to year 2004 in ITRS
//ITRS HP device type
vdd[0] = 1.2;
Lphy[0] = 0.037;//Lphy is the physical gate-length. micron
Lelec[0] = 0.0266;//Lelec is the electrical gate-length. micron
t_ox[0] = 1.2e-3;//micron
v_th[0] = 0.23707;//V
c_ox[0] = 1.79e-14;//F/micron2
mobility_eff[0] = 342.16 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs
Vdsat[0] = 0.128; //V
c_g_ideal[0] = 6.64e-16;//F/micron
c_fringe[0] = 0.08e-15;//F/micron
c_junc[0] = 1e-15;//F/micron2
I_on_n[0] = 1076.9e-6;//A/micron
I_on_p[0] = 712.6e-6;//A/micron
//Note that nmos_effective_resistance_multiplier, n_to_p_eff_curr_drv_ratio and gmp_to_gmn_multiplier values are calculated offline
nmos_effective_resistance_multiplier = 1.54;
n_to_p_eff_curr_drv_ratio[0] = 2.45;
gmp_to_gmn_multiplier[0] = 1.22;
Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];//ohm-micron
Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];//ohm-micron
I_off_n[0][0] = 3.24e-8;//A/micron
I_off_n[0][10] = 4.01e-8;
I_off_n[0][20] = 4.90e-8;
I_off_n[0][30] = 5.92e-8;
I_off_n[0][40] = 7.08e-8;
I_off_n[0][50] = 8.38e-8;
I_off_n[0][60] = 9.82e-8;
I_off_n[0][70] = 1.14e-7;
I_off_n[0][80] = 1.29e-7;
I_off_n[0][90] = 1.43e-7;
I_off_n[0][100] = 1.54e-7;
//ITRS LSTP device type
vdd[1] = 1.3;
Lphy[1] = 0.075;
Lelec[1] = 0.0486;
t_ox[1] = 2.2e-3;
v_th[1] = 0.48203;
c_ox[1] = 1.22e-14;
mobility_eff[1] = 356.76 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[1] = 0.373;
c_g_ideal[1] = 9.15e-16;
c_fringe[1] = 0.08e-15;
c_junc[1] = 1e-15;
I_on_n[1] = 503.6e-6;
I_on_p[1] = 235.1e-6;
nmos_effective_resistance_multiplier = 1.92;
n_to_p_eff_curr_drv_ratio[1] = 2.44;
gmp_to_gmn_multiplier[1] =0.88;
Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1];
Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1];
I_off_n[1][0] = 2.81e-12;
I_off_n[1][10] = 4.76e-12;
I_off_n[1][20] = 7.82e-12;
I_off_n[1][30] = 1.25e-11;
I_off_n[1][40] = 1.94e-11;
I_off_n[1][50] = 2.94e-11;
I_off_n[1][60] = 4.36e-11;
I_off_n[1][70] = 6.32e-11;
I_off_n[1][80] = 8.95e-11;
I_off_n[1][90] = 1.25e-10;
I_off_n[1][100] = 1.7e-10;
//ITRS LOP device type
vdd[2] = 0.9;
Lphy[2] = 0.053;
Lelec[2] = 0.0354;
t_ox[2] = 1.5e-3;
v_th[2] = 0.30764;
c_ox[2] = 1.59e-14;
mobility_eff[2] = 460.39 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[2] = 0.113;
c_g_ideal[2] = 8.45e-16;
c_fringe[2] = 0.08e-15;
c_junc[2] = 1e-15;
I_on_n[2] = 386.6e-6;
I_on_p[2] = 209.7e-6;
nmos_effective_resistance_multiplier = 1.77;
n_to_p_eff_curr_drv_ratio[2] = 2.54;
gmp_to_gmn_multiplier[2] = 0.98;
Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2];
Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2];
I_off_n[2][0] = 2.14e-9;
I_off_n[2][10] = 2.9e-9;
I_off_n[2][20] = 3.87e-9;
I_off_n[2][30] = 5.07e-9;
I_off_n[2][40] = 6.54e-9;
I_off_n[2][50] = 8.27e-8;
I_off_n[2][60] = 1.02e-7;
I_off_n[2][70] = 1.20e-7;
I_off_n[2][80] = 1.36e-8;
I_off_n[2][90] = 1.52e-8;
I_off_n[2][100] = 1.73e-8;
if (ram_cell_tech_type == lp_dram)
{
//LP-DRAM cell access transistor technology parameters
curr_vdd_dram_cell = 1.2;
Lphy[3] = 0.12;
Lelec[3] = 0.0756;
curr_v_th_dram_access_transistor = 0.4545;
width_dram_access_transistor = 0.14;
curr_I_on_dram_cell = 45e-6;
curr_I_off_dram_cell_worst_case_length_temp = 21.1e-12;
curr_Wmemcella_dram = width_dram_access_transistor;
curr_Wmemcellpmos_dram = 0;
curr_Wmemcellnmos_dram = 0;
curr_area_cell_dram = 0.168;
curr_asp_ratio_cell_dram = 1.46;
curr_c_dram_cell = 20e-15;
//LP-DRAM wordline transistor parameters
curr_vpp = 1.6;
t_ox[3] = 2.2e-3;
v_th[3] = 0.4545;
c_ox[3] = 1.22e-14;
mobility_eff[3] = 323.95 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[3] = 0.3;
c_g_ideal[3] = 1.47e-15;
c_fringe[3] = 0.08e-15;
c_junc[3] = 1e-15;
I_on_n[3] = 321.6e-6;
I_on_p[3] = 203.3e-6;
nmos_effective_resistance_multiplier = 1.65;
n_to_p_eff_curr_drv_ratio[3] = 1.95;
gmp_to_gmn_multiplier[3] = 0.90;
Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];
Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];
I_off_n[3][0] = 1.42e-11;
I_off_n[3][10] = 2.25e-11;
I_off_n[3][20] = 3.46e-11;
I_off_n[3][30] = 5.18e-11;
I_off_n[3][40] = 7.58e-11;
I_off_n[3][50] = 1.08e-10;
I_off_n[3][60] = 1.51e-10;
I_off_n[3][70] = 2.02e-10;
I_off_n[3][80] = 2.57e-10;
I_off_n[3][90] = 3.14e-10;
I_off_n[3][100] = 3.85e-10;
}
else if (ram_cell_tech_type == comm_dram)
{
//COMM-DRAM cell access transistor technology parameters
curr_vdd_dram_cell = 1.6;
Lphy[3] = 0.09;
Lelec[3] = 0.0576;
curr_v_th_dram_access_transistor = 1;
width_dram_access_transistor = 0.09;
curr_I_on_dram_cell = 20e-6;
curr_I_off_dram_cell_worst_case_length_temp = 1e-15;
curr_Wmemcella_dram = width_dram_access_transistor;
curr_Wmemcellpmos_dram = 0;
curr_Wmemcellnmos_dram = 0;
curr_area_cell_dram = 6*0.09*0.09;
curr_asp_ratio_cell_dram = 1.5;
curr_c_dram_cell = 30e-15;
//COMM-DRAM wordline transistor parameters
curr_vpp = 3.7;
t_ox[3] = 5.5e-3;
v_th[3] = 1.0;
c_ox[3] = 5.65e-15;
mobility_eff[3] = 302.2 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[3] = 0.32;
c_g_ideal[3] = 5.08e-16;
c_fringe[3] = 0.08e-15;
c_junc[3] = 1e-15;
I_on_n[3] = 1094.3e-6;
I_on_p[3] = I_on_n[3] / 2;
nmos_effective_resistance_multiplier = 1.62;
n_to_p_eff_curr_drv_ratio[3] = 2.05;
gmp_to_gmn_multiplier[3] = 0.90;
Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];
Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];
I_off_n[3][0] = 5.80e-15;
I_off_n[3][10] = 1.21e-14;
I_off_n[3][20] = 2.42e-14;
I_off_n[3][30] = 4.65e-14;
I_off_n[3][40] = 8.60e-14;
I_off_n[3][50] = 1.54e-13;
I_off_n[3][60] = 2.66e-13;
I_off_n[3][70] = 4.45e-13;
I_off_n[3][80] = 7.17e-13;
I_off_n[3][90] = 1.11e-12;
I_off_n[3][100] = 1.67e-12;
}
//SRAM cell properties
curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um;
curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um;
curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um;
curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um;
curr_asp_ratio_cell_sram = 1.46;
}
if (tech == 65)
{ //65nm technology-node. Corresponds to year 2007 in ITRS
//ITRS HP device type
SENSE_AMP_D = .2e-9; // s
SENSE_AMP_P = 5.7e-15; // J
vdd[0] = 1.1;
Lphy[0] = 0.025;
Lelec[0] = 0.019;
t_ox[0] = 1.1e-3;
v_th[0] = .19491;
c_ox[0] = 1.88e-14;
mobility_eff[0] = 436.24 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[0] = 7.71e-2;
c_g_ideal[0] = 4.69e-16;
c_fringe[0] = 0.077e-15;
c_junc[0] = 1e-15;
I_on_n[0] = 1197.2e-6;
I_on_p[0] = 870.8e-6;
nmos_effective_resistance_multiplier = 1.50;
n_to_p_eff_curr_drv_ratio[0] = 2.41;
gmp_to_gmn_multiplier[0] = 1.38;
Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];
Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];
I_off_n[0][0] = 1.96e-7;
I_off_n[0][10] = 2.29e-7;
I_off_n[0][20] = 2.66e-7;
I_off_n[0][30] = 3.05e-7;
I_off_n[0][40] = 3.49e-7;
I_off_n[0][50] = 3.95e-7;
I_off_n[0][60] = 4.45e-7;
I_off_n[0][70] = 4.97e-7;
I_off_n[0][80] = 5.48e-7;
I_off_n[0][90] = 5.94e-7;
I_off_n[0][100] = 6.3e-7;
//ITRS LSTP device type
vdd[1] = 1.2;
Lphy[1] = 0.045;
Lelec[1] = 0.0298;
t_ox[1] = 1.9e-3;
v_th[1] = 0.52354;
c_ox[1] = 1.36e-14;
mobility_eff[1] = 341.21 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[1] = 0.128;
c_g_ideal[1] = 6.14e-16;
c_fringe[1] = 0.08e-15;
c_junc[1] = 1e-15;
I_on_n[1] = 519.2e-6;
I_on_p[1] = 266e-6;
nmos_effective_resistance_multiplier = 1.96;
n_to_p_eff_curr_drv_ratio[1] = 2.23;
gmp_to_gmn_multiplier[1] = 0.99;
Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1];
Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1];
I_off_n[1][0] = 9.12e-12;
I_off_n[1][10] = 1.49e-11;
I_off_n[1][20] = 2.36e-11;
I_off_n[1][30] = 3.64e-11;
I_off_n[1][40] = 5.48e-11;
I_off_n[1][50] = 8.05e-11;
I_off_n[1][60] = 1.15e-10;
I_off_n[1][70] = 1.59e-10;
I_off_n[1][80] = 2.1e-10;
I_off_n[1][90] = 2.62e-10;
I_off_n[1][100] = 3.21e-10;
//ITRS LOP device type
vdd[2] = 0.8;
Lphy[2] = 0.032;
Lelec[2] = 0.0216;
t_ox[2] = 1.2e-3;
v_th[2] = 0.28512;
c_ox[2] = 1.87e-14;
mobility_eff[2] = 495.19 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[2] = 0.292;
c_g_ideal[2] = 6e-16;
c_fringe[2] = 0.08e-15;
c_junc[2] = 1e-15;
I_on_n[2] = 573.1e-6;
I_on_p[2] = 340.6e-6;
nmos_effective_resistance_multiplier = 1.82;
n_to_p_eff_curr_drv_ratio[2] = 2.28;
gmp_to_gmn_multiplier[2] = 1.11;
Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2];
Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2];
I_off_n[2][0] = 4.9e-9;
I_off_n[2][10] = 6.49e-9;
I_off_n[2][20] = 8.45e-9;
I_off_n[2][30] = 1.08e-8;
I_off_n[2][40] = 1.37e-8;
I_off_n[2][50] = 1.71e-8;
I_off_n[2][60] = 2.09e-8;
I_off_n[2][70] = 2.48e-8;
I_off_n[2][80] = 2.84e-8;
I_off_n[2][90] = 3.13e-8;
I_off_n[2][100] = 3.42e-8;
if (ram_cell_tech_type == lp_dram)
{
//LP-DRAM cell access transistor technology parameters
curr_vdd_dram_cell = 1.2;
Lphy[3] = 0.12;
Lelec[3] = 0.0756;
curr_v_th_dram_access_transistor = 0.43806;
width_dram_access_transistor = 0.09;
curr_I_on_dram_cell = 36e-6;
curr_I_off_dram_cell_worst_case_length_temp = 19.6e-12;
curr_Wmemcella_dram = width_dram_access_transistor;
curr_Wmemcellpmos_dram = 0;
curr_Wmemcellnmos_dram = 0;
curr_area_cell_dram = 0.11;
curr_asp_ratio_cell_dram = 1.46;
curr_c_dram_cell = 20e-15;
//LP-DRAM wordline transistor parameters
curr_vpp = 1.6;
t_ox[3] = 2.2e-3;
v_th[3] = 0.43806;
c_ox[3] = 1.22e-14;
mobility_eff[3] = 328.32 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[3] = 0.43806;
c_g_ideal[3] = 1.46e-15;
c_fringe[3] = 0.08e-15;
c_junc[3] = 1e-15 ;
I_on_n[3] = 399.8e-6;
I_on_p[3] = 243.4e-6;
nmos_effective_resistance_multiplier = 1.65;
n_to_p_eff_curr_drv_ratio[3] = 2.05;
gmp_to_gmn_multiplier[3] = 0.90;
Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];
Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];
I_off_n[3][0] = 2.23e-11;
I_off_n[3][10] = 3.46e-11;
I_off_n[3][20] = 5.24e-11;
I_off_n[3][30] = 7.75e-11;
I_off_n[3][40] = 1.12e-10;
I_off_n[3][50] = 1.58e-10;
I_off_n[3][60] = 2.18e-10;
I_off_n[3][70] = 2.88e-10;
I_off_n[3][80] = 3.63e-10;
I_off_n[3][90] = 4.41e-10;
I_off_n[3][100] = 5.36e-10;
}
else if (ram_cell_tech_type == comm_dram)
{
//COMM-DRAM cell access transistor technology parameters
curr_vdd_dram_cell = 1.3;
Lphy[3] = 0.065;
Lelec[3] = 0.0426;
curr_v_th_dram_access_transistor = 1;
width_dram_access_transistor = 0.065;
curr_I_on_dram_cell = 20e-6;
curr_I_off_dram_cell_worst_case_length_temp = 1e-15;
curr_Wmemcella_dram = width_dram_access_transistor;
curr_Wmemcellpmos_dram = 0;
curr_Wmemcellnmos_dram = 0;
curr_area_cell_dram = 6*0.065*0.065;
curr_asp_ratio_cell_dram = 1.5;
curr_c_dram_cell = 30e-15;
//COMM-DRAM wordline transistor parameters
curr_vpp = 3.3;
t_ox[3] = 5e-3;
v_th[3] = 1.0;
c_ox[3] = 6.16e-15;
mobility_eff[3] = 303.44 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[3] = 0.385;
c_g_ideal[3] = 4e-16;
c_fringe[3] = 0.08e-15;
c_junc[3] = 1e-15 ;
I_on_n[3] = 1031e-6;
I_on_p[3] = I_on_n[3] / 2;
nmos_effective_resistance_multiplier = 1.69;
n_to_p_eff_curr_drv_ratio[3] = 2.39;
gmp_to_gmn_multiplier[3] = 0.90;
Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];
Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];
I_off_n[3][0] = 1.80e-14;
I_off_n[3][10] = 3.64e-14;
I_off_n[3][20] = 7.03e-14;
I_off_n[3][30] = 1.31e-13;
I_off_n[3][40] = 2.35e-13;
I_off_n[3][50] = 4.09e-13;
I_off_n[3][60] = 6.89e-13;
I_off_n[3][70] = 1.13e-12;
I_off_n[3][80] = 1.78e-12;
I_off_n[3][90] = 2.71e-12;
I_off_n[3][100] = 3.99e-12;
}
//SRAM cell properties
curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um;
curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um;
curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um;
curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um;
curr_asp_ratio_cell_sram = 1.46;
}
if (tech == 45)
{ //45nm technology-node. Corresponds to year 2010 in ITRS
//ITRS HP device type
SENSE_AMP_D = .04e-9; // s
SENSE_AMP_P = 2.7e-15; // J
vdd[0] = 1.0;
Lphy[0] = 0.018;
Lelec[0] = 0.01345;
t_ox[0] = 0.65e-3;
v_th[0] = .18035;
c_ox[0] = 3.77e-14;
mobility_eff[0] = 266.68 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[0] = 9.38E-2;
c_g_ideal[0] = 6.78e-16;
c_fringe[0] = 0.05e-15;
c_junc[0] = 1e-15;
I_on_n[0] = 2046.6e-6;
//There are certain problems with the ITRS PMOS numbers in MASTAR for 45nm. So we are using 65nm values of
//n_to_p_eff_curr_drv_ratio and gmp_to_gmn_multiplier for 45nm
I_on_p[0] = I_on_n[0] / 2;//This value is fixed arbitrarily but I_on_p is not being used in CACTI
nmos_effective_resistance_multiplier = 1.51;
n_to_p_eff_curr_drv_ratio[0] = 2.41;
gmp_to_gmn_multiplier[0] = 1.38;
Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];
Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];
I_off_n[0][0] = 2.8e-7;
I_off_n[0][10] = 3.28e-7;
I_off_n[0][20] = 3.81e-7;
I_off_n[0][30] = 4.39e-7;
I_off_n[0][40] = 5.02e-7;
I_off_n[0][50] = 5.69e-7;
I_off_n[0][60] = 6.42e-7;
I_off_n[0][70] = 7.2e-7;
I_off_n[0][80] = 8.03e-7;
I_off_n[0][90] = 8.91e-7;
I_off_n[0][100] = 9.84e-7;
//ITRS LSTP device type
vdd[1] = 1.1;
Lphy[1] = 0.028;
Lelec[1] = 0.0212;
t_ox[1] = 1.4e-3;
v_th[1] = 0.50245;
c_ox[1] = 2.01e-14;
mobility_eff[1] = 363.96 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[1] = 9.12e-2;
c_g_ideal[1] = 5.18e-16;
c_fringe[1] = 0.08e-15;
c_junc[1] = 1e-15;
I_on_n[1] = 666.2e-6;
I_on_p[1] = I_on_n[1] / 2;
nmos_effective_resistance_multiplier = 1.99;
n_to_p_eff_curr_drv_ratio[1] = 2.23;
gmp_to_gmn_multiplier[1] = 0.99;
Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1];
Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1];
I_off_n[1][0] = 1.01e-11;
I_off_n[1][10] = 1.65e-11;
I_off_n[1][20] = 2.62e-11;
I_off_n[1][30] = 4.06e-11;
I_off_n[1][40] = 6.12e-11;
I_off_n[1][50] = 9.02e-11;
I_off_n[1][60] = 1.3e-10;
I_off_n[1][70] = 1.83e-10;
I_off_n[1][80] = 2.51e-10;
I_off_n[1][90] = 3.29e-10;
I_off_n[1][100] = 4.1e-10;
//ITRS LOP device type
vdd[2] = 0.7;
Lphy[2] = 0.022;
Lelec[2] = 0.016;
t_ox[2] = 0.9e-3;
v_th[2] = 0.22599;
c_ox[2] = 2.82e-14;//F/micron2
mobility_eff[2] = 508.9 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[2] = 5.71e-2;
c_g_ideal[2] = 6.2e-16;
c_fringe[2] = 0.073e-15;
c_junc[2] = 1e-15;
I_on_n[2] = 748.9e-6;
I_on_p[2] = I_on_n[2] / 2;
nmos_effective_resistance_multiplier = 1.76;
n_to_p_eff_curr_drv_ratio[2] = 2.28;
gmp_to_gmn_multiplier[2] = 1.11;
Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2];
Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2];
I_off_n[2][0] = 4.03e-9;
I_off_n[2][10] = 5.02e-9;
I_off_n[2][20] = 6.18e-9;
I_off_n[2][30] = 7.51e-9;
I_off_n[2][40] = 9.04e-9;
I_off_n[2][50] = 1.08e-8;
I_off_n[2][60] = 1.27e-8;
I_off_n[2][70] = 1.47e-8;
I_off_n[2][80] = 1.66e-8;
I_off_n[2][90] = 1.84e-8;
I_off_n[2][100] = 2.03e-8;
if (ram_cell_tech_type == lp_dram)
{
//LP-DRAM cell access transistor technology parameters
curr_vdd_dram_cell = 1.1;
Lphy[3] = 0.078;
Lelec[3] = 0.0504;// Assume Lelec is 30% lesser than Lphy for DRAM access and wordline transistors.
curr_v_th_dram_access_transistor = 0.44559;
width_dram_access_transistor = 0.079;
curr_I_on_dram_cell = 36e-6;//A
curr_I_off_dram_cell_worst_case_length_temp = 19.5e-12;
curr_Wmemcella_dram = width_dram_access_transistor;
curr_Wmemcellpmos_dram = 0;
curr_Wmemcellnmos_dram = 0;
curr_area_cell_dram = width_dram_access_transistor * Lphy[3] * 10.0;
curr_asp_ratio_cell_dram = 1.46;
curr_c_dram_cell = 20e-15;
//LP-DRAM wordline transistor parameters
curr_vpp = 1.5;
t_ox[3] = 2.1e-3;
v_th[3] = 0.44559;
c_ox[3] = 1.41e-14;
mobility_eff[3] = 426.30 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[3] = 0.181;
c_g_ideal[3] = 1.10e-15;
c_fringe[3] = 0.08e-15;
c_junc[3] = 1e-15;
I_on_n[3] = 456e-6;
I_on_p[3] = I_on_n[3] / 2;
nmos_effective_resistance_multiplier = 1.65;
n_to_p_eff_curr_drv_ratio[3] = 2.05;
gmp_to_gmn_multiplier[3] = 0.90;
Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];
Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];
I_off_n[3][0] = 2.54e-11;
I_off_n[3][10] = 3.94e-11;
I_off_n[3][20] = 5.95e-11;
I_off_n[3][30] = 8.79e-11;
I_off_n[3][40] = 1.27e-10;
I_off_n[3][50] = 1.79e-10;
I_off_n[3][60] = 2.47e-10;
I_off_n[3][70] = 3.31e-10;
I_off_n[3][80] = 4.26e-10;
I_off_n[3][90] = 5.27e-10;
I_off_n[3][100] = 6.46e-10;
}
else if (ram_cell_tech_type == comm_dram)
{
//COMM-DRAM cell access transistor technology parameters
curr_vdd_dram_cell = 1.1;
Lphy[3] = 0.045;
Lelec[3] = 0.0298;
curr_v_th_dram_access_transistor = 1;
width_dram_access_transistor = 0.045;
curr_I_on_dram_cell = 20e-6;//A
curr_I_off_dram_cell_worst_case_length_temp = 1e-15;
curr_Wmemcella_dram = width_dram_access_transistor;
curr_Wmemcellpmos_dram = 0;
curr_Wmemcellnmos_dram = 0;
curr_area_cell_dram = 6*0.045*0.045;
curr_asp_ratio_cell_dram = 1.5;
curr_c_dram_cell = 30e-15;
//COMM-DRAM wordline transistor parameters
curr_vpp = 2.7;
t_ox[3] = 4e-3;
v_th[3] = 1.0;
c_ox[3] = 7.98e-15;
mobility_eff[3] = 368.58 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[3] = 0.147;
c_g_ideal[3] = 3.59e-16;
c_fringe[3] = 0.08e-15;
c_junc[3] = 1e-15;
I_on_n[3] = 999.4e-6;
I_on_p[3] = I_on_n[3] / 2;
nmos_effective_resistance_multiplier = 1.69;
n_to_p_eff_curr_drv_ratio[3] = 1.95;
gmp_to_gmn_multiplier[3] = 0.90;
Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];
Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];
I_off_n[3][0] = 1.31e-14;
I_off_n[3][10] = 2.68e-14;
I_off_n[3][20] = 5.25e-14;
I_off_n[3][30] = 9.88e-14;
I_off_n[3][40] = 1.79e-13;
I_off_n[3][50] = 3.15e-13;
I_off_n[3][60] = 5.36e-13;
I_off_n[3][70] = 8.86e-13;
I_off_n[3][80] = 1.42e-12;
I_off_n[3][90] = 2.20e-12;
I_off_n[3][100] = 3.29e-12;
}
//SRAM cell properties
curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um;
curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um;
curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um;
curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um;
curr_asp_ratio_cell_sram = 1.46;
}
if (tech == 32)
{
SENSE_AMP_D = .03e-9; // s
SENSE_AMP_P = 2.16e-15; // J
//For 2013, MPU/ASIC stagger-contacted M1 half-pitch is 32 nm (so this is 32 nm
//technology i.e. FEATURESIZE = 0.032). Using the SOI process numbers for
//HP and LSTP.
vdd[0] = 0.9;
Lphy[0] = 0.013;
Lelec[0] = 0.01013;
t_ox[0] = 0.5e-3;
v_th[0] = 0.21835;
c_ox[0] = 4.11e-14;
mobility_eff[0] = 361.84 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[0] = 5.09E-2;
c_g_ideal[0] = 5.34e-16;
c_fringe[0] = 0.04e-15;
c_junc[0] = 1e-15;
I_on_n[0] = 2211.7e-6;
I_on_p[0] = I_on_n[0] / 2;
nmos_effective_resistance_multiplier = 1.49;
n_to_p_eff_curr_drv_ratio[0] = 2.41;
gmp_to_gmn_multiplier[0] = 1.38;
Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];//ohm-micron
Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];//ohm-micron
I_off_n[0][0] = 1.52e-7;
I_off_n[0][10] = 1.55e-7;
I_off_n[0][20] = 1.59e-7;
I_off_n[0][30] = 1.68e-7;
I_off_n[0][40] = 1.90e-7;
I_off_n[0][50] = 2.69e-7;
I_off_n[0][60] = 5.32e-7;
I_off_n[0][70] = 1.02e-6;
I_off_n[0][80] = 1.62e-6;
I_off_n[0][90] = 2.73e-6;
I_off_n[0][100] = 6.1e-6;
//LSTP device type
vdd[1] = 1;
Lphy[1] = 0.020;
Lelec[1] = 0.0173;
t_ox[1] = 1.2e-3;
v_th[1] = 0.513;
c_ox[1] = 2.29e-14;
mobility_eff[1] = 347.46 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[1] = 8.64e-2;
c_g_ideal[1] = 4.58e-16;
c_fringe[1] = 0.053e-15;
c_junc[1] = 1e-15;
I_on_n[1] = 683.6e-6;
I_on_p[1] = I_on_n[1] / 2;
nmos_effective_resistance_multiplier = 1.99;
n_to_p_eff_curr_drv_ratio[1] = 2.23;
gmp_to_gmn_multiplier[1] = 0.99;
Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1];
Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1];
I_off_n[1][0] = 2.06e-11;
I_off_n[1][10] = 3.30e-11;
I_off_n[1][20] = 5.15e-11;
I_off_n[1][30] = 7.83e-11;
I_off_n[1][40] = 1.16e-10;
I_off_n[1][50] = 1.69e-10;
I_off_n[1][60] = 2.40e-10;
I_off_n[1][70] = 3.34e-10;
I_off_n[1][80] = 4.54e-10;
I_off_n[1][90] = 5.96e-10;
I_off_n[1][100] = 7.44e-10;
//LOP device type
vdd[2] = 0.6;
Lphy[2] = 0.016;
Lelec[2] = 0.01232;
t_ox[2] = 0.9e-3;
v_th[2] = 0.24227;
c_ox[2] = 2.84e-14;
mobility_eff[2] = 513.52 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[2] = 4.64e-2;
c_g_ideal[2] = 4.54e-16;
c_fringe[2] = 0.057e-15;
c_junc[2] = 1e-15;
I_on_n[2] = 827.8e-6;
I_on_p[2] = I_on_n[2] / 2;
nmos_effective_resistance_multiplier = 1.73;
n_to_p_eff_curr_drv_ratio[2] = 2.28;
gmp_to_gmn_multiplier[2] = 1.11;
Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2];
Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2];
I_off_n[2][0] = 5.94e-8;
I_off_n[2][10] = 7.23e-8;
I_off_n[2][20] = 8.7e-8;
I_off_n[2][30] = 1.04e-7;
I_off_n[2][40] = 1.22e-7;
I_off_n[2][50] = 1.43e-7;
I_off_n[2][60] = 1.65e-7;
I_off_n[2][70] = 1.90e-7;
I_off_n[2][80] = 2.15e-7;
I_off_n[2][90] = 2.39e-7;
I_off_n[2][100] = 2.63e-7;
if (ram_cell_tech_type == lp_dram)
{
//LP-DRAM cell access transistor technology parameters
curr_vdd_dram_cell = 1.0;
Lphy[3] = 0.056;
Lelec[3] = 0.0419;//Assume Lelec is 30% lesser than Lphy for DRAM access and wordline transistors.
curr_v_th_dram_access_transistor = 0.44129;
width_dram_access_transistor = 0.056;
curr_I_on_dram_cell = 36e-6;
curr_I_off_dram_cell_worst_case_length_temp = 18.9e-12;
curr_Wmemcella_dram = width_dram_access_transistor;
curr_Wmemcellpmos_dram = 0;
curr_Wmemcellnmos_dram = 0;
curr_area_cell_dram = width_dram_access_transistor * Lphy[3] * 10.0;
curr_asp_ratio_cell_dram = 1.46;
curr_c_dram_cell = 20e-15;
//LP-DRAM wordline transistor parameters
curr_vpp = 1.5;
t_ox[3] = 2e-3;
v_th[3] = 0.44467;
c_ox[3] = 1.48e-14;
mobility_eff[3] = 408.12 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[3] = 0.174;
c_g_ideal[3] = 7.45e-16;
c_fringe[3] = 0.053e-15;
c_junc[3] = 1e-15;
I_on_n[3] = 1055.4e-6;
I_on_p[3] = I_on_n[3] / 2;
nmos_effective_resistance_multiplier = 1.65;
n_to_p_eff_curr_drv_ratio[3] = 2.05;
gmp_to_gmn_multiplier[3] = 0.90;
Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];
Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];
I_off_n[3][0] = 3.57e-11;
I_off_n[3][10] = 5.51e-11;
I_off_n[3][20] = 8.27e-11;
I_off_n[3][30] = 1.21e-10;
I_off_n[3][40] = 1.74e-10;
I_off_n[3][50] = 2.45e-10;
I_off_n[3][60] = 3.38e-10;
I_off_n[3][70] = 4.53e-10;
I_off_n[3][80] = 5.87e-10;
I_off_n[3][90] = 7.29e-10;
I_off_n[3][100] = 8.87e-10;
}
else if (ram_cell_tech_type == comm_dram)
{
//COMM-DRAM cell access transistor technology parameters
curr_vdd_dram_cell = 1.0;
Lphy[3] = 0.032;
Lelec[3] = 0.0205;//Assume Lelec is 30% lesser than Lphy for DRAM access and wordline transistors.
curr_v_th_dram_access_transistor = 1;
width_dram_access_transistor = 0.032;
curr_I_on_dram_cell = 20e-6;
curr_I_off_dram_cell_worst_case_length_temp = 1e-15;
curr_Wmemcella_dram = width_dram_access_transistor;
curr_Wmemcellpmos_dram = 0;
curr_Wmemcellnmos_dram = 0;
curr_area_cell_dram = 6*0.032*0.032;
curr_asp_ratio_cell_dram = 1.5;
curr_c_dram_cell = 30e-15;
//COMM-DRAM wordline transistor parameters
curr_vpp = 2.6;
t_ox[3] = 4e-3;
v_th[3] = 1.0;
c_ox[3] = 7.99e-15;
mobility_eff[3] = 380.76 * (1e-2 * 1e6 * 1e-2 * 1e6);
Vdsat[3] = 0.129;
c_g_ideal[3] = 2.56e-16;
c_fringe[3] = 0.053e-15;
c_junc[3] = 1e-15;
I_on_n[3] = 1024.5e-6;
I_on_p[3] = I_on_n[3] / 2;
nmos_effective_resistance_multiplier = 1.69;
n_to_p_eff_curr_drv_ratio[3] = 1.95;
gmp_to_gmn_multiplier[3] = 0.90;
Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];
Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];
I_off_n[3][0] = 3.63e-14;
I_off_n[3][10] = 7.18e-14;
I_off_n[3][20] = 1.36e-13;
I_off_n[3][30] = 2.49e-13;
I_off_n[3][40] = 4.41e-13;
I_off_n[3][50] = 7.55e-13;
I_off_n[3][60] = 1.26e-12;
I_off_n[3][70] = 2.03e-12;
I_off_n[3][80] = 3.19e-12;
I_off_n[3][90] = 4.87e-12;
I_off_n[3][100] = 7.16e-12;
}
//SRAM cell properties
curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um;
curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um;
curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um;
curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um;
curr_asp_ratio_cell_sram = 1.46;
}
// if(tech == 22){
// //For 2016, MPU/ASIC stagger-contacted M1 half-pitch is 22 nm (so this is 32 nm
// //technology i.e. FEATURESIZE = 0.022). Using the DG process numbers for
// //HP.
// //22 nm HP
// vdd[0] = 0.8;
// Lphy[0] = 0.009;//Lphy is the physical gate-length.
// Lelec[0] = 0.00468;//Lelec is the electrical gate-length.
// t_ox[0] = 0.55e-3;//micron
// v_th[0] = 0.1395;//V
// c_ox[0] = 3.63e-14;//F/micron2
// mobility_eff[0] = 426.07 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs
// Vdsat[0] = 2.33e-2; //V/micron
// c_g_ideal[0] = 3.27e-16;//F/micron
// c_fringe[0] = 0.06e-15;//F/micron
// c_junc[0] = 0;//F/micron2