-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathncverilog.log
214 lines (214 loc) · 8.47 KB
/
ncverilog.log
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
ncverilog: 11.10-s072: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
TOOL: ncverilog 11.10-s072: Started on Sep 17, 2016 at 03:04:05 CST
ncverilog
-y
/fpga/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims
-y
/fpga/Xilinx/14.2/ISE_DS/ISE/verilog/src/XilinxCoreLib
+incdir+/fpga/Xilinx/14.2/ISE_DS/ISE/verilog/src
+libext+.v
/fpga/Xilinx/14.2/ISE_DS/ISE/verilog/src/glbl.v
./blk_mem_gen_v7_2.v
./TESTBENCH.v
+define+RTL
+access+rw
+notimingchecks
file: /fpga/Xilinx/14.2/ISE_DS/ISE/verilog/src/glbl.v
module worklib.glbl:v
errors: 0, warnings: 0
file: ./blk_mem_gen_v7_2.v
module worklib.blk_mem_gen_v7_2:v
errors: 0, warnings: 0
file: ./TESTBENCH.v
module worklib.PATTERN:v
errors: 0, warnings: 0
module worklib.ram_1R1W:v
errors: 0, warnings: 0
module worklib.TESTBENCH:v
errors: 0, warnings: 0
file: /fpga/Xilinx/14.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V7_2.v
module XilinxCoreLib.BLK_MEM_GEN_V7_2:v
errors: 0, warnings: 0
file: /fpga/Xilinx/14.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V7_2.v
module XilinxCoreLib.blk_mem_axi_write_wrapper_beh_V7_2:v
errors: 0, warnings: 0
module XilinxCoreLib.blk_mem_axi_read_wrapper_beh_V7_2:v
errors: 0, warnings: 0
module XilinxCoreLib.blk_mem_axi_regs_fwd_v7_2:v
errors: 0, warnings: 0
module XilinxCoreLib.BLK_MEM_GEN_V7_2_mem_module:v
errors: 0, warnings: 0
file: /fpga/Xilinx/14.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V7_2.v
module XilinxCoreLib.write_netlist_V7_2:v
errors: 0, warnings: 0
module XilinxCoreLib.read_netlist_V7_2:v
errors: 0, warnings: 0
module XilinxCoreLib.BLK_MEM_GEN_V7_2_output_stage:v
errors: 0, warnings: 0
module XilinxCoreLib.BLK_MEM_GEN_V7_2_softecc_output_reg_stage:v
errors: 0, warnings: 0
file: /fpga/Xilinx/14.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V7_2.v
module XilinxCoreLib.STATE_LOGIC_V7_2:v
errors: 0, warnings: 0
module XilinxCoreLib.beh_vlog_muxf7_V7_2:v
errors: 0, warnings: 0
module XilinxCoreLib.beh_vlog_ff_clr_V7_2:v
errors: 0, warnings: 0
module XilinxCoreLib.beh_vlog_ff_pre_V7_2:v
errors: 0, warnings: 0
module XilinxCoreLib.beh_vlog_ff_ce_clr_V7_2:v
errors: 0, warnings: 0
ncvlog: *W,LIBNOU: Library "/fpga/Xilinx/14.2/ISE_DS/ISE/verilog/src/unisims" given but not used.
Total errors/warnings found outside modules and primitives:
errors: 0, warnings: 1
Caching library 'XilinxCoreLib' ....... Done
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Building instance overlay tables: .................... Done
Generating native compiled code:
XilinxCoreLib.BLK_MEM_GEN_V7_2:v <0x49a341de>
streams: 14, words: 3201
XilinxCoreLib.BLK_MEM_GEN_V7_2_mem_module:v <0x2117739c>
streams: 50, words: 28694
XilinxCoreLib.BLK_MEM_GEN_V7_2_output_stage:v <0x7d253605>
streams: 6, words: 2179
XilinxCoreLib.BLK_MEM_GEN_V7_2_softecc_output_reg_stage:v <0x339510f8>
streams: 5, words: 1215
worklib.PATTERN:v <0x578c09bb>
streams: 2, words: 6613
worklib.TESTBENCH:v <0x029bf7b5>
streams: 0, words: 0
worklib.glbl:v <0x6abb92c6>
streams: 11, words: 2627
worklib.ram_1R1W:v <0x38ded629>
streams: 8, words: 1106
Loading native compiled code: .................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 16 19
Registers: 312 183
Scalar wires: 152 -
Vectored wires: 88 -
Always blocks: 14 65
Initial blocks: 42 60
Cont. assignments: 50 72
Pseudo assignments: 32 16
Simulation timescale: 1ps
Writing initial simulation snapshot: worklib.glbl:v
Loading snapshot worklib.glbl:v .................... Done
*Verdi3* Loading libsscore_ius111.so
*Verdi3* : Enable Parallel Dumping.
ncsim> source /usr/cad/cadence/INCISIV/cur/tools/inca/files/ncsimrc
ncsim> run
Block Memory Generator CORE Generator module loading initial data...
Block Memory Generator data initialization complete.
Block Memory Generator CORE Generator module TESTBENCH.ram.memblock[0].blkmem.inst.native_mem_module.blk_mem_gen_v7_2_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
Block Memory Generator CORE Generator module loading initial data...
Block Memory Generator data initialization complete.
Block Memory Generator CORE Generator module TESTBENCH.ram.memblock[1].blkmem.inst.native_mem_module.blk_mem_gen_v7_2_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
Execute : 0 times Correct!!
Execute : 10000 times Correct!!
Execute : 20000 times Correct!!
Execute : 30000 times Correct!!
Execute : 40000 times Correct!!
Execute : 50000 times Correct!!
Execute : 60000 times Correct!!
Execute : 70000 times Correct!!
Execute : 80000 times Correct!!
Execute : 90000 times Correct!!
Execute : 100000 times Correct!!
Execute : 110000 times Correct!!
Execute : 120000 times Correct!!
Execute : 130000 times Correct!!
Execute : 140000 times Correct!!
Execute : 150000 times Correct!!
Execute : 160000 times Correct!!
Execute : 170000 times Correct!!
Execute : 180000 times Correct!!
Execute : 190000 times Correct!!
Execute : 200000 times Correct!!
Execute : 210000 times Correct!!
Execute : 220000 times Correct!!
Execute : 230000 times Correct!!
Execute : 240000 times Correct!!
Execute : 250000 times Correct!!
Execute : 260000 times Correct!!
Execute : 270000 times Correct!!
Execute : 280000 times Correct!!
Execute : 290000 times Correct!!
Execute : 300000 times Correct!!
Execute : 310000 times Correct!!
Execute : 320000 times Correct!!
Execute : 330000 times Correct!!
Execute : 340000 times Correct!!
Execute : 350000 times Correct!!
Execute : 360000 times Correct!!
Execute : 370000 times Correct!!
Execute : 380000 times Correct!!
Execute : 390000 times Correct!!
Execute : 400000 times Correct!!
Execute : 410000 times Correct!!
Execute : 420000 times Correct!!
Execute : 430000 times Correct!!
Execute : 440000 times Correct!!
Execute : 450000 times Correct!!
Execute : 460000 times Correct!!
Execute : 470000 times Correct!!
Execute : 480000 times Correct!!
Execute : 490000 times Correct!!
Execute : 500000 times Correct!!
Execute : 510000 times Correct!!
Execute : 520000 times Correct!!
Execute : 530000 times Correct!!
Execute : 540000 times Correct!!
Execute : 550000 times Correct!!
Execute : 560000 times Correct!!
Execute : 570000 times Correct!!
Execute : 580000 times Correct!!
Execute : 590000 times Correct!!
Execute : 600000 times Correct!!
Execute : 610000 times Correct!!
Execute : 620000 times Correct!!
Execute : 630000 times Correct!!
Execute : 640000 times Correct!!
Execute : 650000 times Correct!!
Execute : 660000 times Correct!!
Execute : 670000 times Correct!!
Execute : 680000 times Correct!!
Execute : 690000 times Correct!!
Execute : 700000 times Correct!!
Execute : 710000 times Correct!!
Execute : 720000 times Correct!!
Execute : 730000 times Correct!!
Execute : 740000 times Correct!!
Execute : 750000 times Correct!!
Execute : 760000 times Correct!!
Execute : 770000 times Correct!!
Execute : 780000 times Correct!!
Execute : 790000 times Correct!!
Execute : 800000 times Correct!!
Execute : 810000 times Correct!!
Execute : 820000 times Correct!!
Execute : 830000 times Correct!!
Execute : 840000 times Correct!!
Execute : 850000 times Correct!!
Execute : 860000 times Correct!!
Execute : 870000 times Correct!!
Execute : 880000 times Correct!!
Execute : 890000 times Correct!!
Execute : 900000 times Correct!!
Execute : 910000 times Correct!!
Execute : 920000 times Correct!!
Execute : 930000 times Correct!!
Execute : 940000 times Correct!!
Execute : 950000 times Correct!!
Execute : 960000 times Correct!!
Execute : 970000 times Correct!!
Execute : 980000 times Correct!!
Execute : 990000 times Correct!!
************ PASS ALL *************
Simulation complete via $finish(1) at time 10000030 NS + 0
./PATTERN.v:92 $finish;
ncsim> exit
TOOL: ncverilog 11.10-s072: Exiting on Sep 17, 2016 at 03:04:09 CST (total: 00:00:04)