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Memory_Designs
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#Blcok RAMs (BRAMs) techniques memory designs (verilog .v file)
////////////////////////////////////////////////////////////
/////////// PATTERN.v, TESTBENCH.v, ram_1R1W.v /////
///////////////////////////////////////////////////////////////
In each file, you could saw "BLOCKSIZE" and "BLOCLSIZE" parameter
(1) BLOCKSIZE means the memory size (2K, 4K, 8K, 16k, 32K ... etc.)
2K_depth_memory: you should set BLOCKSIZE = 10.
4K_depth_memory: you should set BLOCKSIZE = 11.
8K_depth_memory: you should set BLOCKSIZE = 12.
16K_depth_memory: you should set BLOCKSIZE = 13.
32K_depth_memory: you shoudl set BLOCKSIZE = 14. ... etc.
////////////////////////////////////////////////////////////
(2) BLOCLSIZE means the address data size.
So, here it's fixed set BLOCLSIZE = 9.
You could don't change this parameter.
////////////////////////////////////////////////////////////
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