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Add test utility to create a DataDepGraph
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3 files changed

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unittests/Basic/CMakeLists.txt

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@@ -5,4 +5,5 @@ add_optsched_unittest(OptSchedBasicTests
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LoggerTest.cpp
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UtilitiesTest.cpp
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simple_machine_model_test.cpp
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ddg_test.cpp
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)

unittests/Basic/ddg.h

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#ifndef OPTSCHED_TESTS_DDG_H
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#define OPTSCHED_TESTS_DDG_H
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#include "opt-sched/Scheduler/data_dep.h"
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#include "simple_machine_model.h"
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#include "gtest/gtest.h"
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#include <memory>
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#include <string>
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std::shared_ptr<llvm::opt_sched::DataDepGraph>
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makeDDG(const std::string &DDG,
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llvm::opt_sched::MachineModel *Model = nullptr) {
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using namespace llvm::opt_sched;
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class SimpleDDG : public DataDepGraph {
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public:
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using DataDepGraph::DataDepGraph;
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void convertSUnits(bool, bool) override {
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FAIL() << "Unsupported operation convertSUnits()";
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}
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void convertRegFiles() override {
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FAIL() << "Unsupported operation convertRegFile()";
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}
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};
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struct DDGData {
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std::unique_ptr<MachineModel> Model = nullptr;
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SimpleDDG DDG;
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DDGData(MachineModel *Model) : DDG(Model) {}
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DDGData()
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: Model(llvm::make_unique<MachineModel>(simpleMachineModel())),
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DDG(Model.get()) {}
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};
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auto Result =
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Model ? std::make_shared<DDGData>(Model) : std::make_shared<DDGData>();
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auto Ret = Result->DDG.ReadFromString(DDG);
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EXPECT_TRUE(Ret != RES_ERROR && Ret != RES_FAIL && Ret != RES_TIMEOUT)
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<< "Failed to parse DDG";
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return std::shared_ptr<DataDepGraph>(Result, &Result->DDG);
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}
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#endif

unittests/Basic/ddg_test.cpp

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#include "ddg.h"
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#include "gtest/gtest.h"
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using namespace llvm::opt_sched;
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namespace {
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TEST(SimpleDDG, CanBeMade) {
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std::shared_ptr<DataDepGraph> DDG = makeDDG(R"(
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dag 7 "Simple"
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{
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dag_id fake:3
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dag_weight 1.000000
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compiler LLVM
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dag_lb -1
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dag_ub -1
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nodes
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node 0 "Inst"
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sched_order 0
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issue_cycle 0
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node 1 "Inst"
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sched_order 1
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issue_cycle 1
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node 2 "Inst"
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sched_order 2
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issue_cycle 2
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node 3 "Inst"
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sched_order 3
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issue_cycle 3
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node 4 "Inst"
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sched_order 4
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issue_cycle 4
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node 5 "artificial" "__optsched_entry"
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node 6 "artificial"
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dependencies
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dep 0 1 "other" 0
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dep 1 2 "other" 0
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dep 2 6 "other" 0
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dep 3 4 "data" 1
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dep 4 6 "other" 0
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dep 5 3 "other" 0
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dep 5 0 "other" 0
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}
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)");
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EXPECT_EQ(7, DDG->GetNodeCnt());
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}
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TEST(SimpleDDG, CanBeMadeWithRealData) {
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MachineModel Model = simpleMachineModel();
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{
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InstTypeInfo Info;
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Info.issuType = Model.getDefaultIssueType();
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Info.name = "ATOMIC_FENCE";
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Info.isCntxtDep = false;
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Info.ltncy = 0;
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Info.pipelined = true;
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Info.sprtd = true;
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Info.blksCycle = true;
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Model.AddInstType(Info);
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Info.name = "S_BARRIER";
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Model.AddInstType(Info);
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Info.name = "S_ADD_I32";
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Info.ltncy = 1;
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Model.AddInstType(Info);
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Info.name = "S_CMP_LT_U32";
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Info.ltncy = 1;
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Model.AddInstType(Info);
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}
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std::shared_ptr<DataDepGraph> DDG = makeDDG(R"(
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dag 7 "Simple"
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{
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dag_id kernel_c18_sdk_94:3
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dag_weight 1.000000
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compiler LLVM
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dag_lb -1
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dag_ub -1
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nodes
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node 0 "ATOMIC_FENCE"
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sched_order 0
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issue_cycle 0
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node 1 "S_BARRIER" "S_BARRIER"
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sched_order 1
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issue_cycle 1
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node 2 "ATOMIC_FENCE" "ATOMIC_FENCE"
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sched_order 2
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issue_cycle 2
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node 3 "S_ADD_I32" "S_ADD_I32"
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sched_order 3
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issue_cycle 3
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node 4 "S_CMP_LT_U32" "S_CMP_LT_U32"
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sched_order 4
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issue_cycle 4
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node 5 "artificial" "__optsched_entry"
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node 6 "artificial"
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dependencies
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dep 0 1 "other" 0
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dep 1 2 "other" 0
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dep 2 6 "other" 0
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dep 3 4 "data" 1
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dep 4 6 "other" 0
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dep 5 3 "other" 0
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dep 5 0 "other" 0
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}
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)",
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&Model);
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EXPECT_EQ(7, DDG->GetNodeCnt());
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}
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} // namespace

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