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Hi SAFARI team,
Recently I am considering to integrate image processing algorithms such as convolution into one DRAM chip, and I plan to firstly re-design the scheduling algorithm of memory controller and the convolution dataflow. Then I need to evaluate my design by firstly considering latency and power consumption.
And since my first design will not contain the memory interfaces, how do I modify the Ramulator to evaluate correctly?
Thanks.
The text was updated successfully, but these errors were encountered:
Hi SAFARI team,
Recently I am considering to integrate image processing algorithms such as convolution into one DRAM chip, and I plan to firstly re-design the scheduling algorithm of memory controller and the convolution dataflow. Then I need to evaluate my design by firstly considering latency and power consumption.
And since my first design will not contain the memory interfaces, how do I modify the Ramulator to evaluate correctly?
Thanks.
The text was updated successfully, but these errors were encountered: