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Question regarding PCM behavior #85

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chohy opened this issue May 26, 2020 · 1 comment
Open

Question regarding PCM behavior #85

chohy opened this issue May 26, 2020 · 1 comment

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@chohy
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chohy commented May 26, 2020

I think PCM read bandwidth and write bandwidth should be different.
Because PCM cell has an asymmetric read/write latency and is nonvolatile.
If the row buffer data doesn't change, it is not needed to write row buffer to cell array.

However, when I simulated PCM with two test memory traces, the bandwidth was same.
one memory trace is only read and the other one is only write to random memory addresses.

To make this sense, I think ramulator always rewrite the row buffer to cell array when the row is closed.

Does PCM model of ramulaor close the row differently when row buffer isn't changed?

@maryam1364
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I agree with you. PCM has asymmetric read and write latency.
Any chance that you get the correct output using this PCM model?

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