multi-core simulation has a problem in handling writebacks for cache filtered mode

[FanosLab]

By defining the Write handling parameters in the
Trace::get_filtered_request
as static:
static bool has_write = false;
static long write_addr;
static int line_num = 0;

only one copy exists across all instances and hence the write requests are leaked/intermingled among cores.

To fix this problem, I replaced these three parameters by maps as follows:

static std::map<Trace*,bool> has_write;
static std::map<Trace*,long> write_addr;
static std::map<Trace*,int> line_num;

Thanks,
Mohamed