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the cycle for DDR4 need to be updated #118

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alinezhad2018 opened this issue Aug 9, 2023 · 0 comments

alinezhad2018 commented Aug 9, 2023

ramulator/src/DDR4.h

Line 199 in 743b940

    
           {3200, 1600, 0.625, prefetch_size/2/*DDR*/, 4,     10,   2,    22, 22,  22, 16,  56,  78, 12,  4,    12,   24, 8,    10,   40,  0,   0,    8,  10, 0,     8,     0,  0}

in reference to this datasheet:
https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr4/4gb_ddr4_dram.pdf

It is recommended to update the CCDL (Column to Column Delay) value to 8, considering that the default setting is 10.

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