GDDR5 channel_width should be 32, not 64

[salvadorpetit]

According to Micron documentation: "https://www.micron.com/-/media/client/global/documents/products/technical-note/dram/tned01_gddr5_sgram_introduction.pdf"

The device interface is designed for systems with a 32-bit wide I/O memory channel,
resulting in 32 bytes of data transferred per memory cycle. Systems can span from 64-
bit wide I/O (two memory channels) for entry-level systems, to 512-bit wide I/O (16
memory channels) for high-end systems.

It is true that the minimum system must present two channels, but as far as I know each channel is 32 bit wide.