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jakubcabaljakubcabal
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Merge branch 'friedl-feat-10ge_improvements' into 'devel'
Improvements for 10/25GE modes (especially useful for HFT) See merge request ndk/ndk-fpga!191
2 parents 459453b + 2123165 commit d5098b0

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9 files changed

+77
-13
lines changed

9 files changed

+77
-13
lines changed

‎build/Vivado.inc.tcl

+28-5
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,8 @@
55
#
66
# SPDX-License-Identifier: BSD-3-Clause
77

8+
set TIMING_MET 0
9+
810
if {![info exists $env(OFM_PATH)]} {
911
set OFM_PATH $env(OFM_PATH)
1012
}
@@ -356,11 +358,28 @@ proc SynthesizeDesignRun {synth_flags} {
356358
proc ImplementDesign {synth_flags} {
357359
# Define auxiliary variables
358360
upvar 1 $synth_flags SYNTH_FLAGS
361+
global TIMING_MET
359362

360363
ImplementDesignSetup SYNTH_FLAGS
361364
# Skip actual implementation if one of the variables is set to 1/true
362365
if {$SYNTH_FLAGS(PROJ_ONLY) || $SYNTH_FLAGS(SYNTH_ONLY)} {return}
363-
ImplementDesignRun SYNTH_FLAGS
366+
ImplementDesignRun SYNTH_FLAGS "impl_1"
367+
368+
# Create Intelligent Design Run when the timing not met
369+
if {[info exist SYNTH_FLAGS(IDR)] && !$TIMING_MET} {
370+
371+
set VIVADO_VER [version -short]
372+
set YEAR [string range $VIVADO_VER 0 3]
373+
set IDR_SUPPORTED [expr {$YEAR > 2020}]
374+
375+
if {$IDR_SUPPORTED} {
376+
create_run -flow {Vivado IDR Flow 2022} -parent_run synth_1 idr_1
377+
set_property REFERENCE_RUN impl_1 [get_runs idr_1]
378+
ImplementDesignRun SYNTH_FLAGS idr_1
379+
}
380+
}
381+
382+
364383
}
365384

366385
proc ImplementDesignSetup {synth_flags} {
@@ -456,15 +475,19 @@ proc ImplementDesignSetup {synth_flags} {
456475
}
457476
}
458477

459-
proc ImplementDesignRun {synth_flags} {
478+
proc ImplementDesignRun {synth_flags RUN_NAME} {
460479
# Define auxiliary variables
461480
upvar 1 $synth_flags SYNTH_FLAGS
481+
global TIMING_MET
462482

463483
PrintLabel "Implement"
464484

465-
launch_runs impl_1
466-
wait_on_run impl_1
467-
open_run impl_1
485+
launch_runs $RUN_NAME
486+
wait_on_run $RUN_NAME
487+
open_run $RUN_NAME
488+
489+
set TIMING_MET [expr {[get_property SLACK [get_timing_paths]] >= 0}]
490+
# set TIMING_MET [expr {[get_property STATS.WNS [get_runs $RUN_NAME]] < 0}]
468491

469492
PrintLabel "Report Timing"
470493
set_delay_model -interconnect actual

‎comp/nic/mac_lite/rx_mac_lite/comp/ctrl_unit/ctrl_unit.vhd

+23-6
Original file line numberDiff line numberDiff line change
@@ -202,6 +202,9 @@ architecture FULL of RX_MAC_LITE_CTRL_UNIT is
202202
constant CMD_SW_BASE_REG : std_logic_vector(2 downto 0) := "011"; -- 0x03
203203
constant CMD_SM_CNT_CLEAR : std_logic_vector(2 downto 0) := "100"; -- 0x04
204204

205+
-- reset of control logic
206+
signal ctrl_reset : std_logic;
207+
205208
-- MI32 slave interface signals
206209
signal s_mi_dwr : std_logic_vector(31 downto 0);
207210
signal s_mi_addr : std_logic_vector(31 downto 0);
@@ -296,6 +299,20 @@ architecture FULL of RX_MAC_LITE_CTRL_UNIT is
296299

297300
begin
298301

302+
-- Generate separate reset signal for logic that shouldn't be affected by the network
303+
-- side resets
304+
ctrl_reset_sync_i : entity work.ASYNC_RESET
305+
generic map (
306+
TWO_REG => false,
307+
OUT_REG => true,
308+
REPLICAS => 1
309+
)
310+
port map (
311+
CLK => CLK,
312+
ASYNC_RST => MI_RESET,
313+
OUT_RST(0) => ctrl_reset
314+
);
315+
299316
-- =========================================================================
300317
-- MI32 ASYNC
301318
-- =========================================================================
@@ -440,7 +457,7 @@ begin
440457
reg_enable_p : process (CLK)
441458
begin
442459
if (rising_edge(CLK)) then
443-
if (RESET = '1') then
460+
if (ctrl_reset = '1') then
444461
s_reg_enable <= '0';
445462
elsif (s_reg_enable_we = '1') then
446463
s_reg_enable <= s_mi_dwr(0);
@@ -452,7 +469,7 @@ begin
452469
reg_error_mask_p : process (CLK)
453470
begin
454471
if (rising_edge(CLK)) then
455-
if (RESET = '1') then
472+
if (ctrl_reset = '1') then
456473
s_reg_error_mask <= (others => '1');
457474
elsif (s_reg_error_mask_we = '1') then
458475
s_reg_error_mask <= s_mi_dwr(4 downto 0);
@@ -487,7 +504,7 @@ begin
487504
reg_min_frame_len_p : process (CLK)
488505
begin
489506
if (rising_edge(CLK)) then
490-
if (RESET = '1') then
507+
if (ctrl_reset = '1') then
491508
s_reg_min_frame_len <= std_logic_vector(to_unsigned(64,LEN_WIDTH));
492509
elsif (s_reg_min_frame_len_we = '1') then
493510
s_reg_min_frame_len <= s_mi_dwr(LEN_WIDTH-1 downto 0);
@@ -507,7 +524,7 @@ begin
507524
reg_max_frame_len_p : process (CLK)
508525
begin
509526
if (rising_edge(CLK)) then
510-
if (RESET = '1') then
527+
if (ctrl_reset = '1') then
511528
s_reg_max_frame_len <= std_logic_vector(to_unsigned(1526,LEN_WIDTH));
512529
elsif (s_reg_max_frame_len_we = '1') then
513530
s_reg_max_frame_len <= s_mi_dwr(LEN_WIDTH-1 downto 0);
@@ -527,7 +544,7 @@ begin
527544
reg_mac_check_mode_p : process (CLK)
528545
begin
529546
if (rising_edge(CLK)) then
530-
if (RESET = '1') then
547+
if (ctrl_reset = '1') then
531548
s_reg_mac_check_mode <= (others => '0');
532549
elsif (s_reg_mac_check_mode_we = '1') then
533550
s_reg_mac_check_mode <= s_mi_dwr(1 downto 0);
@@ -752,7 +769,7 @@ begin
752769
reg_sel_register_out_p : process (CLK)
753770
begin
754771
if (rising_edge(CLK)) then
755-
if (RESET = '1') then
772+
if (ctrl_reset = '1') then
756773
-- Select base register field by default
757774
s_reg_sel_register_out <= '0';
758775
elsif (s_cmd_switch_rfc_reg = '1') then

‎core/comp/eth/network_mod/comp/network_mod_core/network_mod_core_ent.vhd

+2
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,8 @@ generic(
7373
MISC_TOP2NET_WIDTH : natural := 1;
7474
-- Width of MISC signal between NET_MOD core logic and Top-Level FPGA design
7575
MISC_NET2TOP_WIDTH : natural := 1;
76+
-- QSFP(DD) physical lanes to Ethernet channels mapping (10 & 25G modes)
77+
CHANNEL_MAP : integer_vector(7 downto 0) := (7, 6, 5, 4, 3, 2, 1, 0);
7678
-- Select correct FPGA device.
7779
-- "AGILEX", "STRATIX10", "ULTRASCALE", ...
7880
DEVICE : string := "STRATIX10"

‎core/comp/eth/network_mod/network_mod.vhd

+1
Original file line numberDiff line numberDiff line change
@@ -460,6 +460,7 @@ begin
460460
generic map (
461461
ETH_PORT_SPEED => ETH_PORT_SPEED(p),
462462
ETH_PORT_CHAN => ETH_PORT_CHAN (p),
463+
CHANNEL_MAP => ETH_CHAN_MAP ,
463464
EHIP_TYPE => EHIP_TYPE ,
464465
LANES => LANES ,
465466
REGIONS => REGIONS_CORE ,

‎core/comp/eth/network_mod/network_mod_ent.vhd

+2
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,8 @@ generic(
4040
ETH_PORT_RX_MTU : integer_vector(ETH_PORTS-1 downto 0) := (others => 16383);
4141
-- Maximum allowed size of TX frame in bytes per Ethernet port.
4242
ETH_PORT_TX_MTU : integer_vector(ETH_PORTS-1 downto 0) := (others => 16383);
43+
-- Optional remapping of physical QSFP(DD) lanes to Eth channel numbers
44+
ETH_CHAN_MAP : integer_vector(7 downto 0) := (7, 6, 5, 4, 3, 2, 1, 0);
4345
-- Optional option to disable MAC Lite modules. Dangerously!
4446
ETH_MAC_BYPASS : boolean := False;
4547
-- Number of serial lanes.

‎core/config/core_conf.tcl

+10
Original file line numberDiff line numberDiff line change
@@ -157,3 +157,13 @@ set TS_DEMO_EN false
157157

158158
# Enable Low-latency optimalizations
159159
set LL_MODE false
160+
161+
set ETH_CHAN_MAP(0) 0
162+
set ETH_CHAN_MAP(1) 1
163+
set ETH_CHAN_MAP(2) 2
164+
set ETH_CHAN_MAP(3) 3
165+
set ETH_CHAN_MAP(4) 4
166+
set ETH_CHAN_MAP(5) 5
167+
set ETH_CHAN_MAP(6) 6
168+
set ETH_CHAN_MAP(7) 7
169+

‎core/config/core_const.tcl

+2
Original file line numberDiff line numberDiff line change
@@ -109,6 +109,8 @@ if {$ETH_PORTS == 0} {
109109
VhdlPkgIntArr ETH_PORT_TX_MTU $ETH_PORTS
110110
}
111111

112+
VhdlPkgIntArr ETH_CHAN_MAP 8
113+
112114
VhdlPkgInt ETH_STREAMS_MODE $ETH_STREAMS_MODE
113115
VhdlPkgBool ETH_MAC_BYPASS $ETH_MAC_BYPASS
114116

‎core/top/DevTree.tcl

+8-2
Original file line numberDiff line numberDiff line change
@@ -133,16 +133,22 @@ proc dts_build_netcope {} {
133133

134134
# Populate application, if exists
135135
global APP_CORE_ENABLE
136+
global ETH_STREAMS_MODE
137+
if {$ETH_STREAMS_MODE == 1} {
138+
set ETH_STREAMS [expr $ETH_PORTS*$ETH_PORT_CHAN(0)]
139+
} else {
140+
set ETH_STREAMS $ETH_PORTS
141+
}
136142
if {$APP_CORE_ENABLE} {
137143
if { [llength [info procs dts_application]] > 0 } {
138144
global MEM_PORTS HBM_PORTS
139145

140146
if {[llength [info args dts_application]] == 3} {
141147
# INFO: backward compatible variant without generics parameter
142-
append ret "app:" [dts_application $ADDR_USERAPP $ETH_PORTS $MEM_PORTS]
148+
append ret "app:" [dts_application $ADDR_USERAPP $ETH_STREAMS $MEM_PORTS]
143149
} else {
144150
array set GENERICS "
145-
ETH_STREAMS $ETH_PORTS
151+
ETH_STREAMS $ETH_STREAMS
146152
DDR_PORTS $MEM_PORTS
147153
HBM_PORTS $HBM_PORTS
148154
"

‎core/top/fpga_common.vhd

+1
Original file line numberDiff line numberDiff line change
@@ -1573,6 +1573,7 @@ begin
15731573
ETH_PORT_RX_MTU => ETH_PORT_RX_MTU,
15741574
ETH_PORT_TX_MTU => ETH_PORT_TX_MTU,
15751575
ETH_MAC_BYPASS => ETH_MAC_BYPASS ,
1576+
ETH_CHAN_MAP => ETH_CHAN_MAP,
15761577
LANES => ETH_LANES ,
15771578
QSFP_PORTS => QSFP_PORTS ,
15781579
QSFP_I2C_PORTS => QSFP_I2C_PORTS ,

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