-
Notifications
You must be signed in to change notification settings - Fork 0
/
testSieve.v
53 lines (42 loc) · 961 Bytes
/
testSieve.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:33:42 04/13/2015
// Design Name: Sieve
// Module Name: U:/public/PrimeFactorization/testSieve.v
// Project Name: PrimeFactorization
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Sieve
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testSieve;
// Inputs
reg clk;
// Outputs
wire [8:0] primeNumber;
wire loop;
// Instantiate the Unit Under Test (UUT)
Sieve uut (
.clk(clk),
.primeNumber(primeNumber),
.loop(loop)
);
always #1 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
// Wait 100 ns for global reset to finish
// Add stimulus here
end
endmodule