From 4b4295051cb77039874c621edc607e41517dfc61 Mon Sep 17 00:00:00 2001 From: Daniel Schwyn Date: Thu, 20 Jul 2017 18:17:39 +0200 Subject: [PATCH] Start modularizing omap44xx spec Signed-off-by: Daniel Schwyn --- socs/cortex/cortexA9.soc | 49 ++++++++++++++++++++++++ socs/omap44xx.soc | 48 ++++-------------------- socs/omap44xx/cortexA9-subsystem.soc | 56 ++++++++++++++++++++++++++++ 3 files changed, 112 insertions(+), 41 deletions(-) create mode 100644 socs/cortex/cortexA9.soc create mode 100644 socs/omap44xx/cortexA9-subsystem.soc diff --git a/socs/cortex/cortexA9.soc b/socs/cortex/cortexA9.soc new file mode 100644 index 0000000000..d5cc89d021 --- /dev/null +++ b/socs/cortex/cortexA9.soc @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2017, ETH Zurich. All rights reserved. + * + * This file is distributed under the terms in the attached LICENSE file. + * If you do not find this file, copies can be found by writing to: + * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. + * Attn: Systems Group. + */ + +module CortexA9-Core(addr periphbase) { + input CPU/32 + output SCU/8, Global_Timer/8 + output GIC_PROC/8, GIC_DISTR/12 + output L2/32 + + PERIPHBASE is map [ + 0x0000-0x00FC to SCU + 0x0100/8 to GIC_PROC + 0x0200/8 to Global_Timer + 0x0600/8 to Private_Timers + 0x1000/12 to GIC_DISTR + ] + + CPU is map [ + periphbase/13 to PERIPHBASE + ] + over L2/32 + + Private_Timers is device accept [0x0/8] +} + +module CortexA9-MPCore(nat cores, addr periphbase) { + input CPU_{[1..cores]}/32 + output L2/32 + + SCU is device accept [0x0-0xFC] + Global_Timer is device accept [0x0/8] + + GIC_PROC is device accept [0x0/8] + GIC_DISTR is device accept [0x0/12] + + CortexA9-Core(periphbase) as Core_{c in [1..cores]} with + CPU_{c} > CPU + SCU < SCU + Global_Timer < Global_Timer + GIC_PROC < GIC_PROC + GIC_DISTR < GIC_DISTR + L2 < L2 +} \ No newline at end of file diff --git a/socs/omap44xx.soc b/socs/omap44xx.soc index 23c788512b..d9dc28963c 100644 --- a/socs/omap44xx.soc +++ b/socs/omap44xx.soc @@ -16,6 +16,8 @@ * */ +import omap44xx/cortexA9-subsystem + /* * 2.2 L3 Memory space mapping */ @@ -23,7 +25,6 @@ SRAM is memory accept [0x0/30] /* Q1 */ -BOOT_ROM is memory accept [0x0-0xBFFF] L3_OCM_RAM is memory accept [0x0-0xDFFF] /* Q2 */ @@ -34,7 +35,7 @@ SDRAM is memory accept [0x0/30] L3 is map [ 0x00000000/30 to SRAM /* 0x40000000-0x4002FFFF reserved */ - 0x40030000-0x4003BFFF to BOOT_ROM + /* 0x40030000-0x4003BFFF Cortex-A9 ROM */ /* 0x4003C000-0x400FFFFF reserved */ //TRM: 0x40034000-0x400FFFFF? /* 0x40100000/20 L4_ABE private access for Cortex A9 /* 0x40200000/20 reserved */ @@ -389,19 +390,10 @@ L4_ABE is accept [0x00000/14] // XXX: First 16KB do what? /* * Cortex A9 Memory Space Mapping */ -CORTEXA9 is map [ - 0x40100000/20 to L4_ABE - 0x48240000/13 to PERIPHBASE - 0x48242000/12 to PL310 - 0x48243000/9 to CORTEXA9_SOCKET_PRCM - 0x48243200/9 to CORTEXA9_PRM - 0x48243400/10 to CORTEXA9_CPU0 - 0x48243800/10 to CORTEXA9_CPU1 - 0x48281000/12 to CORTEXA9_WUGEN - 0x48290000/16 to CMU - 0x482A0000/12 to Local_interconnect - 0x482AF000/12 to MA - ] over L3/32 +CortexA9-Subsystem as CortexA9_SS with + CORTEXA9_{c in [1..2]} > CPU_{c} + L3 < L3 + L4_ABE < L4_ABE /* * 2.4 Dual Cortex-M3 Subsystem Memory Space Mapping @@ -533,32 +525,6 @@ SR_MPU is device accept [0x0/8] SR_IVA is device accept [0x0/8] SR_CORE is device accept [0x0/8] -/* - * 4 Dual Cortex-A9 MPU Subsystem - */ -SCU is device accept [0x00-0xFC] -GIC_PROC is device accept [0x0/8] -Global_Timer is device accept [0x0/8] -Timer is device accept [0x0/8] -GIC_DIST is device accept [0x0/12] -PL310 is device accept [0x0/12] -CORTEXA9_SOCKET_PRCM is device accept [0x0/9] -CORTEXA9_PRM is device accept [0x0/9] -CORTEXA9_CPU0, -CORTEXA9_CPU1 are device accept [0x0/10] -CORTEXA9_WUGEN is device accept [0x0/12] -CMU is device accept [0x0/16] -Local_interconnect is device accept [0x0/12] -MA is device accept [0x0/12] - -PERIPHBASE is map [ - 0x0000/8 to SCU - 0x0100/8 to GIC_PROC - 0x0200/9 to Global_Timer - 0x0600/8 to Timer - 0x1000/12 to GIC_DIST - ] - /* * 5 DSP Subsystem */ diff --git a/socs/omap44xx/cortexA9-subsystem.soc b/socs/omap44xx/cortexA9-subsystem.soc new file mode 100644 index 0000000000..033c8a9e90 --- /dev/null +++ b/socs/omap44xx/cortexA9-subsystem.soc @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2017, ETH Zurich. All rights reserved. + * + * This file is distributed under the terms in the attached LICENSE file. + * If you do not find this file, copies can be found by writing to: + * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. + * Attn: Systems Group. + */ + +/** + * CortexA9 subsystem of TI OMAP4460 SoC + * + * This is derived from: + * OMAP4460 Multimedia Device Silicon Revision 1.x Technical Reference + * Manual Version Q + * + * Section 4 + * + */ + +import ../cortex/cortexA9 + +module CortexA9-Subsystem { + input CPU_{[1..2]}/32 + output L3/32, L4_ABE/20 + + ROM is memory accept [0x0-0xBFFF] + + PL310 is device accept [0x0/12] + CORTEXA9_SOCKET_PRCM is device accept [0x0/9] + CORTEXA9_PRM is device accept [0x0/9] + CORTEXA9_CPU{[0..1]} are device accept [0x0/10] + CORTEXA9_WUGEN is device accept [0x0/12] + CMU is device accept [0x0/16] + Interconnect_config is device accept [0x0/12] + MA is device accept [0x0/12] + + Interconnect is map [ + 0x40030000-0x4003BFFF to ROM + 0x40100000/20 to L4_ABE + 0x48242000/12 to PL310 + 0x48243000/9 to CORTEXA9_SOCKET_PRCM + 0x48243200/9 to CORTEXA9_PRM + 0x48243400/10 to CORTEXA9_CPU0 + 0x48243800/10 to CORTEXA9_CPU1 + 0x48281000/12 to CORTEXA9_WUGEN + 0x48290000/16 to CMU + 0x482A0000/12 to Interconnect_config + 0x482AF000/12 to MA + ] over L3/32 + + + CortexA9-MPCore(2, 0x48240000) as MPU with + CPU_{c in [1..2]} > CPU_{c} + Interconnect < L2 +}