From d5a827a55cc68e86c68400df211fd51520f0b87a Mon Sep 17 00:00:00 2001 From: Jared Wright Date: Thu, 4 Aug 2022 14:02:27 -0600 Subject: [PATCH] Update writer package to account for differences in Intel/AMD CPUID Signed-off-by: Jared Wright --- CMakeLists.txt | 4 ++-- pal/writer/access_mechanism/libpal.py | 7 ++++++- pal/writer/register/c/register_accessor.py | 10 ++++++++++ pal/writer/register/cxx11/register_accessor.py | 10 ++++++++++ pal/writer/register/rust/register_accessor.py | 10 ++++++++++ 5 files changed, 38 insertions(+), 3 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 78bbd5e2a..60b166991 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -126,7 +126,7 @@ if(PAL_AMD_64BIT_LINUX_IOCTL) OUTPUT_DIR ${CMAKE_BINARY_DIR}/c/amd_64bit_linux_ioctl LANGUAGE c EXECUTION_STATE amd_64bit - ACCESS_MECHANISM gnu_inline + ACCESS_MECHANISM libpal ) endif() @@ -136,7 +136,7 @@ if(PAL_AMD_64BIT_LINUX_IOCTL) OUTPUT_DIR ${CMAKE_BINARY_DIR}/c++11/amd_64bit_linux_ioctl LANGUAGE c++11 EXECUTION_STATE amd_64bit - ACCESS_MECHANISM gnu_inline + ACCESS_MECHANISM libpal ) endif() diff --git a/pal/writer/access_mechanism/libpal.py b/pal/writer/access_mechanism/libpal.py index bdafcccb7..118e39d8e 100644 --- a/pal/writer/access_mechanism/libpal.py +++ b/pal/writer/access_mechanism/libpal.py @@ -204,7 +204,12 @@ def __declare_msr_register_dependencies(self, outfile, register, def __call_cpuid_access_mechanism(self, outfile, register, access_mechanism, result): - cpuid_args = [str(access_mechanism.leaf), '0'] + if register.arch == "intel": + cpuid_args = [str(access_mechanism.leaf), '0'] + elif register.arch == "amd64": + cpuid_args = [str(access_mechanism.function), '0'] + else: + raise PalWriterException("CPUID access mechanism not supported for architecture {arch}".format(arch=register.arch)) if register.is_indexed: cpuid_args[1] = 'index' diff --git a/pal/writer/register/c/register_accessor.py b/pal/writer/register/c/register_accessor.py index 60fa02197..6b3c087c4 100644 --- a/pal/writer/register/c/register_accessor.py +++ b/pal/writer/register/c/register_accessor.py @@ -38,6 +38,16 @@ def _declare_register_constants(self, outfile, register): addr = register.access_mechanisms["rdmsr"][0].address self._declare_preprocessor_constant(outfile, prefix + "address", hex(addr)) + if register.access_mechanisms.get("cpuid"): + if register.arch == "intel": + addr = register.access_mechanisms["cpuid"][0].leaf + self._declare_preprocessor_constant(outfile, prefix + "leaf", hex(addr)) + self.write_newline(outfile) + elif register.arch == "amd64": + addr = register.access_mechanisms["cpuid"][0].function + self._declare_preprocessor_constant(outfile, prefix + "function", hex(addr)) + self.write_newline(outfile) + if register.access_mechanisms.get("ldr"): offset = register.access_mechanisms["ldr"][0].offset self._declare_preprocessor_constant(outfile, prefix + "offset", hex(offset)) diff --git a/pal/writer/register/cxx11/register_accessor.py b/pal/writer/register/cxx11/register_accessor.py index d8e197ae2..f0fd58cf1 100644 --- a/pal/writer/register/cxx11/register_accessor.py +++ b/pal/writer/register/cxx11/register_accessor.py @@ -39,6 +39,16 @@ def _declare_register_constants(self, outfile, register): self._declare_hex_integer_constant(outfile, "address", addr) self.write_newline(outfile) + if register.access_mechanisms.get("cpuid"): + if register.arch == "intel": + addr = register.access_mechanisms["cpuid"][0].leaf + self._declare_hex_integer_constant(outfile, "leaf", addr) + self.write_newline(outfile) + elif register.arch == "amd64": + addr = register.access_mechanisms["cpuid"][0].function + self._declare_hex_integer_constant(outfile, "function", addr) + self.write_newline(outfile) + if register.access_mechanisms.get("ldr"): offset = register.access_mechanisms["ldr"][0].offset self._declare_hex_integer_constant(outfile, "offset", offset) diff --git a/pal/writer/register/rust/register_accessor.py b/pal/writer/register/rust/register_accessor.py index 41b81f2c4..ab57cf99d 100644 --- a/pal/writer/register/rust/register_accessor.py +++ b/pal/writer/register/rust/register_accessor.py @@ -38,6 +38,16 @@ def _declare_register_constants(self, outfile, register): self._declare_hex_integer_constant(outfile, prefix + "address", addr, n_bits=32) self.write_newline(outfile) + if register.access_mechanisms.get("cpuid"): + if register.arch == "intel": + addr = register.access_mechanisms["cpuid"][0].leaf + self._declare_hex_integer_constant(outfile, "leaf", addr) + self.write_newline(outfile) + elif register.arch == "amd64": + addr = register.access_mechanisms["cpuid"][0].function + self._declare_hex_integer_constant(outfile, "function", addr) + self.write_newline(outfile) + if register.access_mechanisms.get("ldr"): offset = register.access_mechanisms["ldr"][0].offset self._declare_hex_integer_constant(outfile, prefix + "offset", offset)