FIR_Systolic not properly pipelined

[djcopley]

Excerpt from DSP48E1 User Guide:

To achieve maximum performance when using the DSP48E1 slice, the design needs to be fully pipelined. For multiplier-based designs, the DSP48E1 slice requires a three-stage pipeline. For non-multiplier-based designs, a two-stage pipeline should be used. Also see the 7 series FPGA data sheets [Ref 6]. If latency is important in the design and only one or two registers can be used within the DSP48E1 slice, always use the M register.