This is a project for the Microelectronic Systems course (AY 2017/18), taught by Prof. Mariagrazia Graziano, @ Politecnico di Torino.
The aim is to build a functional model for a DLX processor, described using VHDL. We worked together in order to design this processor, with our own instruction set. Starting from the laboratories, we combined most of the components previously designed, eventually modifying and improving them.
It is pipelined on 5 stages, and it includes advanced features such as data forwarding and branch prediction. It contains a Carry Lookahead Adder and a Booth multiplier.
We are currently planning to add some form of Out of Order execution, as well as a Floating Point unit. This, of course, if our academic schedule will allow us sufficient free time to work on.
For any information, you can simply drop an email: