From f2bba196783fa8a009dd41698fd2ac2756526fc3 Mon Sep 17 00:00:00 2001 From: palumbon Date: Mon, 16 Sep 2024 18:32:43 +0200 Subject: [PATCH 01/20] Fixes for SimpleDruidJIT generation --- .../SimpleDruidTestRTLCompiler.class.st | 1033 ++++++++++------- Druid/DRCPSEdge.class.st | 2 +- Druid/DRCogitCodeGenerator.class.st | 4 +- Druid/DRCogitSimpleStackGenerator.class.st | 19 +- Druid/DRStackInstruction.class.st | 12 + 5 files changed, 636 insertions(+), 434 deletions(-) diff --git a/Druid-Tests/SimpleDruidTestRTLCompiler.class.st b/Druid-Tests/SimpleDruidTestRTLCompiler.class.st index 9b54ba4b..e9877ed3 100644 --- a/Druid-Tests/SimpleDruidTestRTLCompiler.class.st +++ b/Druid-Tests/SimpleDruidTestRTLCompiler.class.st @@ -1893,9 +1893,8 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAdd [ self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. currentBlock := self Label. - jump2 jmpTarget: currentBlock. - currentBlock := self Label. jump1 jmpTarget: currentBlock. + jump2 jmpTarget: currentBlock. ^ 0 ] @@ -1903,21 +1902,23 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAdd [ SimpleDruidTestRTLCompiler >> gen_primitiveAnd [ "AutoGenerated by Druid" - | jump1 jump2 currentBlock | + | s8 jump1 jump3 currentBlock jump2 s5 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 0 R: ClassReg. jump1 := self JumpLessOrEqual: 0. self CmpCq: 10 R: ClassReg. jump2 := self JumpLessOrEqual: 0. - self MoveCq: 42 R: ReceiverResultReg. - self genPrimReturn. + s5 := 42. + self MoveCq: s5 R: ClassReg. + jump3 := self Jump: 0. currentBlock := self Label. + jump1 jmpTarget: currentBlock. jump2 jmpTarget: currentBlock. - self MoveCq: 10 R: ReceiverResultReg. - self genPrimReturn. + s8 := 10. + self MoveCq: s8 R: ClassReg. currentBlock := self Label. - jump1 jmpTarget: currentBlock. - self MoveCq: 10 R: ReceiverResultReg. + jump3 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -1926,22 +1927,24 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAnd [ SimpleDruidTestRTLCompiler >> gen_primitiveAndIfTrue [ "AutoGenerated by Druid" - | jump1 jump2 currentBlock | + | jump3 jump1 s6 currentBlock s9 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 1 R: ClassReg. jump1 := self JumpLessOrEqual: 0. self AndCq: 1 R: ClassReg. self CmpCq: 1 R: ClassReg. jump2 := self JumpNonZero: 0. - self MoveCq: 1 R: ReceiverResultReg. - self genPrimReturn. + s6 := 1. + self MoveCq: s6 R: ClassReg. + jump3 := self Jump: 0. currentBlock := self Label. + jump1 jmpTarget: currentBlock. jump2 jmpTarget: currentBlock. - self MoveCq: 2 R: ReceiverResultReg. - self genPrimReturn. + s9 := 2. + self MoveCq: s9 R: ClassReg. currentBlock := self Label. - jump1 jmpTarget: currentBlock. - self MoveCq: 2 R: ReceiverResultReg. + jump3 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -1963,7 +1966,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveArithmeticBitShiftRight [ SimpleDruidTestRTLCompiler >> gen_primitiveAsCharacter [ "AutoGenerated by Druid" - | s3 s16 currentBlock s2 | + | s13 s14 s2 currentBlock s3 | s2 := self methodNumArgs. s2 = 0 ifTrue: [ | jump1 jump2 jump3 | @@ -1980,32 +1983,28 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAsCharacter [ self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. currentBlock := self Label. - jump3 jmpTarget: currentBlock. - currentBlock := self Label. - jump2 jmpTarget: currentBlock. - currentBlock := self Label. jump1 jmpTarget: currentBlock. + jump2 jmpTarget: currentBlock. + jump3 jmpTarget: currentBlock. ^ 0 ]. - s16 := self methodNumArgs. - s16 = 1 ifTrue: [ - | jump1 jump2 jump3 | + s13 := self methodNumArgs. + s13 = 1 ifTrue: [ + | jump3 jump2 jump1 | self genLoadArg: 0 into: ClassReg. self TstCq: 1 R: ClassReg. - jump1 := self JumpZero: 0. + jump3 := self JumpZero: 0. self ArithmeticShiftRightCq: 3 R: ClassReg. self CmpCq: 0 R: ClassReg. jump2 := self JumpLess: 0. self CmpCq: 16r3FFFFFFF R: ClassReg. - jump3 := self JumpGreater: 0. + jump1 := self JumpGreater: 0. self LogicalShiftLeftCq: 3 R: ClassReg. self AddCq: 2 R: ClassReg. self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. currentBlock := self Label. jump3 jmpTarget: currentBlock. - currentBlock := self Label. jump2 jmpTarget: currentBlock. - currentBlock := self Label. jump1 jmpTarget: currentBlock. ^ 0 ]. ^ 0 @@ -2015,7 +2014,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAsCharacter [ SimpleDruidTestRTLCompiler >> gen_primitiveAsFloat [ "AutoGenerated by Druid" - | jump1 jumpNext s19 jump3 currentBlock s15 jumpTrue s44 s47 jump2 | + | s34 jump5 jump3 jump1 currentBlock s31 jump2 jump4 | self MoveR: ReceiverResultReg R: ClassReg. self ArithmeticShiftRightCq: 3 R: ClassReg. self ConvertR: ClassReg Rd: DPFPReg0. @@ -2026,78 +2025,59 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAsFloat [ self CmpCq: 896 R: SendNumArgsReg. jump1 := self JumpBelowOrEqual: 0. self CmpCq: 1151 R: SendNumArgsReg. - jumpTrue := self JumpBelowOrEqual: 0. - self MoveCq: 0 R: SendNumArgsReg. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: SendNumArgsReg. - jumpNext jmpTarget: self Label. - jump2 := self Jump: 0. + jump2 := self JumpBelowOrEqual: 0. + jump3 := self JumpAbove: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. self AndCq: 16rFFFFFFFFFFFFF R: ClassReg. self CmpCq: 0 R: ClassReg. jump1 := self JumpNonZero: 0. - s15 := 0. - self CmpCq: s15 R: SendNumArgsReg. - jumpTrue := self JumpZero: 0. - self MoveCq: 0 R: SendNumArgsReg. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: SendNumArgsReg. - jumpNext jmpTarget: self Label. - jump3 := self Jump: 0. + self CmpCq: 0 R: SendNumArgsReg. + jump4 := self JumpZero: 0. + jump5 := self JumpNonZero: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - s19 := 896. - self CmpCq: s19 R: SendNumArgsReg. - jumpTrue := self JumpZero: 0. - self MoveCq: 0 R: SendNumArgsReg. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: SendNumArgsReg. - jumpNext jmpTarget: self Label. - currentBlock := self Label. - jump3 jmpTarget: currentBlock. + self CmpCq: 896 R: SendNumArgsReg. + jump1 := self JumpNonZero: 0. currentBlock := self Label. jump2 jmpTarget: currentBlock. - self CmpCq: 1 R: SendNumArgsReg. - jump2 := self JumpNonZero: 0. + jump4 jmpTarget: currentBlock. self MoveRd: DPFPReg0 R: SendNumArgsReg. self RotateLeftCq: 1 R: SendNumArgsReg. self CmpCq: 1 R: SendNumArgsReg. - jump3 := self JumpBelowOrEqual: 0. + jump4 := self JumpBelowOrEqual: 0. self SubCq: 16r7000000000000000 R: SendNumArgsReg. - jump1 := self Jump: 0. + jump2 := self Jump: 0. currentBlock := self Label. - jump3 jmpTarget: currentBlock. + jump4 jmpTarget: currentBlock. currentBlock := self Label. - jump1 jmpTarget: currentBlock. + jump2 jmpTarget: currentBlock. self LogicalShiftLeftCq: 3 R: SendNumArgsReg. self AddCq: 4 R: SendNumArgsReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. - jump1 := self Jump: 0. + jump2 := self Jump: 0. currentBlock := self Label. - jump2 jmpTarget: currentBlock. + jump3 jmpTarget: currentBlock. + jump5 jmpTarget: currentBlock. + jump1 jmpTarget: currentBlock. self MoveAw: objectMemory freeStartAddress R: SendNumArgsReg. self MoveAw: objectMemory freeStartAddress R: ClassReg. self AddCq: 16 R: ClassReg. - s44 := objectMemory getScavengeThreshold. - self CmpCq: s44 R: ClassReg. - jump2 := self JumpAbove: 0. - s47 := 72057594205700130. - self MoveCq: s47 R: ClassReg. + s31 := objectMemory getScavengeThreshold. + self CmpCq: s31 R: ClassReg. + jump1 := self JumpAbove: 0. + s34 := 72057594205700130. + self MoveCq: s34 R: ClassReg. self MoveR: ClassReg M64: 0 r: SendNumArgsReg. self MoveAw: objectMemory freeStartAddress R: ClassReg. self AddCq: 16 R: ClassReg. self MoveR: ClassReg Aw: objectMemory freeStartAddress. self MoveRd: DPFPReg0 M64: 8 r: SendNumArgsReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. currentBlock := self Label. - jump1 jmpTarget: currentBlock. + jump2 jmpTarget: currentBlock. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. currentBlock := self Label. - jump2 jmpTarget: currentBlock. + jump1 jmpTarget: currentBlock. ^ 0 ] @@ -2980,20 +2960,23 @@ SimpleDruidTestRTLCompiler >> gen_primitiveBitAnd [ SimpleDruidTestRTLCompiler >> gen_primitiveBitShift [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 jump2 currentBlock | self MoveR: ReceiverResultReg R: ClassReg. self genLoadArg: 0 into: SendNumArgsReg. self CmpCq: 0 R: SendNumArgsReg. jump1 := self JumpLessOrEqual: 0. self LogicalShiftLeftR: SendNumArgsReg R: ClassReg. - self MoveR: ClassReg R: ReceiverResultReg. - self genPrimReturn. + self MoveR: ClassReg R: SendNumArgsReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. self MoveR: SendNumArgsReg R: SendNumArgsReg. self NegateR: SendNumArgsReg. self LogicalShiftRightR: SendNumArgsReg R: ClassReg. - self MoveR: ClassReg R: ReceiverResultReg. + self MoveR: ClassReg R: SendNumArgsReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -3015,15 +2998,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveBitXor [ SimpleDruidTestRTLCompiler >> gen_primitiveBranchingWithAssigments [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 currentBlock s7 jump2 s3 | self MoveR: ReceiverResultReg R: ClassReg. + s3 := 17. self CmpCq: 0 R: ClassReg. jump1 := self JumpLessOrEqual: 0. - self MoveCq: 17 R: ReceiverResultReg. - self genPrimReturn. + self MoveCq: s3 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 42 R: ReceiverResultReg. + s7 := 42. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -3113,15 +3101,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveCallingMethodReturningConstant [ SimpleDruidTestRTLCompiler >> gen_primitiveCallingMethodWithEarlyReturn [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 0 R: ClassReg. jump1 := self JumpNonZero: 0. - self MoveCq: 42 R: ReceiverResultReg. - self genPrimReturn. + s4 := 42. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 57 R: ReceiverResultReg. + s7 := 57. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -3146,21 +3139,28 @@ SimpleDruidTestRTLCompiler >> gen_primitiveCascadedUint16AtPut [ SimpleDruidTestRTLCompiler >> gen_primitiveCaseOfOtherwiseValue [ "AutoGenerated by Druid" - | jump1 currentBlock | + | s11 s8 jump1 s4 jump3 currentBlock jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 0 R: ClassReg. jump1 := self JumpNonZero: 0. - self MoveCq: 57 R: ReceiverResultReg. - self genPrimReturn. + s4 := 57. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. self CmpCq: 1 R: ClassReg. jump1 := self JumpNonZero: 0. - self MoveCq: 42 R: ReceiverResultReg. - self genPrimReturn. + s8 := 42. + self MoveCq: s8 R: ClassReg. + jump3 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 77 R: ReceiverResultReg. + s11 := 77. + self MoveCq: s11 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + jump3 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -3169,7 +3169,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveCaseOfOtherwiseValue [ SimpleDruidTestRTLCompiler >> gen_primitiveClass [ "AutoGenerated by Druid" - | s32 s87 s2 s56 currentBlock s3 | + | s57 s32 s87 s2 s56 currentBlock s3 | s2 := self methodNumArgs. s2 = 0 ifTrue: [ | jump5 jump3 jump1 jump6 jump4 jump2 | @@ -3333,15 +3333,21 @@ SimpleDruidTestRTLCompiler >> gen_primitiveClassVariable [ SimpleDruidTestRTLCompiler >> gen_primitiveClassVariableWithBranch [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 0 R: ClassReg. jump1 := self JumpNonZero: 0. - self MoveCq: 35 R: ReceiverResultReg. - self genPrimReturn. + s4 := 1. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 36 R: ReceiverResultReg. + s7 := 2. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self AddCq: 34 R: ClassReg. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -3350,15 +3356,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveClassVariableWithBranch [ SimpleDruidTestRTLCompiler >> gen_primitiveConditionWithAnyMask [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self TstCq: 1 R: ClassReg. jump1 := self JumpZero: 0. - self MoveCq: 1 R: ReceiverResultReg. - self genPrimReturn. + s4 := 1. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 2 R: ReceiverResultReg. + s7 := 2. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -3367,15 +3378,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveConditionWithAnyMask [ SimpleDruidTestRTLCompiler >> gen_primitiveConditionWithAnyMaskInverted [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self TstCq: 1 R: ClassReg. jump1 := self JumpZero: 0. - self MoveCq: 1 R: ReceiverResultReg. - self genPrimReturn. + s4 := 1. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 2 R: ReceiverResultReg. + s7 := 2. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -3384,16 +3400,21 @@ SimpleDruidTestRTLCompiler >> gen_primitiveConditionWithAnyMaskInverted [ SimpleDruidTestRTLCompiler >> gen_primitiveConditionWithObjectReference [ "AutoGenerated by Druid" - | jump1 currentBlock s3 | + | s8 jump1 currentBlock jump2 s5 s3 | self MoveR: ReceiverResultReg R: ClassReg. s3 := objectMemory trueObject. self CmpCq: s3 R: ClassReg. jump1 := self JumpAboveOrEqual: 0. - self MoveCq: 1 R: ReceiverResultReg. - self genPrimReturn. + s5 := 1. + self MoveCq: s5 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 2 R: ReceiverResultReg. + s8 := 2. + self MoveCq: s8 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -3412,7 +3433,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveConstantFloatAsInteger [ SimpleDruidTestRTLCompiler >> gen_primitiveDNA [ "AutoGenerated by Druid" - | jump3 jump1 s4 currentBlock s7 jump2 | + | jump1 s22 jump3 s27 currentBlock s15 s7 s4 jump2 s26 s14 s9 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 10 R: ClassReg. jump1 := self JumpLessOrEqual: 0. @@ -3424,21 +3445,36 @@ SimpleDruidTestRTLCompiler >> gen_primitiveDNA [ s7 := 99. self CmpCq: 0 R: ClassReg. jump1 := self JumpLessOrEqual: 0. + s9 := 5. self CmpCq: 7 R: ClassReg. jump3 := self JumpLessOrEqual: 0. self MoveCq: s7 R: ClassReg. currentBlock := self Label. jump2 jmpTarget: currentBlock. - self AddCq: 20 R: ClassReg. - self MoveR: ClassReg R: ReceiverResultReg. - self genPrimReturn. + s14 := 5. + s15 := 15. + self MoveCq: s15 R: SendNumArgsReg. + self MoveCq: s14 R: Extra0Reg. + jump2 := self Jump: 0. currentBlock := self Label. jump3 jmpTarget: currentBlock. - self MoveCq: 146 R: ReceiverResultReg. - self genPrimReturn. + self MoveCq: s9 R: Extra0Reg. + jump3 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 158 R: ReceiverResultReg. + s22 := 17. + self MoveCq: s22 R: Extra0Reg. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + s26 := 99. + s27 := 42. + self MoveCq: s27 R: SendNumArgsReg. + self MoveCq: s26 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self AddR: Extra0Reg R: ClassReg. + self AddR: SendNumArgsReg R: ClassReg. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -3500,9 +3536,9 @@ SimpleDruidTestRTLCompiler >> gen_primitiveDivide [ self DivR: SendNumArgsReg R: ClassReg - Quo: ClassReg - Rem: SendNumArgsReg. - self MoveR: ClassReg R: ReceiverResultReg. + Quo: SendNumArgsReg + Rem: ClassReg. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -3518,9 +3554,9 @@ SimpleDruidTestRTLCompiler >> gen_primitiveDivideByConstant [ self DivR: SendNumArgsReg R: ClassReg - Quo: ClassReg - Rem: SendNumArgsReg. - self MoveR: ClassReg R: ReceiverResultReg. + Quo: SendNumArgsReg + Rem: ClassReg. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -3600,15 +3636,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveDoubleDeferredInline [ SimpleDruidTestRTLCompiler >> gen_primitiveEqualsThan [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 10 R: ClassReg. jump1 := self JumpNonZero: 0. - self MoveCq: 5 R: ReceiverResultReg. - self genPrimReturn. + s4 := 5. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 11 R: ReceiverResultReg. + s7 := 11. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -3659,15 +3700,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveEqualsThanFloats [ SimpleDruidTestRTLCompiler >> gen_primitiveEqualsThanInverted [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 10 R: ClassReg. jump1 := self JumpNonZero: 0. - self MoveCq: 5 R: ReceiverResultReg. - self genPrimReturn. + s4 := 5. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 11 R: ReceiverResultReg. + s7 := 11. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -3916,7 +3962,6 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatAdd [ jump8 jmpTarget: currentBlock. self LogicalShiftLeftCq: 3 R: SendNumArgsReg. self AddCq: 4 R: SendNumArgsReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. jump8 := self Jump: 0. currentBlock := self Label. jump7 jmpTarget: currentBlock. @@ -3933,9 +3978,9 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatAdd [ self AddCq: 16 R: Extra0Reg. self MoveR: Extra0Reg Aw: objectMemory freeStartAddress. self MoveRd: DPFPReg0 M64: 8 r: SendNumArgsReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. currentBlock := self Label. jump8 jmpTarget: currentBlock. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. currentBlock := self Label. jump2 jmpTarget: currentBlock. @@ -3968,7 +4013,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatDivide [ SimpleDruidTestRTLCompiler >> gen_primitiveFloatEqual [ "AutoGenerated by Druid" - | jump1 s86 s83 jump6 jump3 currentBlock jump8 jump5 jump2 jump7 jump4 | + | jump1 jump6 jump3 currentBlock s82 jump8 jump5 s79 jump2 jump7 jump4 | self MoveR: ReceiverResultReg R: ClassReg. self genLoadArg: 0 into: SendNumArgsReg. self MoveR: ClassReg R: Extra0Reg. @@ -4061,26 +4106,24 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatEqual [ jump8 jmpTarget: currentBlock. self CmpRd: DPFPReg1 Rd: DPFPReg0. jump8 := self JumpFPNotEqual: 0. - s83 := objectMemory trueObject. - self MoveCq: s83 R: ReceiverResultReg. - self genPrimReturn. + s79 := objectMemory trueObject. + self MoveCq: s79 R: Extra0Reg. + jump7 := self Jump: 0. currentBlock := self Label. jump8 jmpTarget: currentBlock. - s86 := objectMemory falseObject. - self MoveCq: s86 R: ReceiverResultReg. - self genPrimReturn. - currentBlock := self Label. - jump5 jmpTarget: currentBlock. + s82 := objectMemory falseObject. + self MoveCq: s82 R: Extra0Reg. currentBlock := self Label. - jump1 jmpTarget: currentBlock. + jump7 jmpTarget: currentBlock. + self MoveR: Extra0Reg R: ReceiverResultReg. + self genPrimReturn. currentBlock := self Label. + jump2 jmpTarget: currentBlock. jump3 jmpTarget: currentBlock. - currentBlock := self Label. - jump6 jmpTarget: currentBlock. - currentBlock := self Label. + jump1 jmpTarget: currentBlock. jump4 jmpTarget: currentBlock. - currentBlock := self Label. - jump2 jmpTarget: currentBlock. + jump6 jmpTarget: currentBlock. + jump5 jmpTarget: currentBlock. ^ 0 ] @@ -4236,7 +4279,6 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatMultiply [ jump8 jmpTarget: currentBlock. self LogicalShiftLeftCq: 3 R: SendNumArgsReg. self AddCq: 4 R: SendNumArgsReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. jump8 := self Jump: 0. currentBlock := self Label. jump7 jmpTarget: currentBlock. @@ -4253,9 +4295,9 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatMultiply [ self AddCq: 16 R: Extra0Reg. self MoveR: Extra0Reg Aw: objectMemory freeStartAddress. self MoveRd: DPFPReg0 M64: 8 r: SendNumArgsReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. currentBlock := self Label. jump8 jmpTarget: currentBlock. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. currentBlock := self Label. jump2 jmpTarget: currentBlock. @@ -4272,7 +4314,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatMultiply [ SimpleDruidTestRTLCompiler >> gen_primitiveFloatNotEqual [ "AutoGenerated by Druid" - | jump1 s86 s83 jump6 jump3 currentBlock jump8 jump5 jump2 jump7 jump4 | + | jump1 jump6 jump3 currentBlock s82 jump8 jump5 s79 jump2 jump7 jump4 | self MoveR: ReceiverResultReg R: ClassReg. self genLoadArg: 0 into: SendNumArgsReg. self MoveR: ClassReg R: Extra0Reg. @@ -4365,26 +4407,24 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatNotEqual [ jump8 jmpTarget: currentBlock. self CmpRd: DPFPReg1 Rd: DPFPReg0. jump8 := self JumpFPNotEqual: 0. - s83 := objectMemory falseObject. - self MoveCq: s83 R: ReceiverResultReg. - self genPrimReturn. + s79 := objectMemory falseObject. + self MoveCq: s79 R: Extra0Reg. + jump7 := self Jump: 0. currentBlock := self Label. jump8 jmpTarget: currentBlock. - s86 := objectMemory trueObject. - self MoveCq: s86 R: ReceiverResultReg. - self genPrimReturn. + s82 := objectMemory trueObject. + self MoveCq: s82 R: Extra0Reg. currentBlock := self Label. - jump5 jmpTarget: currentBlock. - currentBlock := self Label. - jump1 jmpTarget: currentBlock. + jump7 jmpTarget: currentBlock. + self MoveR: Extra0Reg R: ReceiverResultReg. + self genPrimReturn. currentBlock := self Label. + jump2 jmpTarget: currentBlock. jump3 jmpTarget: currentBlock. - currentBlock := self Label. - jump6 jmpTarget: currentBlock. - currentBlock := self Label. + jump1 jmpTarget: currentBlock. jump4 jmpTarget: currentBlock. - currentBlock := self Label. - jump2 jmpTarget: currentBlock. + jump6 jmpTarget: currentBlock. + jump5 jmpTarget: currentBlock. ^ 0 ] @@ -4540,7 +4580,6 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatSubtract [ jump8 jmpTarget: currentBlock. self LogicalShiftLeftCq: 3 R: SendNumArgsReg. self AddCq: 4 R: SendNumArgsReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. jump8 := self Jump: 0. currentBlock := self Label. jump7 jmpTarget: currentBlock. @@ -4557,9 +4596,9 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatSubtract [ self AddCq: 16 R: Extra0Reg. self MoveR: Extra0Reg Aw: objectMemory freeStartAddress. self MoveRd: DPFPReg0 M64: 8 r: SendNumArgsReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. currentBlock := self Label. jump8 jmpTarget: currentBlock. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. currentBlock := self Label. jump2 jmpTarget: currentBlock. @@ -4576,7 +4615,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatSubtract [ SimpleDruidTestRTLCompiler >> gen_primitiveFullClosureValue [ "AutoGenerated by Druid" - | s51 s26 currentBlock s2 s3 | + | s23 s44 s2 currentBlock s22 s43 s3 | s2 := self methodNumArgs. s2 = 0 ifTrue: [ | jump1 jump2 jump3 jump4 | @@ -4604,52 +4643,46 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFullClosureValue [ self JumpR: ClassReg. self genPrimReturn. currentBlock := self Label. - jump4 jmpTarget: currentBlock. - currentBlock := self Label. - jump3 jmpTarget: currentBlock. - currentBlock := self Label. - jump2 jmpTarget: currentBlock. - currentBlock := self Label. jump1 jmpTarget: currentBlock. + jump2 jmpTarget: currentBlock. + jump3 jmpTarget: currentBlock. + jump4 jmpTarget: currentBlock. ^ 0 ]. - s26 := self methodNumArgs. - s26 = 1 ifTrue: [ - | jump1 jump2 jump3 jump4 | + s22 := self methodNumArgs. + s22 = 1 ifTrue: [ + | jump4 jump3 jump2 jump1 | self MoveR: ReceiverResultReg R: ClassReg. self genLoadArg: 0 into: SendNumArgsReg. self MoveM64: 24 r: ClassReg R: SendNumArgsReg. self ArithmeticShiftRightCq: 3 R: SendNumArgsReg. self CmpCq: 1 R: SendNumArgsReg. - jump1 := self JumpNonZero: 0. + jump4 := self JumpNonZero: 0. self MoveM64: 16 r: ClassReg R: SendNumArgsReg. self MoveR: SendNumArgsReg R: ClassReg. self AndCq: 7 R: ClassReg. self CmpCq: 0 R: ClassReg. - jump2 := self JumpNonZero: 0. + jump3 := self JumpNonZero: 0. self MoveM64: 0 r: SendNumArgsReg R: ClassReg. self LogicalShiftRightCq: 24 R: ClassReg. self AndCq: 31 R: ClassReg. self CmpCq: 24 R: ClassReg. - jump3 := self JumpBelow: 0. + jump2 := self JumpBelow: 0. self MoveM64: 8 r: SendNumArgsReg R: ClassReg. self AndCq: 1 R: ClassReg. self CmpCq: 0 R: ClassReg. - jump4 := self JumpNonZero: 0. + jump1 := self JumpNonZero: 0. self MoveM64: 8 r: SendNumArgsReg R: ClassReg. self AddCq: self fullBlockEntryOffset R: ClassReg. self JumpR: ClassReg. self genPrimReturn. currentBlock := self Label. jump4 jmpTarget: currentBlock. - currentBlock := self Label. jump3 jmpTarget: currentBlock. - currentBlock := self Label. jump2 jmpTarget: currentBlock. - currentBlock := self Label. jump1 jmpTarget: currentBlock. ^ 0 ]. - s51 := self methodNumArgs. - s51 = 2 ifTrue: [ + s43 := self methodNumArgs. + s43 = 2 ifTrue: [ | jump1 jump2 jump3 jump4 | self MoveR: ReceiverResultReg R: ClassReg. self genLoadArg: 0 into: SendNumArgsReg. @@ -4677,13 +4710,10 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFullClosureValue [ self JumpR: ClassReg. self genPrimReturn. currentBlock := self Label. - jump4 jmpTarget: currentBlock. - currentBlock := self Label. - jump3 jmpTarget: currentBlock. - currentBlock := self Label. - jump2 jmpTarget: currentBlock. - currentBlock := self Label. jump1 jmpTarget: currentBlock. + jump2 jmpTarget: currentBlock. + jump3 jmpTarget: currentBlock. + jump4 jmpTarget: currentBlock. ^ 0 ]. ^ 0 ] @@ -4728,15 +4758,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveGreaterOrEqualThanValue [ SimpleDruidTestRTLCompiler >> gen_primitiveGreaterOrEqualsThan [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 10 R: ClassReg. jump1 := self JumpLess: 0. - self MoveCq: 5 R: ReceiverResultReg. - self genPrimReturn. + s4 := 5. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 11 R: ReceiverResultReg. + s7 := 11. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -4766,15 +4801,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveGreaterOrEqualsThanFloats [ SimpleDruidTestRTLCompiler >> gen_primitiveGreaterOrEqualsThanInverted [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 10 R: ClassReg. jump1 := self JumpGreater: 0. - self MoveCq: 5 R: ReceiverResultReg. - self genPrimReturn. + s4 := 5. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 11 R: ReceiverResultReg. + s7 := 11. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -4783,15 +4823,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveGreaterOrEqualsThanInverted [ SimpleDruidTestRTLCompiler >> gen_primitiveGreaterThan [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 10 R: ClassReg. jump1 := self JumpLessOrEqual: 0. - self MoveCq: 5 R: ReceiverResultReg. - self genPrimReturn. + s4 := 5. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 11 R: ReceiverResultReg. + s7 := 11. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -4818,16 +4863,21 @@ SimpleDruidTestRTLCompiler >> gen_primitiveGreaterThanArgument [ SimpleDruidTestRTLCompiler >> gen_primitiveGreaterThanBitAnd [ "AutoGenerated by Druid" - | jump1 currentBlock | + | s8 jump1 currentBlock jump2 s5 | self MoveR: ReceiverResultReg R: ClassReg. self AndCq: 16rFFFFFFFFFFFFFFFF R: ClassReg. self CmpCq: 1 R: ClassReg. jump1 := self JumpBelowOrEqual: 0. - self MoveCq: 1 R: ReceiverResultReg. - self genPrimReturn. + s5 := 1. + self MoveCq: s5 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 2 R: ReceiverResultReg. + s8 := 2. + self MoveCq: s8 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -4857,15 +4907,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveGreaterThanFloats [ SimpleDruidTestRTLCompiler >> gen_primitiveGreaterThanInverted [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 10 R: ClassReg. jump1 := self JumpGreaterOrEqual: 0. - self MoveCq: 5 R: ReceiverResultReg. - self genPrimReturn. + s4 := 5. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 11 R: ReceiverResultReg. + s7 := 11. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -4910,17 +4965,14 @@ SimpleDruidTestRTLCompiler >> gen_primitiveIdentityHash [ backEnd saveAndRestoreLinkRegAround: [ self CallRT: ceNewHashTrampoline ]. self MoveR: TempReg R: SendNumArgsReg. - self LogicalShiftLeftCq: 3 R: SendNumArgsReg. - self AddCq: 1 R: SendNumArgsReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. jump4 := self Jump: 0. currentBlock := self Label. jump3 jmpTarget: currentBlock. + currentBlock := self Label. + jump4 jmpTarget: currentBlock. self LogicalShiftLeftCq: 3 R: SendNumArgsReg. self AddCq: 1 R: SendNumArgsReg. self MoveR: SendNumArgsReg R: ReceiverResultReg. - currentBlock := self Label. - jump4 jmpTarget: currentBlock. self genPrimReturn. currentBlock := self Label. jump1 jmpTarget: currentBlock. @@ -4932,15 +4984,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveIdentityHash [ SimpleDruidTestRTLCompiler >> gen_primitiveIfFalseIfTrueReturningValue [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 0 R: ClassReg. jump1 := self JumpNonZero: 0. - self MoveCq: 42 R: ReceiverResultReg. - self genPrimReturn. + s4 := 42. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 57 R: ReceiverResultReg. + s7 := 57. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -4949,15 +5006,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveIfFalseIfTrueReturningValue [ SimpleDruidTestRTLCompiler >> gen_primitiveIfTrueIfFalseAssigningValue [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 0 R: ClassReg. jump1 := self JumpNonZero: 0. - self MoveCq: 42 R: ReceiverResultReg. - self genPrimReturn. + s4 := 42. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 57 R: ReceiverResultReg. + s7 := 57. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -4966,15 +5028,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveIfTrueIfFalseAssigningValue [ SimpleDruidTestRTLCompiler >> gen_primitiveIfTrueIfFalseReturningValue [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 0 R: ClassReg. jump1 := self JumpNonZero: 0. - self MoveCq: 42 R: ReceiverResultReg. - self genPrimReturn. + s4 := 42. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 57 R: ReceiverResultReg. + s7 := 57. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -4983,15 +5050,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveIfTrueIfFalseReturningValue [ SimpleDruidTestRTLCompiler >> gen_primitiveIfTrueStatement [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 currentBlock jump2 s5 s3 | self MoveR: ReceiverResultReg R: ClassReg. + s3 := 10. self CmpCq: 0 R: ClassReg. jump1 := self JumpNonZero: 0. - self MoveCq: 42 R: ReceiverResultReg. - self genPrimReturn. + s5 := 42. + self MoveCq: s5 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 10 R: ReceiverResultReg. + self MoveCq: s3 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -5000,27 +5072,23 @@ SimpleDruidTestRTLCompiler >> gen_primitiveIfTrueStatement [ SimpleDruidTestRTLCompiler >> gen_primitiveImmediateAsInteger [ "AutoGenerated by Druid" - | s27 s60 s2 s24 currentBlock s63 s38 s3 | + | s59 s21 s40 s2 s24 currentBlock s56 s41 s3 | s2 := self methodNumArgs. s2 = 0 ifTrue: [ - | jump1 jump2 jump3 | + | jump5 jump3 jump1 jump4 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self TstCq: 1 R: ClassReg. jump1 := self JumpZero: 0. self ArithmeticShiftRightCq: 3 R: ClassReg. self LogicalShiftLeftCq: 3 R: ClassReg. self AddCq: 1 R: ClassReg. - self MoveR: ClassReg R: ReceiverResultReg. - self genPrimReturn. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. self TstCq: 2 R: ClassReg. jump1 := self JumpZero: 0. self LogicalShiftRightCq: 3 R: ClassReg. - self LogicalShiftLeftCq: 3 R: ClassReg. - self AddCq: 1 R: ClassReg. - self MoveR: ClassReg R: ReceiverResultReg. - self genPrimReturn. + jump3 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. self TstCq: 4 R: ClassReg. @@ -5028,45 +5096,43 @@ SimpleDruidTestRTLCompiler >> gen_primitiveImmediateAsInteger [ self MoveR: ClassReg R: SendNumArgsReg. self LogicalShiftRightCq: 4 R: SendNumArgsReg. self TstCq: 8 R: ClassReg. - jump2 := self JumpZero: 0. - s24 := -1152921504606846976. - self MoveCq: s24 R: ClassReg. - jump3 := self Jump: 0. + jump4 := self JumpZero: 0. + s21 := -1152921504606846976. + self MoveCq: s21 R: ClassReg. + jump5 := self Jump: 0. currentBlock := self Label. - jump2 jmpTarget: currentBlock. - s27 := 0. - self MoveCq: s27 R: ClassReg. + jump4 jmpTarget: currentBlock. + s24 := 0. + self MoveCq: s24 R: ClassReg. currentBlock := self Label. - jump3 jmpTarget: currentBlock. + jump5 jmpTarget: currentBlock. self AddR: ClassReg R: SendNumArgsReg. self MoveR: SendNumArgsReg R: ClassReg. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. self LogicalShiftLeftCq: 3 R: ClassReg. self AddCq: 1 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. currentBlock := self Label. jump1 jmpTarget: currentBlock. ^ 0 ]. - s38 := self methodNumArgs. - s38 = 1 ifTrue: [ - | jump1 jump3 jump2 | + s40 := self methodNumArgs. + s40 = 1 ifTrue: [ + | jump5 jump3 jump1 jump4 jump2 | self genLoadArg: 0 into: ClassReg. self TstCq: 1 R: ClassReg. jump1 := self JumpZero: 0. self ArithmeticShiftRightCq: 3 R: ClassReg. - self LogicalShiftLeftCq: 3 R: ClassReg. - self AddCq: 1 R: ClassReg. - self MoveR: ClassReg R: ReceiverResultReg. - self genPrimReturn. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. self TstCq: 2 R: ClassReg. jump1 := self JumpZero: 0. self LogicalShiftRightCq: 3 R: ClassReg. - self LogicalShiftLeftCq: 3 R: ClassReg. - self AddCq: 1 R: ClassReg. - self MoveR: ClassReg R: ReceiverResultReg. - self genPrimReturn. + jump3 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. self TstCq: 4 R: ClassReg. @@ -5074,18 +5140,22 @@ SimpleDruidTestRTLCompiler >> gen_primitiveImmediateAsInteger [ self MoveR: ClassReg R: SendNumArgsReg. self LogicalShiftRightCq: 4 R: SendNumArgsReg. self TstCq: 8 R: ClassReg. - jump3 := self JumpZero: 0. - s60 := -1152921504606846976. - self MoveCq: s60 R: ClassReg. - jump2 := self Jump: 0. + jump5 := self JumpZero: 0. + s56 := -1152921504606846976. + self MoveCq: s56 R: ClassReg. + jump4 := self Jump: 0. currentBlock := self Label. - jump3 jmpTarget: currentBlock. - s63 := 0. - self MoveCq: s63 R: ClassReg. + jump5 jmpTarget: currentBlock. + s59 := 0. + self MoveCq: s59 R: ClassReg. currentBlock := self Label. - jump2 jmpTarget: currentBlock. + jump4 jmpTarget: currentBlock. self AddR: ClassReg R: SendNumArgsReg. self MoveR: SendNumArgsReg R: ClassReg. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. self LogicalShiftLeftCq: 3 R: ClassReg. self AddCq: 1 R: ClassReg. self MoveR: ClassReg R: ReceiverResultReg. @@ -5100,15 +5170,14 @@ SimpleDruidTestRTLCompiler >> gen_primitiveImmediateAsInteger [ SimpleDruidTestRTLCompiler >> gen_primitiveImplicitArgumentBitShiftLeft [ "AutoGenerated by Druid" - | jump1 s10 currentBlock s4 | + | jump1 s4 s10 currentBlock jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 0 R: ClassReg. jump1 := self JumpLessOrEqual: 0. s4 := 1. self MoveCq: s4 R: SendNumArgsReg. self LogicalShiftLeftR: ClassReg R: SendNumArgsReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. - self genPrimReturn. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. self MoveR: ClassReg R: SendNumArgsReg. @@ -5116,7 +5185,10 @@ SimpleDruidTestRTLCompiler >> gen_primitiveImplicitArgumentBitShiftLeft [ s10 := 1. self MoveCq: s10 R: ClassReg. self LogicalShiftRightR: SendNumArgsReg R: ClassReg. - self MoveR: ClassReg R: ReceiverResultReg. + self MoveR: ClassReg R: SendNumArgsReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -5203,9 +5275,9 @@ SimpleDruidTestRTLCompiler >> gen_primitiveIntegerDivide [ self DivR: SendNumArgsReg R: ClassReg - Quo: ClassReg - Rem: SendNumArgsReg. - self MoveR: ClassReg R: ReceiverResultReg. + Quo: SendNumArgsReg + Rem: ClassReg. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -5221,9 +5293,9 @@ SimpleDruidTestRTLCompiler >> gen_primitiveIntegerDivideByConstant [ self DivR: SendNumArgsReg R: ClassReg - Quo: ClassReg - Rem: SendNumArgsReg. - self MoveR: ClassReg R: ReceiverResultReg. + Quo: SendNumArgsReg + Rem: ClassReg. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -5245,17 +5317,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveIntegerRawBitsAsFloat [ SimpleDruidTestRTLCompiler >> gen_primitiveIsIntegerObject [ "AutoGenerated by Druid" - | s7 jump1 currentBlock s4 | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self TstCq: 1 R: ClassReg. jump1 := self JumpZero: 0. s4 := objectMemory trueObject. - self MoveCq: s4 R: ReceiverResultReg. - self genPrimReturn. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. s7 := objectMemory falseObject. - self MoveCq: s7 R: ReceiverResultReg. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -5312,15 +5387,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveLessOrEqualThanValue [ SimpleDruidTestRTLCompiler >> gen_primitiveLessOrEqualsThan [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 10 R: ClassReg. jump1 := self JumpGreater: 0. - self MoveCq: 5 R: ReceiverResultReg. - self genPrimReturn. + s4 := 5. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 11 R: ReceiverResultReg. + s7 := 11. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -5350,15 +5430,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveLessOrEqualsThanFloats [ SimpleDruidTestRTLCompiler >> gen_primitiveLessOrEqualsThanInverted [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 10 R: ClassReg. jump1 := self JumpLess: 0. - self MoveCq: 5 R: ReceiverResultReg. - self genPrimReturn. + s4 := 5. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 11 R: ReceiverResultReg. + s7 := 11. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -5367,15 +5452,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveLessOrEqualsThanInverted [ SimpleDruidTestRTLCompiler >> gen_primitiveLessThan [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 10 R: ClassReg. jump1 := self JumpGreaterOrEqual: 0. - self MoveCq: 5 R: ReceiverResultReg. - self genPrimReturn. + s4 := 5. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 11 R: ReceiverResultReg. + s7 := 11. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -5423,15 +5513,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveLessThanFloats [ SimpleDruidTestRTLCompiler >> gen_primitiveLessThanInverted [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 10 R: ClassReg. jump1 := self JumpLessOrEqual: 0. - self MoveCq: 5 R: ReceiverResultReg. - self genPrimReturn. + s4 := 5. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 11 R: ReceiverResultReg. + s7 := 11. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -5557,9 +5652,9 @@ SimpleDruidTestRTLCompiler >> gen_primitiveMod [ self DivR: SendNumArgsReg R: ClassReg - Quo: ClassReg - Rem: SendNumArgsReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. + Quo: SendNumArgsReg + Rem: ClassReg. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -5575,9 +5670,9 @@ SimpleDruidTestRTLCompiler >> gen_primitiveModByConstant [ self DivR: SendNumArgsReg R: ClassReg - Quo: ClassReg - Rem: SendNumArgsReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. + Quo: SendNumArgsReg + Rem: ClassReg. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -5636,18 +5731,21 @@ SimpleDruidTestRTLCompiler >> gen_primitiveMultiplyInverted [ SimpleDruidTestRTLCompiler >> gen_primitiveMultiplyWithOverflow [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 jump2 currentBlock s8 | self MoveR: ReceiverResultReg R: ClassReg. self genLoadArg: 0 into: SendNumArgsReg. self ArithmeticShiftRightCq: 3 R: ClassReg. self SubCq: 1 R: SendNumArgsReg. self MulR: ClassReg R: SendNumArgsReg. jump1 := self JumpMultiplyNoOverflow: 0. - self MoveCq: 99 R: ReceiverResultReg. - self genPrimReturn. + s8 := 99. + self MoveCq: s8 R: SendNumArgsReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. self AddCq: 1 R: SendNumArgsReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive @@ -5670,15 +5768,17 @@ SimpleDruidTestRTLCompiler >> gen_primitiveNegated [ SimpleDruidTestRTLCompiler >> gen_primitiveNew [ "AutoGenerated by Druid" - | jump1 s28 jump6 b361 jump3 currentBlock jump5 jump2 s17 jump7 jump4 | - self SubCq: 8 R: SPReg. - self MoveR: ReceiverResultReg R: ClassReg. - self MoveM64: 24 r: ClassReg R: Extra3Reg. + | jump1 s28 jump6 jump3 b349 currentBlock jump8 jump5 jump2 s17 jump7 jump4 | + self SubCq: 16 R: SPReg. + self MoveR: ReceiverResultReg R: Extra3Reg. self MoveR: Extra3Reg Mw: 0 r: SPReg. self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveM64: 24 r: Extra3Reg R: Extra3Reg. + self MoveR: Extra3Reg Mw: 8 r: SPReg. + self MoveMw: 8 r: SPReg R: Extra3Reg. self ArithmeticShiftRightCq: 3 R: Extra3Reg. - self MoveR: Extra3Reg Mw: 0 r: SPReg. - self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveR: Extra3Reg Mw: 8 r: SPReg. + self MoveMw: 8 r: SPReg R: Extra3Reg. self MoveR: Extra3Reg R: Extra0Reg. self LogicalShiftRightCq: 16 R: Extra0Reg. self AndCq: 31 R: Extra0Reg. @@ -5688,85 +5788,103 @@ SimpleDruidTestRTLCompiler >> gen_primitiveNew [ jump2 := self JumpNonZero: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveM32: 4 r: ClassReg R: ClassReg. - self AndCq: 16rFFFFFFFF R: ClassReg. - self AndCq: 16r3FFFFF R: ClassReg. - self CmpCq: 0 R: ClassReg. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveM32: 4 r: Extra3Reg R: Extra1Reg. + self AndCq: 16rFFFFFFFF R: Extra1Reg. + self AndCq: 16r3FFFFF R: Extra1Reg. + self CmpCq: 0 R: Extra1Reg. jump1 := self JumpZero: 0. - self CmpCq: 0 R: ClassReg. + self CmpCq: 0 R: Extra1Reg. jump3 := self JumpBelow: 0. - self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveMw: 8 r: SPReg R: Extra3Reg. self AndCq: 16rFFFF R: Extra3Reg. - self MoveR: Extra3Reg Mw: 0 r: SPReg. - self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveR: Extra3Reg Mw: 8 r: SPReg. + self MoveMw: 8 r: SPReg R: Extra3Reg. self CmpCq: 255 R: Extra3Reg. jump4 := self JumpAboveOrEqual: 0. - self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveMw: 8 r: SPReg R: Extra3Reg. self CmpCq: 1 R: Extra3Reg. jump5 := self JumpAboveOrEqual: 0. s17 := 8. - self MoveCq: s17 R: Extra1Reg. + self MoveCq: s17 R: Extra2Reg. jump6 := self Jump: 0. currentBlock := self Label. jump5 jmpTarget: currentBlock. - self MoveMw: 0 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg R: Extra1Reg. - self LogicalShiftLeftCq: 3 R: Extra1Reg. + self MoveMw: 8 r: SPReg R: Extra3Reg. + self MoveR: Extra3Reg R: Extra2Reg. + self LogicalShiftLeftCq: 3 R: Extra2Reg. currentBlock := self Label. jump6 jmpTarget: currentBlock. - self AddCq: 8 R: Extra1Reg. - self MoveAw: objectMemory freeStartAddress R: Extra2Reg. - self AddR: Extra1Reg R: Extra2Reg. + self AddCq: 8 R: Extra2Reg. + self MoveAw: objectMemory freeStartAddress R: ClassReg. + self AddR: Extra2Reg R: ClassReg. s28 := objectMemory getScavengeThreshold. - self CmpCq: s28 R: Extra2Reg. + self CmpCq: s28 R: ClassReg. jump6 := self JumpBelowOrEqual: 0. - self CmpCq: s28 R: Extra2Reg. + self CmpCq: s28 R: ClassReg. jump5 := self JumpAbove: 0. + self MoveAw: objectMemory freeStartAddress R: ClassReg. + jump7 := self Jump: 0. currentBlock := self Label. jump6 jmpTarget: currentBlock. - self MoveAw: objectMemory freeStartAddress R: Extra2Reg. - self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveAw: objectMemory freeStartAddress R: ClassReg. + currentBlock := self Label. + jump7 jmpTarget: currentBlock. + self MoveMw: 8 r: SPReg R: Extra3Reg. self MoveR: Extra3Reg R: SendNumArgsReg. self LogicalShiftLeftCq: 56 R: SendNumArgsReg. self LogicalShiftLeftCq: 24 R: Extra0Reg. self AddR: Extra0Reg R: SendNumArgsReg. - self AddR: ClassReg R: SendNumArgsReg. + self AddR: Extra1Reg R: SendNumArgsReg. self OrCq: 0 R: SendNumArgsReg. - self MoveR: SendNumArgsReg M64: 0 r: Extra2Reg. + self MoveR: SendNumArgsReg M64: 0 r: ClassReg. self MoveAw: objectMemory freeStartAddress R: SendNumArgsReg. - self AddR: Extra1Reg R: SendNumArgsReg. + self AddR: Extra2Reg R: SendNumArgsReg. self MoveR: SendNumArgsReg Aw: objectMemory freeStartAddress. - self genMoveConstant: objectMemory nilObject R: SendNumArgsReg. - self MoveR: Extra2Reg R: Extra1Reg. - self AddCq: 8 R: Extra1Reg. + self CmpCq: 0 R: ClassReg. + jump7 := self JumpNonZero: 0. self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveR: Extra3Reg R: SendNumArgsReg. + jump6 := self Jump: 0. + currentBlock := self Label. + jump7 jmpTarget: currentBlock. + self genMoveConstant: objectMemory nilObject R: SendNumArgsReg. + self MoveR: ClassReg R: Extra2Reg. + self AddCq: 8 R: Extra2Reg. + self MoveMw: 8 r: SPReg R: Extra3Reg. self LogicalShiftLeftCq: 3 R: Extra3Reg. - self MoveR: Extra3Reg Mw: 0 r: SPReg. - self MoveR: Extra2Reg R: ClassReg. - self MoveMw: 0 r: SPReg R: Extra3Reg. - self AddR: Extra3Reg R: ClassReg. - self AddCq: 8 R: ClassReg. - self SubCq: 1 R: ClassReg. - b361 := self Label. - self CmpR: Extra1Reg R: ClassReg. - jump6 := self JumpLess: 0. - self MoveR: SendNumArgsReg M64: 0 r: Extra1Reg. - self MoveR: Extra1Reg R: Extra0Reg. + self MoveR: Extra3Reg Mw: 8 r: SPReg. + self MoveR: ClassReg R: Extra1Reg. + self MoveMw: 8 r: SPReg R: Extra3Reg. + self AddR: Extra3Reg R: Extra1Reg. + self AddCq: 8 R: Extra1Reg. + self SubCq: 1 R: Extra1Reg. + b349 := self Label. + self CmpR: Extra2Reg R: Extra1Reg. + jump7 := self JumpLess: 0. + self MoveR: SendNumArgsReg M64: 0 r: Extra2Reg. + self MoveR: Extra2Reg R: Extra0Reg. self AddCq: 8 R: Extra0Reg. - self MoveR: Extra0Reg R: Extra1Reg. - jump7 := self Jump: b361. + self MoveR: Extra0Reg R: Extra2Reg. + jump8 := self Jump: b349. currentBlock := self Label. - jump6 jmpTarget: currentBlock. - self MoveR: Extra2Reg R: ReceiverResultReg. - self AddCq: 8 R: SPReg. + jump7 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. + self AddCq: 16 R: SPReg. self genPrimReturn. currentBlock := self Label. jump2 jmpTarget: currentBlock. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveR: Extra3Reg R: SendNumArgsReg. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + self MoveR: SendNumArgsReg R: ReceiverResultReg. + currentBlock := self Label. jump1 jmpTarget: currentBlock. jump3 jmpTarget: currentBlock. jump4 jmpTarget: currentBlock. jump5 jmpTarget: currentBlock. - self AddCq: 8 R: SPReg. + self AddCq: 16 R: SPReg. ^ 0 ] @@ -6110,11 +6228,13 @@ SimpleDruidTestRTLCompiler >> gen_primitiveNextUint16At [ SimpleDruidTestRTLCompiler >> gen_primitiveNoopLoopWithInvariant [ "AutoGenerated by Druid" - | jump3 jump1 currentBlock b18 jump2 | + | s8 jump1 jump3 currentBlock b18 jump2 s3 | self MoveR: ReceiverResultReg R: ClassReg. + s3 := 3. self CmpCq: 10 R: ClassReg. jump1 := self JumpGreaterOrEqual: 0. b18 := self Label. + s8 := 5. self MoveR: ClassReg R: SendNumArgsReg. self AddCq: 1 R: SendNumArgsReg. self CmpCq: 10 R: SendNumArgsReg. @@ -6123,11 +6243,14 @@ SimpleDruidTestRTLCompiler >> gen_primitiveNoopLoopWithInvariant [ jump3 := self Jump: b18. currentBlock := self Label. jump2 jmpTarget: currentBlock. - self MoveCq: 5 R: ReceiverResultReg. - self genPrimReturn. + self MoveCq: s8 R: SendNumArgsReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 3 R: ReceiverResultReg. + self MoveCq: s3 R: SendNumArgsReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -6136,15 +6259,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveNoopLoopWithInvariant [ SimpleDruidTestRTLCompiler >> gen_primitiveNotEqualsThan [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 10 R: ClassReg. jump1 := self JumpZero: 0. - self MoveCq: 5 R: ReceiverResultReg. - self genPrimReturn. + s4 := 5. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 11 R: ReceiverResultReg. + s7 := 11. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -6174,15 +6302,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveNotEqualsThanFloats [ SimpleDruidTestRTLCompiler >> gen_primitiveNotEqualsThanInverted [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 10 R: ClassReg. jump1 := self JumpZero: 0. - self MoveCq: 5 R: ReceiverResultReg. - self genPrimReturn. + s4 := 5. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 11 R: ReceiverResultReg. + s7 := 11. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -6191,21 +6324,24 @@ SimpleDruidTestRTLCompiler >> gen_primitiveNotEqualsThanInverted [ SimpleDruidTestRTLCompiler >> gen_primitiveOr [ "AutoGenerated by Druid" - | jump1 currentBlock | + | s8 jump1 currentBlock jump2 s5 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 5 R: ClassReg. - jump1 := self JumpGreaterOrEqual: 0. - self MoveCq: 42 R: ReceiverResultReg. - self genPrimReturn. + jump1 := self JumpLess: 0. + self CmpCq: 10 R: ClassReg. + jump2 := self JumpLessOrEqual: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self CmpCq: 10 R: ClassReg. - jump1 := self JumpLessOrEqual: 0. - self MoveCq: 42 R: ReceiverResultReg. - self genPrimReturn. + s5 := 42. + self MoveCq: s5 R: ClassReg. + jump1 := self Jump: 0. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + s8 := 10. + self MoveCq: s8 R: ClassReg. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 10 R: ReceiverResultReg. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -6344,21 +6480,33 @@ SimpleDruidTestRTLCompiler >> gen_primitiveRotateLeft [ SimpleDruidTestRTLCompiler >> gen_primitiveSandclock [ "AutoGenerated by Druid" - | jump1 currentBlock | + | s16 s4 s12 currentBlock jump1 s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 10 R: ClassReg. jump1 := self JumpLessOrEqual: 0. - self MoveCq: 6 R: ReceiverResultReg. - self genPrimReturn. + s4 := 1. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. + s7 := 99. self CmpCq: 0 R: ClassReg. jump1 := self JumpLessOrEqual: 0. - self MoveCq: 104 R: ReceiverResultReg. - self genPrimReturn. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + s12 := 5. + self MoveCq: s12 R: SendNumArgsReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 116 R: ReceiverResultReg. + s16 := 17. + self MoveCq: s16 R: SendNumArgsReg. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self AddR: SendNumArgsReg R: ClassReg. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -6367,7 +6515,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveSandclock [ SimpleDruidTestRTLCompiler >> gen_primitiveSize [ "AutoGenerated by Druid" - | jump1 jump4 jumpNext jump6 jump3 currentBlock jump8 jump5 jumpTrue s107 jump2 s14 jump7 s138 | + | jump1 jumpNext jump6 jump3 s131 currentBlock s113 jump8 jump5 jumpTrue s107 jump2 s14 jump7 jump4 | self MoveR: ReceiverResultReg R: ClassReg. self MoveR: ClassReg R: Extra1Reg. self CmpCq: 7 R: Extra1Reg. @@ -6509,21 +6657,14 @@ SimpleDruidTestRTLCompiler >> gen_primitiveSize [ jump7 := self JumpNonZero: 0. currentBlock := self Label. jump8 jmpTarget: currentBlock. - self SubCq: 0 R: Extra2Reg. - self MoveR: Extra2Reg R: SendNumArgsReg. - self LogicalShiftLeftCq: 3 R: SendNumArgsReg. - self AddCq: 1 R: SendNumArgsReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. + s113 := 0. + self MoveCq: s113 R: SendNumArgsReg. jump8 := self Jump: 0. currentBlock := self Label. jump7 jmpTarget: currentBlock. self CmpCq: 2 R: Extra0Reg. jump7 := self JumpAboveOrEqual: 0. - self SubR: Extra2Reg R: Extra2Reg. self MoveR: Extra2Reg R: SendNumArgsReg. - self LogicalShiftLeftCq: 3 R: SendNumArgsReg. - self AddCq: 1 R: SendNumArgsReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. jump4 := self Jump: 0. currentBlock := self Label. jump7 jmpTarget: currentBlock. @@ -6546,9 +6687,9 @@ SimpleDruidTestRTLCompiler >> gen_primitiveSize [ jump3 jmpTarget: currentBlock. self MoveR: SendNumArgsReg R: ClassReg. self LogicalShiftRightCq: 10 R: ClassReg. - s138 := objectMemory hiddenRootsObject. + s131 := objectMemory hiddenRootsObject. self LogicalShiftLeftCq: 3 R: ClassReg. - self AddCq: s138 R: ClassReg. + self AddCq: s131 R: ClassReg. self MoveM64: 8 r: ClassReg R: ClassReg. self genMoveConstant: objectMemory nilObject R: Extra0Reg. self CmpR: Extra0Reg R: ClassReg. @@ -6570,14 +6711,15 @@ SimpleDruidTestRTLCompiler >> gen_primitiveSize [ self MoveM64: 24 r: SendNumArgsReg R: Extra0Reg. self ArithmeticShiftRightCq: 3 R: Extra0Reg. self AndCq: 16rFFFF R: Extra0Reg. - self SubR: Extra0Reg R: Extra2Reg. + self MoveR: Extra0Reg R: SendNumArgsReg. + currentBlock := self Label. + jump8 jmpTarget: currentBlock. + jump4 jmpTarget: currentBlock. + self SubR: SendNumArgsReg R: Extra2Reg. self MoveR: Extra2Reg R: Extra0Reg. self LogicalShiftLeftCq: 3 R: Extra0Reg. self AddCq: 1 R: Extra0Reg. self MoveR: Extra0Reg R: ReceiverResultReg. - currentBlock := self Label. - jump8 jmpTarget: currentBlock. - jump4 jmpTarget: currentBlock. self genPrimReturn. currentBlock := self Label. jump2 jmpTarget: currentBlock. @@ -6653,17 +6795,21 @@ SimpleDruidTestRTLCompiler >> gen_primitiveSmallThan [ SimpleDruidTestRTLCompiler >> gen_primitiveSubWithOverflow [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 jump2 currentBlock s7 | self MoveR: ReceiverResultReg R: ClassReg. self genLoadArg: 0 into: SendNumArgsReg. self AddCq: -1 R: SendNumArgsReg. self SubR: SendNumArgsReg R: ClassReg. jump1 := self JumpNoOverflow: 0. - self MoveCq: 99 R: ReceiverResultReg. - self genPrimReturn. + s7 := 99. + self MoveCq: s7 R: SendNumArgsReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveR: ClassReg R: ReceiverResultReg. + self MoveR: ClassReg R: SendNumArgsReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -6672,17 +6818,21 @@ SimpleDruidTestRTLCompiler >> gen_primitiveSubWithOverflow [ SimpleDruidTestRTLCompiler >> gen_primitiveSumWithOverflow [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 jump2 currentBlock s7 | self MoveR: ReceiverResultReg R: ClassReg. self genLoadArg: 0 into: SendNumArgsReg. self AddCq: -1 R: ClassReg. self AddR: SendNumArgsReg R: ClassReg. jump1 := self JumpNoOverflow: 0. - self MoveCq: 99 R: ReceiverResultReg. - self genPrimReturn. + s7 := 99. + self MoveCq: s7 R: SendNumArgsReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveR: ClassReg R: ReceiverResultReg. + self MoveR: ClassReg R: SendNumArgsReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -6830,15 +6980,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveWithConditionalCompilation [ SimpleDruidTestRTLCompiler >> gen_primitiveWithDeadCode [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 0 R: ClassReg. jump1 := self JumpNonZero: 0. - self MoveCq: 42 R: ReceiverResultReg. - self genPrimReturn. + s4 := 42. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 55 R: ReceiverResultReg. + s7 := 55. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -6866,15 +7021,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveWithIfAssigningValue [ SimpleDruidTestRTLCompiler >> gen_primitiveWithIfNilIfNotNilStatement [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 0 R: ClassReg. jump1 := self JumpLessOrEqual: 0. - self MoveCq: 17 R: ReceiverResultReg. - self genPrimReturn. + s4 := 17. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 42 R: ReceiverResultReg. + s7 := 42. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -6883,15 +7043,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveWithIfNilIfNotNilStatement [ SimpleDruidTestRTLCompiler >> gen_primitiveWithIfNotNilIfNilStatement [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 0 R: ClassReg. jump1 := self JumpLessOrEqual: 0. - self MoveCq: 17 R: ReceiverResultReg. - self genPrimReturn. + s4 := 17. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 42 R: ReceiverResultReg. + s7 := 42. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -6900,15 +7065,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveWithIfNotNilIfNilStatement [ SimpleDruidTestRTLCompiler >> gen_primitiveWithIfNotNilIfNilStatementWithArgument [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 0 R: ClassReg. jump1 := self JumpLessOrEqual: 0. - self MoveCq: 17 R: ReceiverResultReg. - self genPrimReturn. + s4 := 17. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 42 R: ReceiverResultReg. + s7 := 42. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -6917,15 +7087,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveWithIfNotNilIfNilStatementWithArgumen SimpleDruidTestRTLCompiler >> gen_primitiveWithIfNotNilStatement [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 s4 currentBlock s7 jump2 | self MoveR: ReceiverResultReg R: ClassReg. self CmpCq: 0 R: ClassReg. jump1 := self JumpLessOrEqual: 0. - self MoveCq: 17 R: ReceiverResultReg. - self genPrimReturn. + s4 := 17. + self MoveCq: s4 R: ClassReg. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 42 R: ReceiverResultReg. + s7 := 42. + self MoveCq: s7 R: ClassReg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -6976,17 +7151,19 @@ SimpleDruidTestRTLCompiler >> gen_primitiveWithSequentialExitPoint [ SimpleDruidTestRTLCompiler >> gen_primitiveWithTwoArgs [ "AutoGenerated by Druid" - | jump1 currentBlock | + | jump1 jump2 currentBlock | self MoveR: ReceiverResultReg R: ClassReg. self genLoadArg: 0 into: SendNumArgsReg. self genLoadArg: 1 into: Extra0Reg. self CmpCq: 0 R: ClassReg. jump1 := self JumpLessOrEqual: 0. - self MoveR: Extra0Reg R: ReceiverResultReg. - self genPrimReturn. + jump2 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveR: SendNumArgsReg R: ReceiverResultReg. + self MoveR: SendNumArgsReg R: Extra0Reg. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: Extra0Reg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] diff --git a/Druid/DRCPSEdge.class.st b/Druid/DRCPSEdge.class.st index e0bb1ba0..2a4578ad 100644 --- a/Druid/DRCPSEdge.class.st +++ b/Druid/DRCPSEdge.class.st @@ -291,7 +291,7 @@ DRCPSEdge >> visitClosureActivation: aDRClosureActivation [ { #category : #visiting } DRCPSEdge >> visitClosureCreation: aDRClosureCreation [ - "Nothing" + ^ nil ] { #category : #visiting } diff --git a/Druid/DRCogitCodeGenerator.class.st b/Druid/DRCogitCodeGenerator.class.st index 20c2172d..43432f8d 100644 --- a/Druid/DRCogitCodeGenerator.class.st +++ b/Druid/DRCogitCodeGenerator.class.st @@ -1110,8 +1110,8 @@ DRCogitCodeGenerator >> visitLoad: aDRLoad [ { #category : #visiting } DRCogitCodeGenerator >> visitLoadStackValue: aDRLoadStackValue [ - "cogit MoveMw: 0 r: SPReg R: TempReg" - self haltIf: [ aDRLoadStackValue operand1 value > 0 ]. + + "cogit MoveMw: index r: SPReg R: TempReg" generatorMethodBuilder addStatement: (RBMessageNode receiver: RBVariableNode selfNode selector: #MoveMw:r:R: diff --git a/Druid/DRCogitSimpleStackGenerator.class.st b/Druid/DRCogitSimpleStackGenerator.class.st index 7ac62635..b99a1f96 100644 --- a/Druid/DRCogitSimpleStackGenerator.class.st +++ b/Druid/DRCogitSimpleStackGenerator.class.st @@ -157,6 +157,12 @@ DRCogitSimpleStackGenerator >> visitClosureCreation: aDRClosureCreation [ copy acceptVisitor: self ] +{ #category : #visiting } +DRCogitSimpleStackGenerator >> visitCogitSendMarshall: aDRCogitSendMarshall [ + + "Avoid marshalling in SimpleStack" +] + { #category : #visiting } DRCogitSimpleStackGenerator >> visitContinueNextBytecode: aDRContinueNextBytecode [ @@ -180,6 +186,13 @@ DRCogitSimpleStackGenerator >> visitDeoptimize: aDRDeoptimize [ selector: #deoptimize) ] +{ #category : #visiting } +DRCogitSimpleStackGenerator >> visitFlushStack: aDRFlushStack [ + + "Nothing! There are not sym stack on simple stack VMs." + "TODO: Avoid DRFlushStack instructions on primitive meta-compilation" +] + { #category : #visiting } DRCogitSimpleStackGenerator >> visitJITMessageSend: aDRMessageSend [ "self genMarshalledSend: selectorIndex numArgs: numArgs sendTable: aSendTable" @@ -224,12 +237,12 @@ DRCogitSimpleStackGenerator >> visitLoadStackPointer: aDRLoadStackPointer [ { #category : #visiting } DRCogitSimpleStackGenerator >> visitPop: aDRPop [ - aDRPop numberOfPoppedElements > 1 ifTrue: [ self halt ]. + aDRPop numberOfPoppedElements isNumber ifFalse: [ self halt ]. generatorMethodBuilder addStatement: (RBMessageNode receiver: RBVariableNode selfNode - selector: #PopR: - arguments: { (RBVariableNode named: aDRPop result name) }) + selector: #PopN: + arguments: { RBLiteralNode value: aDRPop numberOfPoppedElements }) ] { #category : #visiting } diff --git a/Druid/DRStackInstruction.class.st b/Druid/DRStackInstruction.class.st index 1f42a313..931032ad 100644 --- a/Druid/DRStackInstruction.class.st +++ b/Druid/DRStackInstruction.class.st @@ -66,6 +66,18 @@ DRStackInstruction >> removeStackDependent: aStackDependent [ stackDependents := stackDependents copyWithout: aStackDependent ] +{ #category : #accessing } +DRStackInstruction >> replaceDependency: anOperand by: anotherOperand [ + + (self stackDependencies asArray includes: anOperand) ifTrue: [ + anOperand replaceBy: anotherOperand. + self stackDependencies: (self stackDependencies asArray copyWithout: anOperand). + self stackDependencies add: anotherOperand. + ^ self ]. + + super replaceDependency: anOperand by: anotherOperand +] + { #category : #dependencies } DRStackInstruction >> shiftStackAccessBy: anInteger [ From f47cd377443de27303a4bcee3b0a345e4dab8f3a Mon Sep 17 00:00:00 2001 From: palumbon Date: Thu, 19 Sep 2024 15:38:19 +0200 Subject: [PATCH 02/20] Generate all bytecodes and primitives! --- Druid/DRInterpreterToCompiler.class.st | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/Druid/DRInterpreterToCompiler.class.st b/Druid/DRInterpreterToCompiler.class.st index 7a73ac2e..7658ffd2 100644 --- a/Druid/DRInterpreterToCompiler.class.st +++ b/Druid/DRInterpreterToCompiler.class.st @@ -164,12 +164,8 @@ DRInterpreterToCompiler class >> generateDruidJITModelOn: targetClass superclass (self fromInterpreterClass: CogVMSimulatorLSB) doFailOnFirst; - selectPrimitives: [ :e | - ((primitives indexOf: e selector) between: 0 and: 54) and: [ - primitives includes: e selector ] ]; - selectBytecodes: [ :e | - (e bytecodeNumberStart between: 0 and: 255) and: [ - bytecodes includes: e bytecodeNumberStart ] ]; + selectPrimitives: [ :e | primitives includes: e selector ]; + selectBytecodes: [ :e | bytecodes includes: e bytecodeNumberStart ]; targetClass: targetClass; targetSuperclass: aSuperclass; compilerOptions: options; From 07f3126ca726b88fd7ce233c5531722a3a8a8414 Mon Sep 17 00:00:00 2001 From: palumbon Date: Thu, 19 Sep 2024 15:38:55 +0200 Subject: [PATCH 03/20] Fix flushStack generation based on Simple or STRM --- Druid/DRCogitBytecodeCodeGenerator.class.st | 9 --------- Druid/DRCogitStackToRegisterMappingGenerator.class.st | 9 +++++++++ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/Druid/DRCogitBytecodeCodeGenerator.class.st b/Druid/DRCogitBytecodeCodeGenerator.class.st index 45f3ef9a..adae3df0 100644 --- a/Druid/DRCogitBytecodeCodeGenerator.class.st +++ b/Druid/DRCogitBytecodeCodeGenerator.class.st @@ -11,12 +11,3 @@ DRCogitBytecodeCodeGenerator >> visitCall: aDRCall [ aDRCall isMapped ifTrue: [ self assert: aDRCall controlFlowGraph hasAnnotatedBytecode ] ] - -{ #category : #visiting } -DRCogitBytecodeCodeGenerator >> visitFlushStack: aDRFlushStack [ - - generatorMethodBuilder addStatement: (RBMessageNode - receiver: RBVariableNode selfNode - selector: #ssFlushStackExceptTop: - arguments: { (RBLiteralValueNode value: aDRFlushStack operand1 value) }) -] diff --git a/Druid/DRCogitStackToRegisterMappingGenerator.class.st b/Druid/DRCogitStackToRegisterMappingGenerator.class.st index 87bf7ad2..aa9250e5 100644 --- a/Druid/DRCogitStackToRegisterMappingGenerator.class.st +++ b/Druid/DRCogitStackToRegisterMappingGenerator.class.st @@ -168,6 +168,15 @@ DRCogitStackToRegisterMappingGenerator >> visitDeoptimize: aDRDeoptimize [ markDeadCode := true. ] +{ #category : #visiting } +DRCogitStackToRegisterMappingGenerator >> visitFlushStack: aDRFlushStack [ + + generatorMethodBuilder addStatement: (RBMessageNode + receiver: RBVariableNode selfNode + selector: #ssFlushStackExceptTop: + arguments: { (RBLiteralValueNode value: aDRFlushStack operand1 value) }) +] + { #category : #visiting } DRCogitStackToRegisterMappingGenerator >> visitJITMessageSend: aDRMessageSend [ "self genMarshalledSend: selectorIndex numArgs: numArgs sendTable: aSendTable" From c34429068f64aa81b61554e1ed428313364b361e Mon Sep 17 00:00:00 2001 From: palumbon Date: Mon, 23 Sep 2024 17:10:07 +0200 Subject: [PATCH 04/20] Check if compiler isSimpleStack on send generation --- Druid/DRBytecodeIRGenerator.class.st | 28 ++++++++++--------- Druid/SimpleStackBasedCogit.extension.st | 6 ++++ .../StackToRegisterMappingCogit.extension.st | 6 ++++ 3 files changed, 27 insertions(+), 13 deletions(-) diff --git a/Druid/DRBytecodeIRGenerator.class.st b/Druid/DRBytecodeIRGenerator.class.st index ac1d2575..0428e3b7 100644 --- a/Druid/DRBytecodeIRGenerator.class.st +++ b/Druid/DRBytecodeIRGenerator.class.st @@ -360,19 +360,21 @@ DRBytecodeIRGenerator >> interpretSendWith: aRBMessageNode specialSelector: isSp argumentCount asDRValue. sendTableName asDRValue }. send addBefore: (marshall := DRCogitSendMarshall send: send). - - "If all arguments pass on registers, then we need to pop them from the stack, but the marshall already unspill them if spilled" - argumentCount simpleConstantFold asDRValue isConstant - ifTrue: [ - marshall addBefore: (controlFlowGraph instructionFactory flushStackExceptTop: argumentCount simpleConstantFold + 1). - argumentCount simpleConstantFold + 1 timesRepeat: [ "Receiver" - self - pop: 1 - unspilled: argumentCount simpleConstantFold <= self numRegArgs ] ] - ifFalse: [ - marshall addBefore: controlFlowGraph instructionFactory flushStack. - marshall doPop: true ]. - ^ self push: DRPhysicalGeneralPurposeRegister receiverResultReg + + compiler compilerClass isSimpleStack ifFalse: [ + "If all arguments pass on registers, then we need to pop them from the stack, but the marshall already unspill them if spilled" + argumentCount simpleConstantFold asDRValue isConstant + ifTrue: [ + marshall addBefore: + (controlFlowGraph instructionFactory flushStackExceptTop: argumentCount simpleConstantFold + 1). + argumentCount simpleConstantFold + 1 "Receiver" timesRepeat: [ + self + pop: 1 + unspilled: argumentCount simpleConstantFold <= self numRegArgs ] ] + ifFalse: [ + marshall addBefore: controlFlowGraph instructionFactory flushStack. + marshall doPop: true ]. + ^ self push: DRPhysicalGeneralPurposeRegister receiverResultReg ] ] { #category : #'special cases' } diff --git a/Druid/SimpleStackBasedCogit.extension.st b/Druid/SimpleStackBasedCogit.extension.st index bd6642f2..0cc7b624 100644 --- a/Druid/SimpleStackBasedCogit.extension.st +++ b/Druid/SimpleStackBasedCogit.extension.st @@ -49,3 +49,9 @@ SimpleStackBasedCogit class >> druidNewRegisterAllocator [ ^ DRCogitLinearScanRegisterAllocator new ] + +{ #category : #'*Druid' } +SimpleStackBasedCogit class >> isSimpleStack [ + + ^ true +] diff --git a/Druid/StackToRegisterMappingCogit.extension.st b/Druid/StackToRegisterMappingCogit.extension.st index 046bac88..043e934d 100644 --- a/Druid/StackToRegisterMappingCogit.extension.st +++ b/Druid/StackToRegisterMappingCogit.extension.st @@ -52,3 +52,9 @@ StackToRegisterMappingCogit class >> druidNewRegisterAllocator [ ^ DRCogitDynamicLinearScanRegisterAllocator new ] + +{ #category : #'*Druid' } +StackToRegisterMappingCogit class >> isSimpleStack [ + + ^ false +] From d2e56888176412e941b8d55e03f26afdc16c197e Mon Sep 17 00:00:00 2001 From: palumbon Date: Mon, 23 Sep 2024 17:10:38 +0200 Subject: [PATCH 05/20] Fix LoadStackValue code generation for index > 0 --- Druid/DRCogitCodeGenerator.class.st | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Druid/DRCogitCodeGenerator.class.st b/Druid/DRCogitCodeGenerator.class.st index 43432f8d..2fa7746b 100644 --- a/Druid/DRCogitCodeGenerator.class.st +++ b/Druid/DRCogitCodeGenerator.class.st @@ -1111,12 +1111,25 @@ DRCogitCodeGenerator >> visitLoad: aDRLoad [ { #category : #visiting } DRCogitCodeGenerator >> visitLoadStackValue: aDRLoadStackValue [ + + | offset | + + self assert: aDRLoadStackValue operand1 simpleConstantFold isNumber. + + offset := RBLiteralNode value: aDRLoadStackValue operand1 simpleConstantFold << 3. + +" RBMessageNode + receiver: (aDRLoadStackValue operand1 rtlPushArgumentExpressions: self) first + selector: #<< + arguments: { RBVariableNode named: '3' }. +" + "cogit MoveMw: index r: SPReg R: TempReg" generatorMethodBuilder addStatement: (RBMessageNode receiver: RBVariableNode selfNode selector: #MoveMw:r:R: arguments: { - (aDRLoadStackValue operand1 rtlPushArgumentExpressions: self) first. + offset. (RBVariableNode named: 'SPReg'). (RBVariableNode named: aDRLoadStackValue result name) }) ] From 5fa942a8d6bd15676a9c0c27b36772defbbd2a56 Mon Sep 17 00:00:00 2001 From: palumbon Date: Mon, 23 Sep 2024 17:12:06 +0200 Subject: [PATCH 06/20] Moving Coalesce tests to the expected class --- ...DRBytecodeScenarioCompilationTest.class.st | 182 ----------------- .../DRCogitStackCoalescingTest.class.st | 188 ++++++++++++++++++ 2 files changed, 188 insertions(+), 182 deletions(-) diff --git a/Druid-Tests/DRBytecodeScenarioCompilationTest.class.st b/Druid-Tests/DRBytecodeScenarioCompilationTest.class.st index 2ed5e531..55bf6a30 100644 --- a/Druid-Tests/DRBytecodeScenarioCompilationTest.class.st +++ b/Druid-Tests/DRBytecodeScenarioCompilationTest.class.st @@ -4,188 +4,6 @@ Class { #category : #'Druid-Tests' } -{ #category : #tests } -DRBytecodeScenarioCompilationTest >> testCoalesceOneSpilledAndOneUnspilledPopInsertsUnspill [ - - | cfg basicBlock1 basicBlock2 mergeBlock popToUnspill popStackDepth | - cfg := DRControlFlowGraph new. - basicBlock1 := cfg newBasicBlockWith: [ :block | - block popUnspilled - ]. - basicBlock2 := cfg newBasicBlockWith: [ :block | - popToUnspill := block pop - ]. - cfg initialBasicBlock jumpIf: true to: basicBlock1 ifFalseTo: basicBlock2. - mergeBlock := cfg newBasicBlock. - basicBlock1 jumpTo: mergeBlock. - basicBlock2 jumpTo: mergeBlock. - - popStackDepth := popToUnspill stackDepth. - - DRCogitStackCoalescing applyTo: cfg. - - self assert: basicBlock2 firstInstruction isUnspill. - self assert: basicBlock2 firstInstruction operand1 value equals: popStackDepth negated - 1 -] - -{ #category : #tests } -DRBytecodeScenarioCompilationTest >> testCoalesceOneSpilledAndOneUnspilledPopsIntoSingleUnpilledPop [ - - | cfg basicBlock1 basicBlock2 mergeBlock | - cfg := DRControlFlowGraph new. - basicBlock1 := cfg newBasicBlockWith: [ :block | - block popUnspilled - ]. - basicBlock2 := cfg newBasicBlockWith: [ :block | - block pop - ]. - cfg initialBasicBlock jumpIf: true to: basicBlock1 ifFalseTo: basicBlock2. - mergeBlock := cfg newBasicBlock. - basicBlock1 jumpTo: mergeBlock. - basicBlock2 jumpTo: mergeBlock. - - DRCogitStackCoalescing applyTo: cfg. - - self assert: mergeBlock firstInstruction isPop. - self assert: mergeBlock firstInstruction isUnspilled -] - -{ #category : #tests } -DRBytecodeScenarioCompilationTest >> testCoalesceOneUnspilledAndOneSpilledPopInsertsUnspill [ - - | cfg basicBlock1 basicBlock2 mergeBlock popToUnspill popStackDepth | - cfg := DRControlFlowGraph new. - basicBlock2 := cfg newBasicBlockWith: [ :block | - popToUnspill := block pop - ]. - basicBlock1 := cfg newBasicBlockWith: [ :block | - block popUnspilled - ]. - cfg initialBasicBlock jumpIf: true to: basicBlock1 ifFalseTo: basicBlock2. - mergeBlock := cfg newBasicBlock. - basicBlock1 jumpTo: mergeBlock. - basicBlock2 jumpTo: mergeBlock. - - popStackDepth := popToUnspill stackDepth. - - DRCogitStackCoalescing applyTo: cfg. - - self assert: basicBlock2 firstInstruction isUnspill. - self assert: basicBlock2 firstInstruction operand1 value equals: popStackDepth negated - 1 -] - -{ #category : #tests } -DRBytecodeScenarioCompilationTest >> testCoalesceOneUnspilledAndOnespilledPopsIntoSingleUnpilledPop [ - - | cfg basicBlock1 basicBlock2 mergeBlock | - cfg := DRControlFlowGraph new. - basicBlock2 := cfg newBasicBlockWith: [ :block | - block pop - ]. - basicBlock1 := cfg newBasicBlockWith: [ :block | - block popUnspilled - ]. - cfg initialBasicBlock jumpIf: true to: basicBlock1 ifFalseTo: basicBlock2. - mergeBlock := cfg newBasicBlock. - basicBlock1 jumpTo: mergeBlock. - basicBlock2 jumpTo: mergeBlock. - - DRCogitStackCoalescing applyTo: cfg. - - self assert: mergeBlock firstInstruction isPop. - self assert: mergeBlock firstInstruction isUnspilled -] - -{ #category : #tests } -DRBytecodeScenarioCompilationTest >> testCoalesceTwoSpilledPopsDoesNotReplaceMovedInstructions [ - - | cfg basicBlock1 basicBlock2 mergeBlock | - cfg := DRControlFlowGraph new. - basicBlock1 := cfg newBasicBlockWith: [ :block | - block pop - ]. - basicBlock2 := cfg newBasicBlockWith: [ :block | - block pop - ]. - cfg initialBasicBlock jumpIf: true to: basicBlock1 ifFalseTo: basicBlock2. - mergeBlock := cfg newBasicBlock. - basicBlock1 jumpTo: mergeBlock. - basicBlock2 jumpTo: mergeBlock. - - DRCogitStackCoalescing applyTo: cfg. - - "Blocks only contain the jumps" - self assert: basicBlock1 instructions size equals: 1. - self assert: basicBlock2 instructions size equals: 1. -] - -{ #category : #tests } -DRBytecodeScenarioCompilationTest >> testCoalesceTwoSpilledPopsIntoSingleSpilledPop [ - - | cfg basicBlock1 basicBlock2 mergeBlock | - cfg := DRControlFlowGraph new. - basicBlock1 := cfg newBasicBlockWith: [ :block | - block pop - ]. - basicBlock2 := cfg newBasicBlockWith: [ :block | - block pop - ]. - cfg initialBasicBlock jumpIf: true to: basicBlock1 ifFalseTo: basicBlock2. - mergeBlock := cfg newBasicBlock. - basicBlock1 jumpTo: mergeBlock. - basicBlock2 jumpTo: mergeBlock. - - DRCogitStackCoalescing applyTo: cfg. - - self assert: mergeBlock firstInstruction isPop. - self deny: mergeBlock firstInstruction isUnspilled -] - -{ #category : #tests } -DRBytecodeScenarioCompilationTest >> testCoalesceTwoUnspilledPopsDoesNotReplaceMovedInstructions [ - - | cfg basicBlock1 basicBlock2 mergeBlock | - cfg := DRControlFlowGraph new. - basicBlock1 := cfg newBasicBlockWith: [ :block | - block popUnspilled - ]. - basicBlock2 := cfg newBasicBlockWith: [ :block | - block popUnspilled - ]. - cfg initialBasicBlock jumpIf: true to: basicBlock1 ifFalseTo: basicBlock2. - mergeBlock := cfg newBasicBlock. - basicBlock1 jumpTo: mergeBlock. - basicBlock2 jumpTo: mergeBlock. - - DRCogitStackCoalescing applyTo: cfg. - - "Blocks only contain the jumps" - self assert: basicBlock1 instructions size equals: 1. - self assert: basicBlock2 instructions size equals: 1. -] - -{ #category : #tests } -DRBytecodeScenarioCompilationTest >> testCoalesceTwoUnspilledPopsIntoSingleUnspilledPop [ - - | cfg basicBlock1 basicBlock2 mergeBlock | - cfg := DRControlFlowGraph new. - basicBlock1 := cfg newBasicBlockWith: [ :block | - block popUnspilled - ]. - basicBlock2 := cfg newBasicBlockWith: [ :block | - block popUnspilled - ]. - cfg initialBasicBlock jumpIf: true to: basicBlock1 ifFalseTo: basicBlock2. - mergeBlock := cfg newBasicBlock. - basicBlock1 jumpTo: mergeBlock. - basicBlock2 jumpTo: mergeBlock. - - DRCogitStackCoalescing applyTo: cfg. - - self assert: mergeBlock firstInstruction isPop. - self assert: mergeBlock firstInstruction isUnspilled -] - { #category : #tests } DRBytecodeScenarioCompilationTest >> testFlushStackOnBranch1 [ diff --git a/Druid-Tests/DRCogitStackCoalescingTest.class.st b/Druid-Tests/DRCogitStackCoalescingTest.class.st index 91860a02..9737970c 100644 --- a/Druid-Tests/DRCogitStackCoalescingTest.class.st +++ b/Druid-Tests/DRCogitStackCoalescingTest.class.st @@ -3,3 +3,191 @@ Class { #superclass : #DROptimisationTest, #category : #'Druid-Tests-Optimizations' } + +{ #category : #tests } +DRCogitStackCoalescingTest >> setUp [ + + optimisation := DRCogitStackCoalescing new +] + +{ #category : #tests } +DRCogitStackCoalescingTest >> testCoalesceOneSpilledAndOneUnspilledPopInsertsUnspill [ + + | cfg basicBlock1 basicBlock2 mergeBlock popToUnspill popStackDepth | + cfg := DRControlFlowGraph new. + basicBlock1 := cfg newBasicBlockWith: [ :block | + block popUnspilled + ]. + basicBlock2 := cfg newBasicBlockWith: [ :block | + popToUnspill := block pop + ]. + cfg initialBasicBlock jumpIf: true to: basicBlock1 ifFalseTo: basicBlock2. + mergeBlock := cfg newBasicBlock. + basicBlock1 jumpTo: mergeBlock. + basicBlock2 jumpTo: mergeBlock. + + popStackDepth := popToUnspill stackDepth. + + optimisation applyTo: cfg. + + self assert: basicBlock2 firstInstruction isUnspill. + self assert: basicBlock2 firstInstruction operand1 value equals: popStackDepth negated - 1 +] + +{ #category : #tests } +DRCogitStackCoalescingTest >> testCoalesceOneSpilledAndOneUnspilledPopsIntoSingleUnpilledPop [ + + | cfg basicBlock1 basicBlock2 mergeBlock | + cfg := DRControlFlowGraph new. + basicBlock1 := cfg newBasicBlockWith: [ :block | + block popUnspilled + ]. + basicBlock2 := cfg newBasicBlockWith: [ :block | + block pop + ]. + cfg initialBasicBlock jumpIf: true to: basicBlock1 ifFalseTo: basicBlock2. + mergeBlock := cfg newBasicBlock. + basicBlock1 jumpTo: mergeBlock. + basicBlock2 jumpTo: mergeBlock. + + optimisation applyTo: cfg. + + self assert: mergeBlock firstInstruction isPop. + self assert: mergeBlock firstInstruction isUnspilled +] + +{ #category : #tests } +DRCogitStackCoalescingTest >> testCoalesceOneUnspilledAndOneSpilledPopInsertsUnspill [ + + | cfg basicBlock1 basicBlock2 mergeBlock popToUnspill popStackDepth | + cfg := DRControlFlowGraph new. + basicBlock2 := cfg newBasicBlockWith: [ :block | + popToUnspill := block pop + ]. + basicBlock1 := cfg newBasicBlockWith: [ :block | + block popUnspilled + ]. + cfg initialBasicBlock jumpIf: true to: basicBlock1 ifFalseTo: basicBlock2. + mergeBlock := cfg newBasicBlock. + basicBlock1 jumpTo: mergeBlock. + basicBlock2 jumpTo: mergeBlock. + + popStackDepth := popToUnspill stackDepth. + + optimisation applyTo: cfg. + + self assert: basicBlock2 firstInstruction isUnspill. + self assert: basicBlock2 firstInstruction operand1 value equals: popStackDepth negated - 1 +] + +{ #category : #tests } +DRCogitStackCoalescingTest >> testCoalesceOneUnspilledAndOnespilledPopsIntoSingleUnpilledPop [ + + | cfg basicBlock1 basicBlock2 mergeBlock | + cfg := DRControlFlowGraph new. + basicBlock2 := cfg newBasicBlockWith: [ :block | + block pop + ]. + basicBlock1 := cfg newBasicBlockWith: [ :block | + block popUnspilled + ]. + cfg initialBasicBlock jumpIf: true to: basicBlock1 ifFalseTo: basicBlock2. + mergeBlock := cfg newBasicBlock. + basicBlock1 jumpTo: mergeBlock. + basicBlock2 jumpTo: mergeBlock. + + optimisation applyTo: cfg. + + self assert: mergeBlock firstInstruction isPop. + self assert: mergeBlock firstInstruction isUnspilled +] + +{ #category : #tests } +DRCogitStackCoalescingTest >> testCoalesceTwoSpilledPopsDoesNotReplaceMovedInstructions [ + + | cfg basicBlock1 basicBlock2 mergeBlock | + cfg := DRControlFlowGraph new. + basicBlock1 := cfg newBasicBlockWith: [ :block | + block pop + ]. + basicBlock2 := cfg newBasicBlockWith: [ :block | + block pop + ]. + cfg initialBasicBlock jumpIf: true to: basicBlock1 ifFalseTo: basicBlock2. + mergeBlock := cfg newBasicBlock. + basicBlock1 jumpTo: mergeBlock. + basicBlock2 jumpTo: mergeBlock. + + optimisation applyTo: cfg. + + "Blocks only contain the jumps" + self assert: basicBlock1 instructions size equals: 1. + self assert: basicBlock2 instructions size equals: 1. +] + +{ #category : #tests } +DRCogitStackCoalescingTest >> testCoalesceTwoSpilledPopsIntoSingleSpilledPop [ + + | cfg basicBlock1 basicBlock2 mergeBlock | + cfg := DRControlFlowGraph new. + basicBlock1 := cfg newBasicBlockWith: [ :block | + block pop + ]. + basicBlock2 := cfg newBasicBlockWith: [ :block | + block pop + ]. + cfg initialBasicBlock jumpIf: true to: basicBlock1 ifFalseTo: basicBlock2. + mergeBlock := cfg newBasicBlock. + basicBlock1 jumpTo: mergeBlock. + basicBlock2 jumpTo: mergeBlock. + + optimisation applyTo: cfg. + + self assert: mergeBlock firstInstruction isPop. + self deny: mergeBlock firstInstruction isUnspilled +] + +{ #category : #tests } +DRCogitStackCoalescingTest >> testCoalesceTwoUnspilledPopsDoesNotReplaceMovedInstructions [ + + | cfg basicBlock1 basicBlock2 mergeBlock | + cfg := DRControlFlowGraph new. + basicBlock1 := cfg newBasicBlockWith: [ :block | + block popUnspilled + ]. + basicBlock2 := cfg newBasicBlockWith: [ :block | + block popUnspilled + ]. + cfg initialBasicBlock jumpIf: true to: basicBlock1 ifFalseTo: basicBlock2. + mergeBlock := cfg newBasicBlock. + basicBlock1 jumpTo: mergeBlock. + basicBlock2 jumpTo: mergeBlock. + + optimisation applyTo: cfg. + + "Blocks only contain the jumps" + self assert: basicBlock1 instructions size equals: 1. + self assert: basicBlock2 instructions size equals: 1. +] + +{ #category : #tests } +DRCogitStackCoalescingTest >> testCoalesceTwoUnspilledPopsIntoSingleUnspilledPop [ + + | cfg basicBlock1 basicBlock2 mergeBlock | + cfg := DRControlFlowGraph new. + basicBlock1 := cfg newBasicBlockWith: [ :block | + block popUnspilled + ]. + basicBlock2 := cfg newBasicBlockWith: [ :block | + block popUnspilled + ]. + cfg initialBasicBlock jumpIf: true to: basicBlock1 ifFalseTo: basicBlock2. + mergeBlock := cfg newBasicBlock. + basicBlock1 jumpTo: mergeBlock. + basicBlock2 jumpTo: mergeBlock. + + optimisation applyTo: cfg. + + self assert: mergeBlock firstInstruction isPop. + self assert: mergeBlock firstInstruction isUnspilled +] From e9efdc44053139f4cc2f8b71e3431f26b28ccf1e Mon Sep 17 00:00:00 2001 From: palumbon Date: Tue, 24 Sep 2024 11:27:10 +0200 Subject: [PATCH 07/20] Parametrize #compilerClass for Bytecode and Primitive tests --- .../DRBytecodeCompilationTest.class.st | 13 ++--- Druid-Tests/DRMetaCompilationTest.class.st | 49 +++++++++++++++++++ .../DRPrimitiveCompilationTest.class.st | 46 +---------------- 3 files changed, 58 insertions(+), 50 deletions(-) create mode 100644 Druid-Tests/DRMetaCompilationTest.class.st diff --git a/Druid-Tests/DRBytecodeCompilationTest.class.st b/Druid-Tests/DRBytecodeCompilationTest.class.st index 1091b37b..3606822e 100644 --- a/Druid-Tests/DRBytecodeCompilationTest.class.st +++ b/Druid-Tests/DRBytecodeCompilationTest.class.st @@ -1,6 +1,6 @@ Class { #name : #DRBytecodeCompilationTest, - #superclass : #DRDruidTest, + #superclass : #DRMetaCompilationTest, #category : #'Druid-Tests' } @@ -18,7 +18,7 @@ DRBytecodeCompilationTest >> compileBytecode: bytecode1 selector: selector1 andB }; interpreter: self interpreter; targetName: generatorSelector; - configureForCompilerClass: DruidTestRTLCompiler. + configureForCompilerClass: compilerClass. compiler compile. "Then generate the machine code for that method" @@ -47,7 +47,7 @@ DRBytecodeCompilationTest >> compileBytecode: bytecode selector: aSelector optio compiler := DRBytecodeCompilerCompiler new bytecodes: { (bytecode -> aSelector) }; interpreter: self interpreter; - configureForCompilerClass: DruidTestRTLCompiler; + configureForCompilerClass: compilerClass; addCompilerOptions: options. compiler compile. @@ -87,7 +87,7 @@ DRBytecodeCompilationTest >> doCompileBytecode: bytecode selector: aSelector [ compiler := DRBytecodeCompilerCompiler new sourceName: aSelector; interpreter: self interpreter; - configureForCompilerClass: DruidTestRTLCompiler. + configureForCompilerClass: compilerClass. compiler compile. ] @@ -119,9 +119,10 @@ DRBytecodeCompilationTest >> prepareStackForPrimitiveReceiver: aReceiver argumen DRBytecodeCompilationTest >> prepareStackForSendReceiver: aReceiver arguments: arguments method: aMethod [ super prepareStackForSendReceiver: aReceiver arguments: arguments method: aMethod. - + self makeFrame: aReceiver arguments: arguments method: aMethod. - + + self flag: #TODO. "Receive this by param, method is not used for the tests" cogit methodOrBlockNumTemps timesRepeat: [ self pushAddress: memory nilObject ] diff --git a/Druid-Tests/DRMetaCompilationTest.class.st b/Druid-Tests/DRMetaCompilationTest.class.st new file mode 100644 index 00000000..98edb223 --- /dev/null +++ b/Druid-Tests/DRMetaCompilationTest.class.st @@ -0,0 +1,49 @@ +Class { + #name : #DRMetaCompilationTest, + #superclass : #DRDruidTest, + #instVars : [ + 'cogitStyle', + 'compilerClass' + ], + #category : #'Druid-Tests' +} + +{ #category : #'building suites' } +DRMetaCompilationTest class >> cogitStyleParameter [ + "Two ways to compile code with different calling conventions: simple stack vs stack to register mapping" + + ^ ParametrizedTestMatrix new + addCase: { #cogitStyle -> #beForStackToRegisterMapping. #compilerClass -> DruidTestRTLCompiler}; + addCase: { #cogitStyle -> #beForSimpleStack. #compilerClass -> SimpleDruidTestRTLCompiler}; + yourself +] + +{ #category : #'building suites' } +DRMetaCompilationTest class >> testParameters [ + + ^ super testParameters * self cogitStyleParameter +] + +{ #category : #accessing } +DRMetaCompilationTest >> cogitStyle: aSymbol [ + + cogitStyle := aSymbol +] + +{ #category : #accessing } +DRMetaCompilationTest >> compilerClass [ + + ^ compilerClass +] + +{ #category : #accessing } +DRMetaCompilationTest >> compilerClass: anObject [ + + compilerClass := anObject +] + +{ #category : #'helpers-compiling' } +DRMetaCompilationTest >> jitCompilerClass [ + + ^ compilerClass +] diff --git a/Druid-Tests/DRPrimitiveCompilationTest.class.st b/Druid-Tests/DRPrimitiveCompilationTest.class.st index 54d3ec1c..f4f14be2 100644 --- a/Druid-Tests/DRPrimitiveCompilationTest.class.st +++ b/Druid-Tests/DRPrimitiveCompilationTest.class.st @@ -1,36 +1,12 @@ Class { #name : #DRPrimitiveCompilationTest, - #superclass : #DRDruidTest, + #superclass : #DRMetaCompilationTest, #instVars : [ - 'stopAddress', - 'cogitStyle', - 'compilerClass' + 'stopAddress' ], #category : #'Druid-Tests' } -{ #category : #'building suites' } -DRPrimitiveCompilationTest class >> cogitStyleParameter [ - "Two ways to compile code with different calling conventions: simple stack vs stack to register mapping" - - ^ ParametrizedTestMatrix new - addCase: { #cogitStyle -> #beForStackToRegisterMapping. #compilerClass -> DruidTestRTLCompiler}; - addCase: { #cogitStyle -> #beForSimpleStack. #compilerClass -> SimpleDruidTestRTLCompiler}; - yourself -] - -{ #category : #'building suites' } -DRPrimitiveCompilationTest class >> testParameters [ - - ^ super testParameters * self cogitStyleParameter -] - -{ #category : #accessing } -DRPrimitiveCompilationTest >> cogitStyle: aSymbol [ - - cogitStyle := aSymbol -] - { #category : #'helpers-compiling' } DRPrimitiveCompilationTest >> compileCogitSelector: aSelector numArgs: argumentCount [ @@ -137,18 +113,6 @@ DRPrimitiveCompilationTest >> compilePrimitive: primitiveSelector ForSendReceive self prepareStackForSendReceiver: receiver arguments: arguments ] -{ #category : #accessing } -DRPrimitiveCompilationTest >> compilerClass [ - - ^ compilerClass -] - -{ #category : #accessing } -DRPrimitiveCompilationTest >> compilerClass: anObject [ - - compilerClass := anObject -] - { #category : #'helpers - execution' } DRPrimitiveCompilationTest >> executeUntilStopPrimitiveWithReceiver: receiverOop [ @@ -168,12 +132,6 @@ DRPrimitiveCompilationTest >> executeUntilStopPrimitiveWithReceiver: receiverOop self runFrom: cogInitialAddress until: stopAddress. ] -{ #category : #'helpers-compiling' } -DRPrimitiveCompilationTest >> jitCompilerClass [ - - ^ compilerClass -] - { #category : #'helpers - execution' } DRPrimitiveCompilationTest >> runUntilStop [ From 47d812b4e24143f21b72d10705aeaba9ee232080 Mon Sep 17 00:00:00 2001 From: palumbon Date: Tue, 24 Sep 2024 11:39:03 +0200 Subject: [PATCH 08/20] Using initializeSStack: in BytecodeScenarioCompilationTest to be compatible with SimpleDruid --- .../DRBytecodeCompilationTest.class.st | 20 +- ...DRBytecodeScenarioCompilationTest.class.st | 223 +++++++++--------- Druid-Tests/DRMetaCompilationTest.class.st | 6 + 3 files changed, 132 insertions(+), 117 deletions(-) diff --git a/Druid-Tests/DRBytecodeCompilationTest.class.st b/Druid-Tests/DRBytecodeCompilationTest.class.st index 3606822e..0feeac8f 100644 --- a/Druid-Tests/DRBytecodeCompilationTest.class.st +++ b/Druid-Tests/DRBytecodeCompilationTest.class.st @@ -92,18 +92,30 @@ DRBytecodeCompilationTest >> doCompileBytecode: bytecode selector: aSelector [ compiler compile. ] +{ #category : #initialization } +DRBytecodeCompilationTest >> initializeSStack: argCount [ + + self isSimpleStack ifTrue: [ ^ self ]. "No SSTack" + + cogit ssPushRegister: ReceiverResultReg. + argCount > 0 ifTrue: [ cogit ssPushRegister: Arg0Reg ]. + argCount > 1 ifTrue: [ cogit ssPushRegister: Arg1Reg ] +] + { #category : #helpers } DRBytecodeCompilationTest >> makeFrame: aReceiver arguments: arguments method: aMethod [ - "Callee side - make up the frame" + "Now push the link register, it will be popped by the return" machineSimulator hasLinkRegister ifTrue: [ self pushAddress: machineSimulator linkRegisterValue ]. self pushAddress: machineSimulator fp. - machineSimulator fp: machineSimulator smalltalkStackPointerRegisterValue. + machineSimulator fp: + machineSimulator smalltalkStackPointerRegisterValue. self pushAddress: aMethod. - self pushAddress: 0 "context". - self pushAddress: aReceiver. + self pushAddress: 0. "context" + self pushAddress: aReceiver. + arguments do: [ :anArgument | self pushAddress: anArgument ]. ] diff --git a/Druid-Tests/DRBytecodeScenarioCompilationTest.class.st b/Druid-Tests/DRBytecodeScenarioCompilationTest.class.st index 55bf6a30..d649d64d 100644 --- a/Druid-Tests/DRBytecodeScenarioCompilationTest.class.st +++ b/Druid-Tests/DRBytecodeScenarioCompilationTest.class.st @@ -4,16 +4,114 @@ Class { #category : #'Druid-Tests' } +{ #category : #tests } +DRBytecodeScenarioCompilationTest >> testCoallescedPops [ + + self + compileBytecode: 0 + selector: #bytecodePopOnTwoBranches + thenDo: [ :generator | "Push the receiver" + self initializeSStack: 0. + "Then execute the druid's compiled code" + generator value. + cogit genReturnTopFromMethod ]. + + self executePrimitiveWithReceiver: 17. + + self assert: machineSimulator receiverRegisterValue equals: 17 +] + +{ #category : #tests } +DRBytecodeScenarioCompilationTest >> testCoallescedPushOnBranchOne [ + + self + compileBytecode: 0 + selector: #bytecodePushOnTwoBranches + thenDo: [ :generator | + self initializeSStack: 0. + generator value. "Call generator" + cogit genReturnTopFromMethod ]. + + self executePrimitiveWithReceiver: 17. + + self assert: machineSimulator receiverRegisterValue equals: 1 +] + +{ #category : #tests } +DRBytecodeScenarioCompilationTest >> testCoallescedPushOnBranchTwo [ + + self + compileBytecode: 0 + selector: #bytecodePushOnTwoBranches + thenDo: [ :generator | + self initializeSStack: 0. + generator value. "Call generator" + cogit genReturnTopFromMethod ]. + + self executePrimitiveWithReceiver: -17. + + self assert: machineSimulator receiverRegisterValue equals: 2 +] + +{ #category : #tests } +DRBytecodeScenarioCompilationTest >> testCoallescedTwoPops [ + + self + compileBytecode: 0 + selector: #bytecodeTwoPopOnTwoBranches + thenDo: [ :generator | + self initializeSStack: 1. + generator value. "Call generator" + cogit genReturnTopFromMethod ]. + + self executePrimitiveWithReceiver: 17 withArguments: { 42 }. + + self assert: machineSimulator receiverRegisterValue equals: 59 +] + +{ #category : #tests } +DRBytecodeScenarioCompilationTest >> testCoallescedTwoPushesOnBranchOne [ + + self + compileBytecode: 0 + selector: #bytecodeTwoPushOnTwoBranches + thenDo: [ :generator | + self initializeSStack: 0. + generator value. "Call generator" + cogit genReturnTopFromMethod ]. + + self executePrimitiveWithReceiver: 17. + + self assert: machineSimulator receiverRegisterValue equals: 3 +] + +{ #category : #tests } +DRBytecodeScenarioCompilationTest >> testCoallescedTwoPushesOnBranchTwo [ + + self + compileBytecode: 0 + selector: #bytecodeTwoPushOnTwoBranches + thenDo: [ :generator | + self initializeSStack: 0. + generator value. "Call generator" + cogit genReturnTopFromMethod ]. + + self executePrimitiveWithReceiver: -17. + + self assert: machineSimulator receiverRegisterValue equals: 7 +] + { #category : #tests } DRBytecodeScenarioCompilationTest >> testFlushStackOnBranch1 [ - | mustBeBooleanTrampolineAddress | + | mustBeBooleanTrampolineAddress | + self isSimpleStack ifTrue: [ self skip ]. + cogit ceDeoptimiseFrameTrampoline: fakeTrampoline. mustBeBooleanTrampolineAddress := self compile: [ cogit RetN: 0 ]. cogit ceSendMustBeBooleanTrampoline: mustBeBooleanTrampolineAddress. - self compileBytecode: 0 selector: #bytecodeWithFlushStackOnDominator @@ -34,6 +132,8 @@ DRBytecodeScenarioCompilationTest >> testFlushStackOnBranch1 [ DRBytecodeScenarioCompilationTest >> testFlushStackOnBranch2 [ | deoptimizeAddress | + self isSimpleStack ifTrue: [ self skip ]. + deoptimizeAddress := self compile: [ cogit RetN: 0 ]. cogit ceDeoptimiseFrameTrampoline: deoptimizeAddress. @@ -56,7 +156,9 @@ DRBytecodeScenarioCompilationTest >> testFlushStackOnBranch2 [ ] { #category : #tests } -DRBytecodeScenarioCompilationTest >> testPopAfterFlushStack [ +DRBytecodeScenarioCompilationTest >> testFlushStackThenPop [ + + self isSimpleStack ifTrue: [ self skip ]. self compileBytecode: 0 @@ -68,62 +170,11 @@ DRBytecodeScenarioCompilationTest >> testPopAfterFlushStack [ generator value. cogit genUpArrowReturn ]. - self executeMethodWithReceiver: 0 withArguments: #( ). + self executePrimitiveWithReceiver: 0. self assert: cogit ssTop constant equals: 237 ] -{ #category : #tests } -DRBytecodeScenarioCompilationTest >> testPopsAreCoallesced [ - - self - compileBytecode: 0 - selector: #bytecodePopOnTwoBranches - thenDo: [ :generator | "Push the receiver" - cogit ssPushRegister: ReceiverResultReg. - "Then execute the druid's compiled code" - generator value. - cogit genReturnTopFromMethod ]. - - self executePrimitiveWithReceiver: 17. - - self assert: machineSimulator receiverRegisterValue equals: 17 -] - -{ #category : #tests } -DRBytecodeScenarioCompilationTest >> testPushAreCoallescedBranchOne [ - - self - compileBytecode: 0 - selector: #bytecodePushOnTwoBranches - thenDo: [ :generator | "Push the receiver" - cogit ssPushRegister: ReceiverResultReg. - "Then execute the druid's compiled code" - generator value. - cogit genReturnTopFromMethod ]. - - self executePrimitiveWithReceiver: 17. - - self assert: machineSimulator receiverRegisterValue equals: 1 -] - -{ #category : #tests } -DRBytecodeScenarioCompilationTest >> testPushAreCoallescedBranchTwo [ - - self - compileBytecode: 0 - selector: #bytecodePushOnTwoBranches - thenDo: [ :generator | "Push the receiver" - cogit ssPushRegister: ReceiverResultReg. - "Then execute the druid's compiled code" - generator value. - cogit genReturnTopFromMethod ]. - - self executePrimitiveWithReceiver: -17. - - self assert: machineSimulator receiverRegisterValue equals: 2 -] - { #category : #tests } DRBytecodeScenarioCompilationTest >> testPushTrueAndJumpFalse [ @@ -259,9 +310,8 @@ DRBytecodeScenarioCompilationTest >> testSuperBytecodePrimIdenticalAndJumpFalse andBytecode: 184 selector: #shortConditionalJumpFalse thenDo: [ :generator | - cogit ssPushRegister: ReceiverResultReg. - cogit ssPushRegister: Arg0Reg. - + self initializeSStack: 1. + cogit bytecodePC: 16. cogit methodObj: method. cogit debugStackPointers: @@ -315,8 +365,7 @@ DRBytecodeScenarioCompilationTest >> testSuperBytecodePrimIdenticalAndJumpFalse2 andBytecode: 184 selector: #shortConditionalJumpFalse thenDo: [ :generator | - cogit ssPushRegister: ReceiverResultReg. - cogit ssPushRegister: Arg0Reg. + self initializeSStack: 1. cogit bytecodePC: 16. cogit methodObj: method. @@ -355,7 +404,7 @@ DRBytecodeScenarioCompilationTest >> testSuperInstructionCompilation [ options: #( superInstructions ) thenDo: [ :generator | "Nothing" ]. - compiledMethod := DruidTestRTLCompiler >> #gen_fakePushConstantTrueBytecode. + compiledMethod := compilerClass >> #gen_fakePushConstantTrueBytecode. "Avoid super-instruction if there is a fixup to the next bytecode" fixupCheck := compiledMethod ast allChildren detect: [ :n | n isMessage and: [ n selector = #ifTrue: ] ]. @@ -376,58 +425,6 @@ DRBytecodeScenarioCompilationTest >> testSuperInstructionCompilation [ ] -{ #category : #tests } -DRBytecodeScenarioCompilationTest >> testTwoPopsAreCoallesced [ - - self - compileBytecode: 0 - selector: #bytecodeTwoPopOnTwoBranches - thenDo: [ :generator | "Push the receiver" - cogit ssPushRegister: ReceiverResultReg. - cogit ssPushRegister: Arg0Reg. - "Then execute the druid's compiled code" - generator value. - cogit genReturnTopFromMethod ]. - - self executePrimitiveWithReceiver: 17 withArguments: { 42 }. - - self assert: machineSimulator receiverRegisterValue equals: 59 -] - -{ #category : #tests } -DRBytecodeScenarioCompilationTest >> testTwoPushesAreCoallescedBranchOne [ - - self - compileBytecode: 0 - selector: #bytecodeTwoPushOnTwoBranches - thenDo: [ :generator | "Push the receiver" - cogit ssPushRegister: ReceiverResultReg. - "Then execute the druid's compiled code" - generator value. - cogit genReturnTopFromMethod ]. - - self executePrimitiveWithReceiver: 17. - - self assert: machineSimulator receiverRegisterValue equals: 3 -] - -{ #category : #tests } -DRBytecodeScenarioCompilationTest >> testTwoPushesAreCoallescedBranchTwo [ - - self - compileBytecode: 0 - selector: #bytecodeTwoPushOnTwoBranches - thenDo: [ :generator | "Push the receiver" - cogit ssPushRegister: ReceiverResultReg. - "Then execute the druid's compiled code" - generator value. - cogit genReturnTopFromMethod ]. - - self executePrimitiveWithReceiver: -17. - - self assert: machineSimulator receiverRegisterValue equals: 7 -] - { #category : #tests } DRBytecodeScenarioCompilationTest >> testUnknownBytecode [ diff --git a/Druid-Tests/DRMetaCompilationTest.class.st b/Druid-Tests/DRMetaCompilationTest.class.st index 98edb223..f2424211 100644 --- a/Druid-Tests/DRMetaCompilationTest.class.st +++ b/Druid-Tests/DRMetaCompilationTest.class.st @@ -42,6 +42,12 @@ DRMetaCompilationTest >> compilerClass: anObject [ compilerClass := anObject ] +{ #category : #testing } +DRMetaCompilationTest >> isSimpleStack [ + + ^ compilerClass isSimpleStack +] + { #category : #'helpers-compiling' } DRMetaCompilationTest >> jitCompilerClass [ From 3728fba3e5785d7c51cdf5ec6a16fe7cdae62641 Mon Sep 17 00:00:00 2001 From: palumbon Date: Tue, 24 Sep 2024 11:39:39 +0200 Subject: [PATCH 09/20] Avoid SimpleDruid for Bytecode tests -> big refactor needed --- Druid-Tests/DRBytecodeCompilationTest.class.st | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Druid-Tests/DRBytecodeCompilationTest.class.st b/Druid-Tests/DRBytecodeCompilationTest.class.st index 0feeac8f..d3a926cc 100644 --- a/Druid-Tests/DRBytecodeCompilationTest.class.st +++ b/Druid-Tests/DRBytecodeCompilationTest.class.st @@ -4,6 +4,15 @@ Class { #category : #'Druid-Tests' } +{ #category : #'building suites' } +DRBytecodeCompilationTest class >> cogitStyleParameter [ + + ^ ParametrizedTestMatrix new + addCase: { #cogitStyle -> #beForStackToRegisterMapping. #compilerClass -> DruidTestRTLCompiler}; + "addCase: { #cogitStyle -> #beForSimpleStack. #compilerClass -> SimpleDruidTestRTLCompiler};" + yourself +] + { #category : #enumerating } DRBytecodeCompilationTest >> compileBytecode: bytecode1 selector: selector1 andBytecode: bytecode2 selector: selector2 thenDo: aFullBlockClosure [ From 54b6fdded248b72915a326e78bac0db53ceb04b9 Mon Sep 17 00:00:00 2001 From: palumbon Date: Tue, 24 Sep 2024 12:37:52 +0200 Subject: [PATCH 10/20] Push TestRTL generated code --- .../DRBytecodeCompilationTest.class.st | 2 +- Druid-Tests/DruidTestRTLCompiler.class.st | 180 +- .../SimpleDruidTestRTLCompiler.class.st | 2589 ++++++++--------- 3 files changed, 1200 insertions(+), 1571 deletions(-) diff --git a/Druid-Tests/DRBytecodeCompilationTest.class.st b/Druid-Tests/DRBytecodeCompilationTest.class.st index d3a926cc..9dc7b654 100644 --- a/Druid-Tests/DRBytecodeCompilationTest.class.st +++ b/Druid-Tests/DRBytecodeCompilationTest.class.st @@ -124,7 +124,7 @@ DRBytecodeCompilationTest >> makeFrame: aReceiver arguments: arguments method: a self pushAddress: aMethod. self pushAddress: 0. "context" self pushAddress: aReceiver. - arguments do: [ :anArgument | self pushAddress: anArgument ]. + "arguments do: [ :anArgument | self pushAddress: anArgument ]." ] diff --git a/Druid-Tests/DruidTestRTLCompiler.class.st b/Druid-Tests/DruidTestRTLCompiler.class.st index a5e7c85c..b5482bbd 100644 --- a/Druid-Tests/DruidTestRTLCompiler.class.st +++ b/Druid-Tests/DruidTestRTLCompiler.class.st @@ -901,47 +901,16 @@ DruidTestRTLCompiler >> gen_bytecodePopOnTwoBranches [ DruidTestRTLCompiler >> gen_bytecodePrimAdd [ "AutoGenerated by Druid" - | t0 jump3 jump1 t1 currentBlock jump2 live t2 | + | live currentBlock | live := 0. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). - t1 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t1). - t2 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t2). - (self ssValue: 1) copyToReg: t0. - (self ssValue: 0) copyToReg: t1. - self MoveR: t0 R: t2. - self AndR: t1 R: t2. self ssFlushStackExceptTop: 2. - self TstCq: 1 R: t2. - jump1 := self JumpZero: 0. - self AddCq: -1 R: t0. - self AddR: t1 R: t0. - jump2 := self JumpOverflow: 0. - self ssUnspillStackSlotAt: 0. - self ssUnspillStackSlotAt: 1. - self MoveR: t0 R: t2. - jump3 := self Jump: 0. - currentBlock := self Label. - jump1 jmpTarget: currentBlock. - jump2 jmpTarget: currentBlock. self marshallSendArgumentsNoPush: 1. self genMarshalledSendNoPush: -1 numArgs: 1 sendTable: ordinarySendTrampolines. - self MoveR: ReceiverResultReg R: t2. - currentBlock := self Label. - jump3 jmpTarget: currentBlock. self ssPop: 2 popSpilled: false. - self ssPushRegister: t2. + self ssPushRegister: ReceiverResultReg. ^ 0 ] @@ -949,67 +918,7 @@ DruidTestRTLCompiler >> gen_bytecodePrimAdd [ DruidTestRTLCompiler >> gen_bytecodePrimIdenticalSistaV1 [ "AutoGenerated by Druid" - | jump1 b507 s57 s54 t1 jump6 jump3 nextFixup b503 currentBlock t3 t0 nextBytecode jump2 jump5 live t2 jump4 | - nextFixup := self fixupAt: bytecodePC + 1. - nextFixup notAFixup ifTrue: [ - nextBytecode := objectMemory - fetchByte: bytecodePC + 1 - ofObject: methodObj. - nextBytecode = 184 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self gen_bytecodePrimIdenticalSistaV1_shortConditionalJumpTrue_1 ]. - nextBytecode = 185 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self gen_bytecodePrimIdenticalSistaV1_shortConditionalJumpTrue_2 ]. - nextBytecode = 186 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self gen_bytecodePrimIdenticalSistaV1_shortConditionalJumpTrue_3 ]. - nextBytecode = 187 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self gen_bytecodePrimIdenticalSistaV1_shortConditionalJumpTrue_4 ]. - nextBytecode = 188 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self gen_bytecodePrimIdenticalSistaV1_shortConditionalJumpTrue_5 ]. - nextBytecode = 189 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self gen_bytecodePrimIdenticalSistaV1_shortConditionalJumpTrue_6 ]. - nextBytecode = 190 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self gen_bytecodePrimIdenticalSistaV1_shortConditionalJumpTrue_7 ]. - nextBytecode = 191 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self gen_bytecodePrimIdenticalSistaV1_shortConditionalJumpTrue_8 ]. - nextBytecode = 192 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self gen_bytecodePrimIdenticalSistaV1_shortConditionalJumpFalse_9 ]. - nextBytecode = 193 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimIdenticalSistaV1_shortConditionalJumpFalse_10 ]. - nextBytecode = 194 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimIdenticalSistaV1_shortConditionalJumpFalse_11 ]. - nextBytecode = 195 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimIdenticalSistaV1_shortConditionalJumpFalse_12 ]. - nextBytecode = 196 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimIdenticalSistaV1_shortConditionalJumpFalse_13 ]. - nextBytecode = 197 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimIdenticalSistaV1_shortConditionalJumpFalse_14 ]. - nextBytecode = 198 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimIdenticalSistaV1_shortConditionalJumpFalse_15 ]. - nextBytecode = 199 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimIdenticalSistaV1_shortConditionalJumpFalse_16 ] ]. + | jump1 b507 s57 s54 t1 jump6 jump3 b503 currentBlock t3 t0 jump5 jump2 live t2 jump4 | live := 0. t0 := self allocateRegNotConflictingWith: live @@ -2886,76 +2795,7 @@ DruidTestRTLCompiler >> gen_bytecodePrimIdenticalSistaV1_shortConditionalJumpTru DruidTestRTLCompiler >> gen_bytecodePrimNotIdenticalSistaV1 [ "AutoGenerated by Druid" - | jump1 b507 s57 s54 t1 jump6 jump3 nextFixup b503 currentBlock t3 t0 nextBytecode jump2 jump5 live t2 jump4 | - nextFixup := self fixupAt: bytecodePC + 1. - nextFixup notAFixup ifTrue: [ - nextBytecode := objectMemory - fetchByte: bytecodePC + 1 - ofObject: methodObj. - nextBytecode = 184 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimNotIdenticalSistaV1_shortConditionalJumpTrue_1 ]. - nextBytecode = 185 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimNotIdenticalSistaV1_shortConditionalJumpTrue_2 ]. - nextBytecode = 186 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimNotIdenticalSistaV1_shortConditionalJumpTrue_3 ]. - nextBytecode = 187 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimNotIdenticalSistaV1_shortConditionalJumpTrue_4 ]. - nextBytecode = 188 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimNotIdenticalSistaV1_shortConditionalJumpTrue_5 ]. - nextBytecode = 189 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimNotIdenticalSistaV1_shortConditionalJumpTrue_6 ]. - nextBytecode = 190 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimNotIdenticalSistaV1_shortConditionalJumpTrue_7 ]. - nextBytecode = 191 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimNotIdenticalSistaV1_shortConditionalJumpTrue_8 ]. - nextBytecode = 192 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimNotIdenticalSistaV1_shortConditionalJumpFalse_9 ]. - nextBytecode = 193 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimNotIdenticalSistaV1_shortConditionalJumpFalse_10 ]. - nextBytecode = 194 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimNotIdenticalSistaV1_shortConditionalJumpFalse_11 ]. - nextBytecode = 195 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimNotIdenticalSistaV1_shortConditionalJumpFalse_12 ]. - nextBytecode = 196 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimNotIdenticalSistaV1_shortConditionalJumpFalse_13 ]. - nextBytecode = 197 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimNotIdenticalSistaV1_shortConditionalJumpFalse_14 ]. - nextBytecode = 198 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimNotIdenticalSistaV1_shortConditionalJumpFalse_15 ]. - nextBytecode = 199 ifTrue: [ - bytecodePC := bytecodePC + 1. - ^ self - gen_bytecodePrimNotIdenticalSistaV1_shortConditionalJumpFalse_16 ] ]. + | jump1 b507 s57 s54 t1 jump6 jump3 b503 currentBlock t3 t0 jump5 jump2 live t2 jump4 | live := 0. t0 := self allocateRegNotConflictingWith: live @@ -9628,9 +9468,9 @@ DruidTestRTLCompiler >> gen_primitiveIntegerDivideByConstant [ self DivR: SendNumArgsReg R: ClassReg - Quo: SendNumArgsReg - Rem: ClassReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. + Quo: ClassReg + Rem: SendNumArgsReg. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -10005,9 +9845,9 @@ DruidTestRTLCompiler >> gen_primitiveModByConstant [ self DivR: SendNumArgsReg R: ClassReg - Quo: SendNumArgsReg - Rem: ClassReg. - self MoveR: ClassReg R: ReceiverResultReg. + Quo: ClassReg + Rem: SendNumArgsReg. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] diff --git a/Druid-Tests/SimpleDruidTestRTLCompiler.class.st b/Druid-Tests/SimpleDruidTestRTLCompiler.class.st index e9877ed3..c6298e22 100644 --- a/Druid-Tests/SimpleDruidTestRTLCompiler.class.st +++ b/Druid-Tests/SimpleDruidTestRTLCompiler.class.st @@ -1,6 +1,9 @@ Class { #name : #SimpleDruidTestRTLCompiler, #superclass : #SimpleDruidJIT, + #instVars : [ + 'methodOrBlockNumTemps' + ], #category : #'Druid-Tests' } @@ -8,8 +11,15 @@ Class { SimpleDruidTestRTLCompiler class >> bytecodeTable [ - ^ { { 1. 0. 0. #gen_BytecodeWithNoFrameInstVarRefAnnotation. - #isInstVarRef. #needsFrameNever:. 1 } } + ^ { + { 1. 0. 0. #gen_BytecodeWithNoFrameInstVarRefAnnotation. + #isInstVarRef. #needsFrameNever:. 1 }. + { 1. 77. 77. #gen_BytecodeWithNoFrameInstVarRefAnnotation }. + { 1. 90. 90. #gen_BytecodeWithNoFrameInstVarRefAnnotation }. + { 1. 91. 91. #gen_BytecodeWithNoFrameInstVarRefAnnotation }. + { 1. 176. 176. #gen_BytecodeWithNoFrameInstVarRefAnnotation }. + { 1. 184. 184. #gen_BytecodeWithNoFrameInstVarRefAnnotation }. + { 1. 192. 192. #gen_BytecodeWithNoFrameInstVarRefAnnotation } } ] { #category : #'class initialization' } @@ -80,12 +90,6 @@ SimpleDruidTestRTLCompiler >> compileEntry [ ] -{ #category : #accessing } -SimpleDruidTestRTLCompiler >> deadCode [ - - ^ deadCode -] - { #category : #accessing } SimpleDruidTestRTLCompiler >> extA [ @@ -214,776 +218,372 @@ SimpleDruidTestRTLCompiler >> gen_ReturnTopFromMethod [ ] { #category : #generated } -SimpleDruidTestRTLCompiler >> gen_StoreAndPopReceiverVariableBytecode0 [ +SimpleDruidTestRTLCompiler >> gen_assertIsIgnored [ + + | currentBlock | + self MoveCq: 17 R: ReceiverResultReg. + self RetN: 1 * objectMemory wordSize. + ^ CompletePrimitive +] + +{ #category : #generated } +SimpleDruidTestRTLCompiler >> gen_branchingWithAssigments [ + + | currentBlock jump0 jump1 | + self CmpCq: 0 R: ReceiverResultReg. + jump0 := self JumpLessOrEqual: 0. + self MoveCq: 17 R: ReceiverResultReg. + jump1 := self Jump: 0. + currentBlock := self Label. + jump0 jmpTarget: currentBlock. + self MoveCq: 42 R: ReceiverResultReg. + currentBlock := self Label. + jump1 jmpTarget: currentBlock. + self RetN: 1 * objectMemory wordSize. + ^ CompletePrimitive +] + +{ #category : #generated } +SimpleDruidTestRTLCompiler >> gen_bytecodePopOnTwoBranches [ "AutoGenerated by Druid" - | jump1 jump7 jumpNext t1 jump6 jump3 jump9 currentBlock t0 jump5 jump2 jumpTrue jump8 live t2 jump4 | - live := 0. + | t0 jump1 s2 currentBlock jump2 | + t0 := ClassReg. self annotateBytecode: self Label. - self ensureReceiverResultRegContainsSelf. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). - self MoveR: ReceiverResultReg R: t0. - t1 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t1). - (self ssValue: 0) copyToReg: t1. - t2 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t2). - self MoveM64: 0 r: t0 R: t2. - self ArithmeticShiftRightCq: 23 R: t2. - self AndCq: 1 R: t2. - self ssFlushStack. - self CmpCq: 0 R: t2. - jump1 := self JumpZero: 0. - self deoptimize. + self MoveMw: 0 r: SPReg R: ClassReg. + self CmpCq: 0 R: t0. + jump1 := self JumpLessOrEqual: 0. + self MoveMw: 0 r: SPReg R: ClassReg. + self PopN: 1. jump2 := self Jump: 0. - deadCode := false. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self ssPop: 1. + self MoveMw: 0 r: SPReg R: ClassReg. + self PopN: 1. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self PushR: t0. + ^ 0 +] + +{ #category : #generated } +SimpleDruidTestRTLCompiler >> gen_bytecodePrimAdd [ + "AutoGenerated by Druid" + + | currentBlock | + self genSend: -1 numArgs: 1 sendTable: ordinarySendTrampolines. + ^ 0 +] + +{ #category : #generated } +SimpleDruidTestRTLCompiler >> gen_bytecodePrimIdenticalSistaV1 [ + "AutoGenerated by Druid" + + | jump5 s46 jump3 t3 s86 jump1 t1 currentBlock b505 s90 jumpNext jump6 jump4 t4 s87 jumpTrue s63 jump2 s21 s85 t2 s91 t0 b481 | + t0 := ClassReg. + t1 := SendNumArgsReg. + t2 := Extra0Reg. + t3 := Extra1Reg. + t4 := Extra2Reg. + self MoveMw: 1 << 3 r: SPReg R: ClassReg. + self MoveMw: 0 << 3 r: SPReg R: SendNumArgsReg. self MoveR: t0 R: t2. self AndCq: 7 R: t2. self CmpCq: 0 R: t2. jump1 := self JumpNonZero: 0. - self MoveR: t0 R: t2. - self AndCq: objectMemory getMemoryMap getSpaceMaskToUse R: t2. - self CmpCq: objectMemory getMemoryMap getOldSpaceMask R: t2. - jump3 := self JumpNonZero: 0. - self MoveR: t1 R: t2. - self AndCq: 7 R: t2. + self MoveM64: 0 r: t0 R: t2. + self AndCq: 16r3FFFF7 R: t2. self CmpCq: 0 R: t2. - jump4 := self JumpNonZero: 0. - self MoveR: t1 R: t2. - self AndCq: objectMemory getMemoryMap getSpaceMaskToUse R: t2. - self CmpCq: objectMemory getMemoryMap getNewSpaceMask R: t2. - jump5 := self JumpNonZero: 0. - self MoveR: t1 R: t2. - self CmpCq: objectMemory getMemoryMap getNewSpaceStart R: t2. - jumpTrue := self JumpAboveOrEqual: 0. - self MoveCq: 0 R: t2. + jump2 := self JumpNonZero: 0. + self MoveM64: 8 r: t0 R: t2. + self MoveR: t1 R: t0. + b505 := self Label. + self MoveR: t2 R: t3. + self AndCq: 7 R: t3. + self CmpCq: 0 R: t3. + jump3 := self JumpNonZero: 0. + self MoveM64: 0 r: t2 R: t3. + self AndCq: 16r3FFFF7 R: t3. + s21 := 0. + self CmpCq: s21 R: t3. + jumpTrue := self JumpZero: 0. + self MoveCq: 0 R: t3. jumpNext := self Jump: 0. jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t2. + self MoveCq: 1 R: t3. jumpNext jmpTarget: self Label. - self CmpCq: 1 R: t2. - jump6 := self JumpNonZero: 0. - self MoveM64: 0 r: t0 R: t2. - self ArithmeticShiftRightCq: 29 R: t2. - self AndCq: 1 R: t2. - self CmpCq: 0 R: t2. - jump7 := self JumpNonZero: 0. - self MoveR: t0 R: TempReg. - backEnd saveAndRestoreLinkRegAround: [ - self CallRT: ceStoreCheckTrampoline ]. - self TstCq: 7 R: t1. - jump8 := self JumpNonZero: 0. - jump9 := self JumpZero: 0. - currentBlock := self Label. - jump5 jmpTarget: currentBlock. - self MoveCq: 0 R: t2. - currentBlock := self Label. - jump6 jmpTarget: currentBlock. + self CmpCq: 1 R: t3. + jump4 := self JumpNonZero: 0. + self MoveR: t2 R: t3. + self MoveR: t0 R: t4. + self MoveM64: 8 r: t3 R: t3. + self MoveR: t3 R: t2. + self MoveR: t4 R: t0. + jump5 := self Jump: b505. currentBlock := self Label. - jump1 jmpTarget: currentBlock. jump3 jmpTarget: currentBlock. jump4 jmpTarget: currentBlock. - jump7 jmpTarget: currentBlock. - self TstCq: 7 R: t1. - jump7 := self JumpNonZero: 0. - currentBlock := self Label. - jump9 jmpTarget: currentBlock. - self CmpCq: objectMemory nilObject R: t1. - jump9 := self JumpBelow: 0. - self MoveR: t1 R: t2. - self CmpCq: objectMemory trueObject R: t2. - jumpTrue := self JumpBelowOrEqual: 0. - self MoveCq: 0 R: t2. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t2. - jumpNext jmpTarget: self Label. + self MoveR: t0 R: t3. jump4 := self Jump: 0. currentBlock := self Label. - jump9 jmpTarget: currentBlock. - self MoveCq: 0 R: t2. + jump1 jmpTarget: currentBlock. + jump2 jmpTarget: currentBlock. + self MoveR: t0 R: t2. + self MoveR: t1 R: t3. currentBlock := self Label. jump4 jmpTarget: currentBlock. - self CmpCq: 1 R: t2. - jump4 := self JumpZero: 0. - self CmpCq: objectMemory getMemoryMap getNewSpaceStart R: t1. - jump9 := self JumpBelow: 0. - self MoveM64: 0 r: t0 R: t2. - self ArithmeticShiftRightCq: 29 R: t2. - self AndCq: 1 R: t2. - self CmpCq: 0 R: t2. - jump3 := self JumpNonZero: 0. - self MoveR: t0 R: t2. + self MoveR: t3 R: t4. + self AndCq: 7 R: t4. + self CmpCq: 0 R: t4. + jump4 := self JumpNonZero: 0. + self MoveM64: 0 r: t3 R: t4. + self AndCq: 16r3FFFF7 R: t4. + s46 := 0. + self CmpCq: s46 R: t4. + jumpTrue := self JumpZero: 0. + self MoveCq: 0 R: t4. + jumpNext := self Jump: 0. + jumpTrue jmpTarget: self Label. + self MoveCq: 1 R: t4. + jumpNext jmpTarget: self Label. + self CmpCq: 1 R: t4. + jump2 := self JumpNonZero: 0. + self MoveR: t2 R: t4. + self MoveM64: 8 r: t3 R: t3. + b481 := self Label. + self MoveR: t3 R: t2. self AndCq: 7 R: t2. self CmpCq: 0 R: t2. jump1 := self JumpNonZero: 0. - self MoveR: t0 R: t2. - self AndCq: objectMemory getMemoryMap getSpaceMaskToUse R: t2. - self CmpCq: objectMemory getMemoryMap getPermSpaceMask R: t2. + self MoveM64: 0 r: t3 R: t2. + self AndCq: 16r3FFFF7 R: t2. + s63 := 0. + self CmpCq: s63 R: t2. jumpTrue := self JumpZero: 0. self MoveCq: 0 R: t2. jumpNext := self Jump: 0. jumpTrue jmpTarget: self Label. self MoveCq: 1 R: t2. jumpNext jmpTarget: self Label. - jump6 := self Jump: 0. + self CmpCq: 1 R: t2. + jump3 := self JumpNonZero: 0. + self MoveR: t3 R: t2. + self MoveR: t4 R: t0. + self MoveM64: 8 r: t2 R: t2. + self MoveR: t2 R: t3. + self MoveR: t0 R: t4. + jump6 := self Jump: b481. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveCq: 0 R: t2. - currentBlock := self Label. - jump6 jmpTarget: currentBlock. - self CmpCq: 1 R: t2. - jump6 := self JumpNonZero: 0. - self MoveR: t1 R: t2. - self AndCq: objectMemory getMemoryMap getSpaceMaskToUse R: t2. - self CmpCq: objectMemory getMemoryMap getPermSpaceMask R: t2. - jump1 := self JumpZero: 0. - self MoveR: t0 R: TempReg. - backEnd saveAndRestoreLinkRegAround: [ - self CallRT: ceStoreCheckTrampoline ]. + jump3 jmpTarget: currentBlock. + self MoveR: t3 R: t2. + jump3 := self Jump: 0. currentBlock := self Label. - jump8 jmpTarget: currentBlock. - jump7 jmpTarget: currentBlock. jump4 jmpTarget: currentBlock. - jump9 jmpTarget: currentBlock. + jump2 jmpTarget: currentBlock. + self MoveR: t2 R: t4. + self MoveR: t3 R: t2. + currentBlock := self Label. jump3 jmpTarget: currentBlock. - jump6 jmpTarget: currentBlock. - jump1 jmpTarget: currentBlock. - self MoveR: t1 M64: 8 r: t0. + self PopN: 2. + self CmpR: t2 R: t4. + jump3 := self JumpNonZero: 0. + s85 := objectMemory trueObject. + s86 := s85. + s86 = nil ifTrue: [ ^ 0 ]. + self MoveCq: s86 R: t3. + jump2 := self Jump: 0. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + s90 := objectMemory falseObject. + s91 := s90. + s91 = nil ifTrue: [ ^ 0 ]. + self MoveCq: s91 R: t3. currentBlock := self Label. jump2 jmpTarget: currentBlock. + self PushR: t3. ^ 0 ] { #category : #generated } -SimpleDruidTestRTLCompiler >> gen_StoreAndPopReceiverVariableBytecode1 [ +SimpleDruidTestRTLCompiler >> gen_bytecodePrimNotIdenticalSistaV1 [ "AutoGenerated by Druid" - | jump1 jump7 jumpNext t1 jump6 jump3 jump9 currentBlock t0 jump5 jump2 jumpTrue jump8 live t2 jump4 | - live := 0. - self annotateBytecode: self Label. - self ensureReceiverResultRegContainsSelf. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). - self MoveR: ReceiverResultReg R: t0. - t1 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t1). - (self ssValue: 0) copyToReg: t1. - t2 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t2). + | jump5 s46 jump3 t3 s86 jump1 t1 currentBlock b505 s90 jumpNext jump6 jump4 t4 s87 jumpTrue s63 jump2 s21 s85 t2 s91 t0 b481 | + t0 := ClassReg. + t1 := SendNumArgsReg. + t2 := Extra0Reg. + t3 := Extra1Reg. + t4 := Extra2Reg. + self MoveMw: 1 << 3 r: SPReg R: ClassReg. + self MoveMw: 0 << 3 r: SPReg R: SendNumArgsReg. + self MoveR: t0 R: t2. + self AndCq: 7 R: t2. + self CmpCq: 0 R: t2. + jump1 := self JumpNonZero: 0. self MoveM64: 0 r: t0 R: t2. - self ArithmeticShiftRightCq: 23 R: t2. - self AndCq: 1 R: t2. - self ssFlushStack. + self AndCq: 16r3FFFF7 R: t2. self CmpCq: 0 R: t2. - jump1 := self JumpZero: 0. - self deoptimize. - jump2 := self Jump: 0. - deadCode := false. + jump2 := self JumpNonZero: 0. + self MoveM64: 8 r: t0 R: t2. + self MoveR: t1 R: t0. + b505 := self Label. + self MoveR: t2 R: t3. + self AndCq: 7 R: t3. + self CmpCq: 0 R: t3. + jump3 := self JumpNonZero: 0. + self MoveM64: 0 r: t2 R: t3. + self AndCq: 16r3FFFF7 R: t3. + s21 := 0. + self CmpCq: s21 R: t3. + jumpTrue := self JumpZero: 0. + self MoveCq: 0 R: t3. + jumpNext := self Jump: 0. + jumpTrue jmpTarget: self Label. + self MoveCq: 1 R: t3. + jumpNext jmpTarget: self Label. + self CmpCq: 1 R: t3. + jump4 := self JumpNonZero: 0. + self MoveR: t2 R: t3. + self MoveR: t0 R: t4. + self MoveM64: 8 r: t3 R: t3. + self MoveR: t3 R: t2. + self MoveR: t4 R: t0. + jump5 := self Jump: b505. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + jump4 jmpTarget: currentBlock. + self MoveR: t0 R: t3. + jump4 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self ssPop: 1. + jump2 jmpTarget: currentBlock. self MoveR: t0 R: t2. + self MoveR: t1 R: t3. + currentBlock := self Label. + jump4 jmpTarget: currentBlock. + self MoveR: t3 R: t4. + self AndCq: 7 R: t4. + self CmpCq: 0 R: t4. + jump4 := self JumpNonZero: 0. + self MoveM64: 0 r: t3 R: t4. + self AndCq: 16r3FFFF7 R: t4. + s46 := 0. + self CmpCq: s46 R: t4. + jumpTrue := self JumpZero: 0. + self MoveCq: 0 R: t4. + jumpNext := self Jump: 0. + jumpTrue jmpTarget: self Label. + self MoveCq: 1 R: t4. + jumpNext jmpTarget: self Label. + self CmpCq: 1 R: t4. + jump2 := self JumpNonZero: 0. + self MoveR: t2 R: t4. + self MoveM64: 8 r: t3 R: t3. + b481 := self Label. + self MoveR: t3 R: t2. self AndCq: 7 R: t2. self CmpCq: 0 R: t2. jump1 := self JumpNonZero: 0. - self MoveR: t0 R: t2. - self AndCq: objectMemory getMemoryMap getSpaceMaskToUse R: t2. - self CmpCq: objectMemory getMemoryMap getOldSpaceMask R: t2. - jump3 := self JumpNonZero: 0. - self MoveR: t1 R: t2. - self AndCq: 7 R: t2. - self CmpCq: 0 R: t2. - jump4 := self JumpNonZero: 0. - self MoveR: t1 R: t2. - self AndCq: objectMemory getMemoryMap getSpaceMaskToUse R: t2. - self CmpCq: objectMemory getMemoryMap getNewSpaceMask R: t2. - jump5 := self JumpNonZero: 0. - self MoveR: t1 R: t2. - self CmpCq: objectMemory getMemoryMap getNewSpaceStart R: t2. - jumpTrue := self JumpAboveOrEqual: 0. + self MoveM64: 0 r: t3 R: t2. + self AndCq: 16r3FFFF7 R: t2. + s63 := 0. + self CmpCq: s63 R: t2. + jumpTrue := self JumpZero: 0. self MoveCq: 0 R: t2. jumpNext := self Jump: 0. jumpTrue jmpTarget: self Label. self MoveCq: 1 R: t2. jumpNext jmpTarget: self Label. self CmpCq: 1 R: t2. - jump6 := self JumpNonZero: 0. - self MoveM64: 0 r: t0 R: t2. - self ArithmeticShiftRightCq: 29 R: t2. - self AndCq: 1 R: t2. - self CmpCq: 0 R: t2. - jump7 := self JumpNonZero: 0. - self MoveR: t0 R: TempReg. - backEnd saveAndRestoreLinkRegAround: [ - self CallRT: ceStoreCheckTrampoline ]. - self TstCq: 7 R: t1. - jump8 := self JumpNonZero: 0. - jump9 := self JumpZero: 0. - currentBlock := self Label. - jump5 jmpTarget: currentBlock. - self MoveCq: 0 R: t2. - currentBlock := self Label. - jump6 jmpTarget: currentBlock. - currentBlock := self Label. - jump1 jmpTarget: currentBlock. - jump3 jmpTarget: currentBlock. - jump4 jmpTarget: currentBlock. - jump7 jmpTarget: currentBlock. - self TstCq: 7 R: t1. - jump7 := self JumpNonZero: 0. - currentBlock := self Label. - jump9 jmpTarget: currentBlock. - self CmpCq: objectMemory nilObject R: t1. - jump9 := self JumpBelow: 0. - self MoveR: t1 R: t2. - self CmpCq: objectMemory trueObject R: t2. - jumpTrue := self JumpBelowOrEqual: 0. - self MoveCq: 0 R: t2. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t2. - jumpNext jmpTarget: self Label. - jump4 := self Jump: 0. - currentBlock := self Label. - jump9 jmpTarget: currentBlock. - self MoveCq: 0 R: t2. - currentBlock := self Label. - jump4 jmpTarget: currentBlock. - self CmpCq: 1 R: t2. - jump4 := self JumpZero: 0. - self CmpCq: objectMemory getMemoryMap getNewSpaceStart R: t1. - jump9 := self JumpBelow: 0. - self MoveM64: 0 r: t0 R: t2. - self ArithmeticShiftRightCq: 29 R: t2. - self AndCq: 1 R: t2. - self CmpCq: 0 R: t2. - jump3 := self JumpNonZero: 0. - self MoveR: t0 R: t2. - self AndCq: 7 R: t2. - self CmpCq: 0 R: t2. - jump1 := self JumpNonZero: 0. - self MoveR: t0 R: t2. - self AndCq: objectMemory getMemoryMap getSpaceMaskToUse R: t2. - self CmpCq: objectMemory getMemoryMap getPermSpaceMask R: t2. - jumpTrue := self JumpZero: 0. - self MoveCq: 0 R: t2. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t2. - jumpNext jmpTarget: self Label. - jump6 := self Jump: 0. - currentBlock := self Label. - jump1 jmpTarget: currentBlock. - self MoveCq: 0 R: t2. - currentBlock := self Label. - jump6 jmpTarget: currentBlock. - self CmpCq: 1 R: t2. - jump6 := self JumpNonZero: 0. - self MoveR: t1 R: t2. - self AndCq: objectMemory getMemoryMap getSpaceMaskToUse R: t2. - self CmpCq: objectMemory getMemoryMap getPermSpaceMask R: t2. - jump1 := self JumpZero: 0. - self MoveR: t0 R: TempReg. - backEnd saveAndRestoreLinkRegAround: [ - self CallRT: ceStoreCheckTrampoline ]. - currentBlock := self Label. - jump8 jmpTarget: currentBlock. - jump7 jmpTarget: currentBlock. - jump4 jmpTarget: currentBlock. - jump9 jmpTarget: currentBlock. - jump3 jmpTarget: currentBlock. - jump6 jmpTarget: currentBlock. - jump1 jmpTarget: currentBlock. - self MoveR: t1 M64: 16 r: t0. - currentBlock := self Label. - jump2 jmpTarget: currentBlock. - ^ 0 -] - -{ #category : #generated } -SimpleDruidTestRTLCompiler >> gen_StoreAndPopReceiverVariableBytecode2 [ - "AutoGenerated by Druid" - - | jump1 jump7 jumpNext t1 jump6 jump3 jump9 currentBlock t0 jump5 jump2 jumpTrue jump8 live t2 jump4 | - live := 0. - self annotateBytecode: self Label. - self ensureReceiverResultRegContainsSelf. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). - self MoveR: ReceiverResultReg R: t0. - t1 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t1). - (self ssValue: 0) copyToReg: t1. - t2 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t2). - self MoveM64: 0 r: t0 R: t2. - self ArithmeticShiftRightCq: 23 R: t2. - self AndCq: 1 R: t2. - self ssFlushStack. - self CmpCq: 0 R: t2. - jump1 := self JumpZero: 0. - self deoptimize. - jump2 := self Jump: 0. - deadCode := false. - currentBlock := self Label. - jump1 jmpTarget: currentBlock. - self ssPop: 1. - self MoveR: t0 R: t2. - self AndCq: 7 R: t2. - self CmpCq: 0 R: t2. - jump1 := self JumpNonZero: 0. - self MoveR: t0 R: t2. - self AndCq: objectMemory getMemoryMap getSpaceMaskToUse R: t2. - self CmpCq: objectMemory getMemoryMap getOldSpaceMask R: t2. jump3 := self JumpNonZero: 0. - self MoveR: t1 R: t2. - self AndCq: 7 R: t2. - self CmpCq: 0 R: t2. - jump4 := self JumpNonZero: 0. - self MoveR: t1 R: t2. - self AndCq: objectMemory getMemoryMap getSpaceMaskToUse R: t2. - self CmpCq: objectMemory getMemoryMap getNewSpaceMask R: t2. - jump5 := self JumpNonZero: 0. - self MoveR: t1 R: t2. - self CmpCq: objectMemory getMemoryMap getNewSpaceStart R: t2. - jumpTrue := self JumpAboveOrEqual: 0. - self MoveCq: 0 R: t2. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t2. - jumpNext jmpTarget: self Label. - self CmpCq: 1 R: t2. - jump6 := self JumpNonZero: 0. - self MoveM64: 0 r: t0 R: t2. - self ArithmeticShiftRightCq: 29 R: t2. - self AndCq: 1 R: t2. - self CmpCq: 0 R: t2. - jump7 := self JumpNonZero: 0. - self MoveR: t0 R: TempReg. - backEnd saveAndRestoreLinkRegAround: [ - self CallRT: ceStoreCheckTrampoline ]. - self TstCq: 7 R: t1. - jump8 := self JumpNonZero: 0. - jump9 := self JumpZero: 0. - currentBlock := self Label. - jump5 jmpTarget: currentBlock. - self MoveCq: 0 R: t2. - currentBlock := self Label. - jump6 jmpTarget: currentBlock. + self MoveR: t3 R: t2. + self MoveR: t4 R: t0. + self MoveM64: 8 r: t2 R: t2. + self MoveR: t2 R: t3. + self MoveR: t0 R: t4. + jump6 := self Jump: b481. currentBlock := self Label. jump1 jmpTarget: currentBlock. jump3 jmpTarget: currentBlock. - jump4 jmpTarget: currentBlock. - jump7 jmpTarget: currentBlock. - self TstCq: 7 R: t1. - jump7 := self JumpNonZero: 0. - currentBlock := self Label. - jump9 jmpTarget: currentBlock. - self CmpCq: objectMemory nilObject R: t1. - jump9 := self JumpBelow: 0. - self MoveR: t1 R: t2. - self CmpCq: objectMemory trueObject R: t2. - jumpTrue := self JumpBelowOrEqual: 0. - self MoveCq: 0 R: t2. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t2. - jumpNext jmpTarget: self Label. - jump4 := self Jump: 0. - currentBlock := self Label. - jump9 jmpTarget: currentBlock. - self MoveCq: 0 R: t2. - currentBlock := self Label. - jump4 jmpTarget: currentBlock. - self CmpCq: 1 R: t2. - jump4 := self JumpZero: 0. - self CmpCq: objectMemory getMemoryMap getNewSpaceStart R: t1. - jump9 := self JumpBelow: 0. - self MoveM64: 0 r: t0 R: t2. - self ArithmeticShiftRightCq: 29 R: t2. - self AndCq: 1 R: t2. - self CmpCq: 0 R: t2. - jump3 := self JumpNonZero: 0. - self MoveR: t0 R: t2. - self AndCq: 7 R: t2. - self CmpCq: 0 R: t2. - jump1 := self JumpNonZero: 0. - self MoveR: t0 R: t2. - self AndCq: objectMemory getMemoryMap getSpaceMaskToUse R: t2. - self CmpCq: objectMemory getMemoryMap getPermSpaceMask R: t2. - jumpTrue := self JumpZero: 0. - self MoveCq: 0 R: t2. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t2. - jumpNext jmpTarget: self Label. - jump6 := self Jump: 0. - currentBlock := self Label. - jump1 jmpTarget: currentBlock. - self MoveCq: 0 R: t2. - currentBlock := self Label. - jump6 jmpTarget: currentBlock. - self CmpCq: 1 R: t2. - jump6 := self JumpNonZero: 0. - self MoveR: t1 R: t2. - self AndCq: objectMemory getMemoryMap getSpaceMaskToUse R: t2. - self CmpCq: objectMemory getMemoryMap getPermSpaceMask R: t2. - jump1 := self JumpZero: 0. - self MoveR: t0 R: TempReg. - backEnd saveAndRestoreLinkRegAround: [ - self CallRT: ceStoreCheckTrampoline ]. + self MoveR: t3 R: t2. + jump3 := self Jump: 0. currentBlock := self Label. - jump8 jmpTarget: currentBlock. - jump7 jmpTarget: currentBlock. jump4 jmpTarget: currentBlock. - jump9 jmpTarget: currentBlock. - jump3 jmpTarget: currentBlock. - jump6 jmpTarget: currentBlock. - jump1 jmpTarget: currentBlock. - self MoveR: t1 M64: 24 r: t0. - currentBlock := self Label. jump2 jmpTarget: currentBlock. - ^ 0 -] - -{ #category : #generated } -SimpleDruidTestRTLCompiler >> gen_StoreAndPopReceiverVariableBytecode3 [ - "AutoGenerated by Druid" - - | jump1 jump7 jumpNext t1 jump6 jump3 jump9 currentBlock t0 jump5 jump2 jumpTrue jump8 live t2 jump4 | - live := 0. - self annotateBytecode: self Label. - self ensureReceiverResultRegContainsSelf. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). - self MoveR: ReceiverResultReg R: t0. - t1 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t1). - (self ssValue: 0) copyToReg: t1. - t2 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t2). - self MoveM64: 0 r: t0 R: t2. - self ArithmeticShiftRightCq: 23 R: t2. - self AndCq: 1 R: t2. - self ssFlushStack. - self CmpCq: 0 R: t2. - jump1 := self JumpZero: 0. - self deoptimize. - jump2 := self Jump: 0. - deadCode := false. - currentBlock := self Label. - jump1 jmpTarget: currentBlock. - self ssPop: 1. - self MoveR: t0 R: t2. - self AndCq: 7 R: t2. - self CmpCq: 0 R: t2. - jump1 := self JumpNonZero: 0. - self MoveR: t0 R: t2. - self AndCq: objectMemory getMemoryMap getSpaceMaskToUse R: t2. - self CmpCq: objectMemory getMemoryMap getOldSpaceMask R: t2. - jump3 := self JumpNonZero: 0. - self MoveR: t1 R: t2. - self AndCq: 7 R: t2. - self CmpCq: 0 R: t2. - jump4 := self JumpNonZero: 0. - self MoveR: t1 R: t2. - self AndCq: objectMemory getMemoryMap getSpaceMaskToUse R: t2. - self CmpCq: objectMemory getMemoryMap getNewSpaceMask R: t2. - jump5 := self JumpNonZero: 0. - self MoveR: t1 R: t2. - self CmpCq: objectMemory getMemoryMap getNewSpaceStart R: t2. - jumpTrue := self JumpAboveOrEqual: 0. - self MoveCq: 0 R: t2. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t2. - jumpNext jmpTarget: self Label. - self CmpCq: 1 R: t2. - jump6 := self JumpNonZero: 0. - self MoveM64: 0 r: t0 R: t2. - self ArithmeticShiftRightCq: 29 R: t2. - self AndCq: 1 R: t2. - self CmpCq: 0 R: t2. - jump7 := self JumpNonZero: 0. - self MoveR: t0 R: TempReg. - backEnd saveAndRestoreLinkRegAround: [ - self CallRT: ceStoreCheckTrampoline ]. - self TstCq: 7 R: t1. - jump8 := self JumpNonZero: 0. - jump9 := self JumpZero: 0. - currentBlock := self Label. - jump5 jmpTarget: currentBlock. - self MoveCq: 0 R: t2. - currentBlock := self Label. - jump6 jmpTarget: currentBlock. - currentBlock := self Label. - jump1 jmpTarget: currentBlock. - jump3 jmpTarget: currentBlock. - jump4 jmpTarget: currentBlock. - jump7 jmpTarget: currentBlock. - self TstCq: 7 R: t1. - jump7 := self JumpNonZero: 0. - currentBlock := self Label. - jump9 jmpTarget: currentBlock. - self CmpCq: objectMemory nilObject R: t1. - jump9 := self JumpBelow: 0. - self MoveR: t1 R: t2. - self CmpCq: objectMemory trueObject R: t2. - jumpTrue := self JumpBelowOrEqual: 0. - self MoveCq: 0 R: t2. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t2. - jumpNext jmpTarget: self Label. - jump4 := self Jump: 0. - currentBlock := self Label. - jump9 jmpTarget: currentBlock. - self MoveCq: 0 R: t2. - currentBlock := self Label. - jump4 jmpTarget: currentBlock. - self CmpCq: 1 R: t2. - jump4 := self JumpZero: 0. - self CmpCq: objectMemory getMemoryMap getNewSpaceStart R: t1. - jump9 := self JumpBelow: 0. - self MoveM64: 0 r: t0 R: t2. - self ArithmeticShiftRightCq: 29 R: t2. - self AndCq: 1 R: t2. - self CmpCq: 0 R: t2. - jump3 := self JumpNonZero: 0. - self MoveR: t0 R: t2. - self AndCq: 7 R: t2. - self CmpCq: 0 R: t2. - jump1 := self JumpNonZero: 0. - self MoveR: t0 R: t2. - self AndCq: objectMemory getMemoryMap getSpaceMaskToUse R: t2. - self CmpCq: objectMemory getMemoryMap getPermSpaceMask R: t2. - jumpTrue := self JumpZero: 0. - self MoveCq: 0 R: t2. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t2. - jumpNext jmpTarget: self Label. - jump6 := self Jump: 0. - currentBlock := self Label. - jump1 jmpTarget: currentBlock. - self MoveCq: 0 R: t2. + self MoveR: t2 R: t4. + self MoveR: t3 R: t2. currentBlock := self Label. - jump6 jmpTarget: currentBlock. - self CmpCq: 1 R: t2. - jump6 := self JumpNonZero: 0. - self MoveR: t1 R: t2. - self AndCq: objectMemory getMemoryMap getSpaceMaskToUse R: t2. - self CmpCq: objectMemory getMemoryMap getPermSpaceMask R: t2. - jump1 := self JumpZero: 0. - self MoveR: t0 R: TempReg. - backEnd saveAndRestoreLinkRegAround: [ - self CallRT: ceStoreCheckTrampoline ]. + jump3 jmpTarget: currentBlock. + self PopN: 2. + self CmpR: t2 R: t4. + jump3 := self JumpZero: 0. + s85 := objectMemory trueObject. + s86 := s85. + s86 = nil ifTrue: [ ^ 0 ]. + self MoveCq: s86 R: t3. + jump2 := self Jump: 0. currentBlock := self Label. - jump8 jmpTarget: currentBlock. - jump7 jmpTarget: currentBlock. - jump4 jmpTarget: currentBlock. - jump9 jmpTarget: currentBlock. jump3 jmpTarget: currentBlock. - jump6 jmpTarget: currentBlock. - jump1 jmpTarget: currentBlock. - self MoveR: t1 M64: 32 r: t0. + s90 := objectMemory falseObject. + s91 := s90. + s91 = nil ifTrue: [ ^ 0 ]. + self MoveCq: s91 R: t3. currentBlock := self Label. jump2 jmpTarget: currentBlock. + self PushR: t3. ^ 0 ] { #category : #generated } -SimpleDruidTestRTLCompiler >> gen_assertIsIgnored [ - - | currentBlock | - self MoveCq: 17 R: ReceiverResultReg. - self RetN: 1 * objectMemory wordSize. - ^ CompletePrimitive -] - -{ #category : #generated } -SimpleDruidTestRTLCompiler >> gen_branchingWithAssigments [ - - | currentBlock jump0 jump1 | - self CmpCq: 0 R: ReceiverResultReg. - jump0 := self JumpLessOrEqual: 0. - self MoveCq: 17 R: ReceiverResultReg. - jump1 := self Jump: 0. - currentBlock := self Label. - jump0 jmpTarget: currentBlock. - self MoveCq: 42 R: ReceiverResultReg. - currentBlock := self Label. - jump1 jmpTarget: currentBlock. - self RetN: 1 * objectMemory wordSize. - ^ CompletePrimitive -] - -{ #category : #generated } -SimpleDruidTestRTLCompiler >> gen_bytecodePrimAdd [ +SimpleDruidTestRTLCompiler >> gen_bytecodePushOnTwoBranches [ "AutoGenerated by Druid" - | live currentBlock s2 | - live := 0. + | t0 jump1 s2 currentBlock jump2 | + t0 := ClassReg. self annotateBytecode: self Label. - self marshallSendArguments: 1. - self - genMarshalledSend: -1 - numArgs: 1 - sendTable: ordinarySendTrampolines. + self MoveMw: 0 r: SPReg R: ClassReg. + self CmpCq: 0 R: t0. + jump1 := self JumpLessOrEqual: 0. + self genPushConstant: 1. + jump2 := self Jump: 0. + currentBlock := self Label. + jump1 jmpTarget: currentBlock. + self genPushConstant: 2. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. ^ 0 ] { #category : #generated } -SimpleDruidTestRTLCompiler >> gen_bytecodePrimIdenticalSistaV1 [ +SimpleDruidTestRTLCompiler >> gen_bytecodeTwoPopOnTwoBranches [ "AutoGenerated by Druid" - | jump5 jump3 s53 s69 jump1 s75 t1 s36 b489 jumpNext currentBlock live jump4 s71 jumpTrue b485 jump2 t2 s68 t0 | - live := 0. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). - (self ssValue: 1) copyToReg: t0. - t1 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t1). - (self ssValue: 0) copyToReg: t1. - t2 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t2). - self MoveR: t0 R: t2. - self AndCq: 7 R: t2. - self CmpCq: 0 R: t2. - jump1 := self JumpNonZero: 0. - self MoveM64: 0 r: t0 R: t2. - self AndCq: 16r3FFFF7 R: t2. - self CmpCq: 0 R: t2. - jump2 := self JumpNonZero: 0. - self MoveM64: 8 r: t0 R: t2. - b489 := self Label. - self MoveR: t2 R: t0. - self AndCq: 7 R: t0. - self CmpCq: 0 R: t0. - jump3 := self JumpNonZero: 0. - self MoveM64: 0 r: t2 R: t0. - self AndCq: 16r3FFFF7 R: t0. + | t0 jump1 t1 currentBlock s2 jump2 t2 | + t0 := ClassReg. + t1 := SendNumArgsReg. + t2 := Extra0Reg. + self annotateBytecode: self Label. + self MoveMw: 0 r: SPReg R: ClassReg. self CmpCq: 0 R: t0. - jump4 := self JumpNonZero: 0. - self MoveM64: 8 r: t2 R: t0. - self MoveR: t0 R: t2. - jump5 := self Jump: b489. - currentBlock := self Label. - jump3 jmpTarget: currentBlock. - jump4 jmpTarget: currentBlock. - self MoveR: t2 R: t0. - jump4 := self Jump: 0. - currentBlock := self Label. - jump1 jmpTarget: currentBlock. - jump2 jmpTarget: currentBlock. - currentBlock := self Label. - jump4 jmpTarget: currentBlock. - self MoveR: t1 R: t2. - self AndCq: 7 R: t2. - self CmpCq: 0 R: t2. - jump4 := self JumpNonZero: 0. - self MoveM64: 0 r: t1 R: t2. - self AndCq: 16r3FFFF7 R: t2. - self CmpCq: 0 R: t2. - jumpTrue := self JumpZero: 0. - self MoveCq: 0 R: t2. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t2. - jumpNext jmpTarget: self Label. + jump1 := self JumpLessOrEqual: 0. + self MoveMw: 0 r: SPReg R: ClassReg. + self PopN: 1. + self MoveMw: 0 r: SPReg R: SendNumArgsReg. + self PopN: 1. jump2 := self Jump: 0. currentBlock := self Label. - jump4 jmpTarget: currentBlock. - s36 := 0. - self MoveCq: s36 R: t2. - currentBlock := self Label. - jump2 jmpTarget: currentBlock. - self CmpCq: 1 R: t2. - jump2 := self JumpNonZero: 0. - self MoveM64: 8 r: t1 R: t2. - b485 := self Label. - self MoveR: t2 R: t1. - self AndCq: 7 R: t1. - self CmpCq: 0 R: t1. - jump4 := self JumpNonZero: 0. - self MoveM64: 0 r: t2 R: t1. - self AndCq: 16r3FFFF7 R: t1. - self CmpCq: 0 R: t1. - jumpTrue := self JumpZero: 0. - self MoveCq: 0 R: t1. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t1. - jumpNext jmpTarget: self Label. - jump1 := self Jump: 0. - currentBlock := self Label. - jump4 jmpTarget: currentBlock. - s53 := 0. - self MoveCq: s53 R: t1. - currentBlock := self Label. - jump1 jmpTarget: currentBlock. - self CmpCq: 1 R: t1. - jump1 := self JumpNonZero: 0. - self MoveM64: 8 r: t2 R: t1. - self MoveR: t1 R: t2. - jump4 := self Jump: b485. - currentBlock := self Label. jump1 jmpTarget: currentBlock. + self MoveMw: 0 r: SPReg R: SendNumArgsReg. + self PopN: 1. + self MoveMw: 0 r: SPReg R: Extra0Reg. + self PopN: 1. + self MoveR: t1 R: t0. self MoveR: t2 R: t1. - jump1 := self Jump: 0. - currentBlock := self Label. - jump2 jmpTarget: currentBlock. - currentBlock := self Label. - jump1 jmpTarget: currentBlock. - self ssPop: 2. - self CmpR: t1 R: t0. - jump1 := self JumpNonZero: 0. - s68 := objectMemory trueObject. - s69 := s68. - jump2 := self Jump: 0. - currentBlock := self Label. - jump1 jmpTarget: currentBlock. - s71 := objectMemory falseObject. - s69 := s71. currentBlock := self Label. jump2 jmpTarget: currentBlock. - s69 = nil ifTrue: [ ^ 0 ]. - self ssPushConstant: s69. + self AddR: t1 R: t0. + self PushR: t0. ^ 0 ] @@ -991,36 +591,9 @@ SimpleDruidTestRTLCompiler >> gen_bytecodePrimIdenticalSistaV1 [ SimpleDruidTestRTLCompiler >> gen_bytecodeWithDeoptimisation [ "AutoGenerated by Druid" - | live currentBlock | - live := 0. - self ssFlushStack. - self deoptimize. - ^ 0 -] - -{ #category : #generated } -SimpleDruidTestRTLCompiler >> gen_bytecodeWithFlushStackOnDominator [ - "AutoGenerated by Druid" - - | t0 jump1 currentBlock jump2 live | - live := 0. - self annotateBytecode: self Label. - t0 := self allocateRegNotConflictingWith: live ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). - (self ssValue: 0) copyToReg: t0. - self ssFlushStack. - self CmpCq: 0 R: t0. - jump1 := self JumpLessOrEqual: 0. + | currentBlock t0 | + t0 := ClassReg. self deoptimize. - jump2 := self Jump: 0. - deadCode := false. - currentBlock := self Label. - jump1 jmpTarget: currentBlock. - (self ssValue: 0) copyToReg: t0. - self MoveR: t0 R: TempReg. - self CallRT: ceSendMustBeBooleanTrampoline. - currentBlock := self Label. - jump2 jmpTarget: currentBlock. ^ 0 ] @@ -1048,14 +621,10 @@ SimpleDruidTestRTLCompiler >> gen_bytecodeWithUnknownBytecodeSend [ SimpleDruidTestRTLCompiler >> gen_duplicateTopBytecode [ "AutoGenerated by Druid" - | live currentBlock t0 | - live := 0. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). - (self ssValue: 0) copyToReg: t0. - self ssPushRegister: t0. + | currentBlock t0 | + t0 := ClassReg. + self MoveMw: 0 << 3 r: SPReg R: ClassReg. + self PushR: t0. ^ 0 ] @@ -1082,36 +651,37 @@ SimpleDruidTestRTLCompiler >> gen_emptyPrimitiveWithArguments [ SimpleDruidTestRTLCompiler >> gen_extBBytecode [ "AutoGenerated by Druid" - | s6 s3 s16 s10 s2 currentBlock s7 s4 s17 s11 live s9 | - live := 0. + | s6 s3 s10 s5 s2 s18 currentBlock s12 s7 s4 s17 s11 s9 | s2 := byte1. s3 := numExtB. - 0 = s3 ifTrue: [ - 127 < s2 ifTrue: [ + s3 = 0 ifTrue: [ + s2 > 127 ifTrue: [ s6 := s2 - 256. s7 := s6. extB := s7. - s16 := numExtB. - s17 := s16 + 1. - numExtB := s17. + s17 := numExtB. + s18 := s17 + 1. + numExtB := s18. ^ 0 ]. - s9 := extB. - s10 := s9 << 8. - s11 := s10 + s2. - s7 := s11. + s9 := s2. + s10 := extB. + s11 := s10 << 8. + s12 := s11 + s9. + s7 := s12. extB := s7. - s16 := numExtB. - s17 := s16 + 1. - numExtB := s17. + s17 := numExtB. + s18 := s17 + 1. + numExtB := s18. ^ 0 ]. - s9 := extB. - s10 := s9 << 8. - s11 := s10 + s2. - s7 := s11. + s9 := s2. + s10 := extB. + s11 := s10 << 8. + s12 := s11 + s9. + s7 := s12. extB := s7. - s16 := numExtB. - s17 := s16 + 1. - numExtB := s17. + s17 := numExtB. + s18 := s17 + 1. + numExtB := s18. ^ 0 ] @@ -1206,8 +776,7 @@ SimpleDruidTestRTLCompiler >> gen_extPushFullClosureBytecode [ SimpleDruidTestRTLCompiler >> gen_extPushIntegerBytecode [ "AutoGenerated by Druid" - | s5 s8 s4 s2 currentBlock s9 s10 live s3 | - live := 0. + | s8 s4 s2 currentBlock s9 s10 s5 s3 | s2 := byte1. s3 := extB. s4 := s3 << 8. @@ -1217,7 +786,7 @@ SimpleDruidTestRTLCompiler >> gen_extPushIntegerBytecode [ s8 := s2 + s4. s9 := s8 << 3. s10 := s9 + 1. - self ssPushConstant: s10. + self genPushConstant: s10. ^ 0 ] @@ -1225,8 +794,8 @@ SimpleDruidTestRTLCompiler >> gen_extPushIntegerBytecode [ SimpleDruidTestRTLCompiler >> gen_extSendSuperBytecode [ "AutoGenerated by Druid" - | s6 s3 s16 s10 s8 s5 s2 s18 currentBlock s15 s4 s17 live s9 | - live := 0. + | s6 s3 s16 s10 s8 s5 s2 s18 currentBlock s15 t0 s4 s17 s11 s9 | + t0 := ClassReg. s2 := byte1. s3 := s2 >> 3. s4 := extA. @@ -1237,9 +806,7 @@ SimpleDruidTestRTLCompiler >> gen_extSendSuperBytecode [ s8 ifTrue: [ s10 := extB. s10 >= 64 ifTrue: [ - self ssFlushStack. self deoptimize. - deadCode := false. ^ 0 ]. s15 := s2 bitAnd: 7. s16 := extB. @@ -1247,11 +814,7 @@ SimpleDruidTestRTLCompiler >> gen_extSendSuperBytecode [ s18 := s15 + s17. extB := 0. numExtB := 0. - self marshallSendArguments: s18. - self - genMarshalledSend: s6 - numArgs: s18 - sendTable: superSendTrampolines. + self genSend: s6 numArgs: s18 sendTable: superSendTrampolines. ^ 0 ]. s15 := s2 bitAnd: 7. s16 := extB. @@ -1259,11 +822,234 @@ SimpleDruidTestRTLCompiler >> gen_extSendSuperBytecode [ s18 := s15 + s17. extB := 0. numExtB := 0. - self marshallSendArguments: s18. - self - genMarshalledSend: s6 - numArgs: s18 - sendTable: superSendTrampolines. + self genSend: s6 numArgs: s18 sendTable: superSendTrampolines. + ^ 0 +] + +{ #category : #generated } +SimpleDruidTestRTLCompiler >> gen_extStoreLiteralVariableBytecode [ + "AutoGenerated by Druid" + + | s80 t2 jump6 s40 t3 jump7 t4 jump8 s58 jump9 s85 s170 s2 jumpTrue s3 s4 s122 s5 s74 s6 s64 s10 s11 s12 jump1 s51 s67 jump2 jump3 b612 s153 s69 jump4 t0 currentBlock s54 jump5 t1 jumpNext s101 | + t0 := ClassReg. + t1 := SendNumArgsReg. + t2 := Extra0Reg. + t3 := Extra1Reg. + t4 := Extra2Reg. + self annotateBytecode: self Label. + s3 := byte1. + s4 := extA. + s5 := s4 << 8. + s6 := s3 + s5. + extA := 0. + self MoveMw: 0 << 3 r: SPReg R: ClassReg. + self genMoveConstant: methodObj R: t1. + s10 := LiteralStart. + s11 := s6 + s10. + s12 := s11 << 3. + self AddCq: s12 R: t1. + self MoveM64: 8 r: t1 R: t1. + self MoveM64: 0 r: t1 R: t2. + self AndCq: 16r3FFFF7 R: t2. + self CmpCq: 0 R: t2. + jump1 := self JumpNonZero: 0. + self MoveM64: 8 r: t1 R: t2. + b612 := self Label. + self MoveR: t0 R: t1. + self MoveR: t2 R: t3. + self AndCq: 7 R: t3. + self CmpCq: 0 R: t3. + jump2 := self JumpNonZero: 0. + self MoveM64: 0 r: t2 R: t3. + self AndCq: 16r3FFFF7 R: t3. + self CmpCq: 0 R: t3. + jump3 := self JumpNonZero: 0. + self MoveM64: 8 r: t2 R: t3. + self MoveR: t3 R: t2. + jump4 := self Jump: b612. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + jump3 jmpTarget: currentBlock. + self MoveR: t2 R: t3. + jump3 := self Jump: 0. + currentBlock := self Label. + jump1 jmpTarget: currentBlock. + self MoveR: t1 R: t3. + self MoveR: t0 R: t1. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + s40 := ValueIndex. + self MoveM64: 0 r: t3 R: t2. + self LogicalShiftRightCq: 23 R: t2. + self AndCq: 1 R: t2. + self CmpCq: 0 R: t2. + jump3 := self JumpZero: 0. + self deoptimize. + jump1 := self Jump: 0. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + self MoveR: t3 R: t2. + self AndCq: 7 R: t2. + self CmpCq: 0 R: t2. + jump3 := self JumpNonZero: 0. + s51 := objectMemory getMemoryMap getSpaceMaskToUse. + self MoveR: t3 R: t2. + self AndCq: s51 R: t2. + s54 := objectMemory getMemoryMap getOldSpaceMask. + self CmpCq: s54 R: t2. + jumpTrue := self JumpZero: 0. + self MoveCq: 0 R: t2. + jumpNext := self Jump: 0. + jumpTrue jmpTarget: self Label. + self MoveCq: 1 R: t2. + jumpNext jmpTarget: self Label. + self CmpCq: 1 R: t2. + jump2 := self JumpNonZero: 0. + s58 := s40. + self MoveR: t3 R: t2. + self MoveR: t1 R: t3. + self AndCq: 7 R: t3. + self CmpCq: 0 R: t3. + jump5 := self JumpNonZero: 0. + s64 := objectMemory getMemoryMap getSpaceMaskToUse. + self MoveR: t1 R: t3. + self AndCq: s64 R: t3. + s67 := objectMemory getMemoryMap getNewSpaceMask. + self CmpCq: s67 R: t3. + jump6 := self JumpNonZero: 0. + s69 := objectMemory getMemoryMap getNewSpaceStart. + self MoveR: t1 R: t3. + self CmpCq: s69 R: t3. + jumpTrue := self JumpAboveOrEqual: 0. + self MoveCq: 0 R: t3. + jumpNext := self Jump: 0. + jumpTrue jmpTarget: self Label. + self MoveCq: 1 R: t3. + jumpNext jmpTarget: self Label. + jump7 := self Jump: 0. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + s74 := 0. + self MoveCq: s74 R: t3. + currentBlock := self Label. + jump7 jmpTarget: currentBlock. + s80 := s58. + self CmpCq: 1 R: t3. + jump7 := self JumpNonZero: 0. + self MoveR: t1 R: t3. + s85 := s80. + self MoveM64: 0 r: t2 R: t1. + self LogicalShiftRightCq: 29 R: t1. + self AndCq: 1 R: t1. + self CmpCq: 0 R: t1. + jump6 := self JumpNonZero: 0. + self MoveR: t2 R: TempReg. + backEnd saveAndRestoreLinkRegAround: [ + self CallRT: ceStoreCheckTrampoline ]. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + self MoveCq: s85 R: t1. + jump6 := self Jump: 0. + currentBlock := self Label. + jump7 jmpTarget: currentBlock. + self MoveCq: s80 R: t3. + self MoveR: t1 R: t0. + jump7 := self Jump: 0. + currentBlock := self Label. + jump5 jmpTarget: currentBlock. + s101 := s58. + self MoveR: t2 R: t0. + self MoveCq: s101 R: t3. + self MoveR: t0 R: t2. + self MoveR: t1 R: t0. + currentBlock := self Label. + jump7 jmpTarget: currentBlock. + self MoveR: t3 R: t1. + self MoveR: t0 R: t3. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + self MoveR: t3 R: t0. + jump6 := self Jump: 0. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + jump2 jmpTarget: currentBlock. + s122 := s40. + self MoveR: t3 R: t2. + self MoveR: t1 R: t0. + self MoveCq: s122 R: t1. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + self MoveM64: 0 r: t2 R: t3. + self LogicalShiftRightCq: 29 R: t3. + self AndCq: 1 R: t3. + self CmpCq: 0 R: t3. + jump6 := self JumpZero: 0. + self MoveR: t0 R: t3. + jump2 := self Jump: 0. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + self TstCq: 7 R: t0. + jump6 := self JumpZero: 0. + self MoveR: t0 R: t3. + jump3 := self Jump: 0. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + self CmpCq: 16r20000000000 R: t2. + jump6 := self JumpBelow: 0. + self CmpCq: 16r20000000000 R: t0. + jump7 := self JumpLess: 0. + self MoveR: t0 R: t3. + jump5 := self Jump: 0. + currentBlock := self Label. + jump7 jmpTarget: currentBlock. + self genMoveConstant: objectMemory nilObject R: t3. + self CmpR: t3 R: t0. + jump7 := self JumpBelow: 0. + s153 := objectMemory trueObject. + self MoveR: t0 R: t3. + self CmpCq: s153 R: t3. + jumpTrue := self JumpBelowOrEqual: 0. + self MoveCq: 0 R: t3. + jumpNext := self Jump: 0. + jumpTrue jmpTarget: self Label. + self MoveCq: 1 R: t3. + jumpNext jmpTarget: self Label. + self CmpCq: 1 R: t3. + jump8 := self JumpNonZero: 0. + self MoveR: t0 R: t3. + jump9 := self Jump: 0. + currentBlock := self Label. + jump7 jmpTarget: currentBlock. + jump8 jmpTarget: currentBlock. + self MoveR: t2 R: t3. + self MoveR: t0 R: t4. + s170 := objectMemory getMemoryMap getNewSpaceStart. + self CmpCq: s170 R: t4. + jump8 := self JumpBelow: 0. + self MoveR: t3 R: TempReg. + backEnd saveAndRestoreLinkRegAround: [ + self CallRT: ceStoreCheckTrampoline ]. + self MoveR: t0 R: t3. + jump7 := self Jump: 0. + currentBlock := self Label. + jump8 jmpTarget: currentBlock. + self MoveR: t0 R: t3. + jump8 := self Jump: 0. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + self MoveR: t0 R: t3. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + jump3 jmpTarget: currentBlock. + jump5 jmpTarget: currentBlock. + jump9 jmpTarget: currentBlock. + jump7 jmpTarget: currentBlock. + jump8 jmpTarget: currentBlock. + self LogicalShiftLeftCq: 3 R: t1. + self AddR: t1 R: t2. + self MoveR: t3 M64: 8 r: t2. + currentBlock := self Label. + jump1 jmpTarget: currentBlock. ^ 0 ] @@ -1271,371 +1057,369 @@ SimpleDruidTestRTLCompiler >> gen_extSendSuperBytecode [ SimpleDruidTestRTLCompiler >> gen_extStoreReceiverVariableBytecode [ "AutoGenerated by Druid" - | t2 jump6 jump10 s18 t3 jump7 jump8 s83 s96 jump9 s44 s106 s2 jumpTrue s3 s72 s4 s35 s48 live s5 s6 s64 s110 s39 s9 s78 s50 s66 jump1 s13 jump2 s114 jump3 t0 jump4 s92 currentBlock t1 jump5 jumpNext s101 | - live := 0. + | jump6 t2 s102 jump7 t3 s57 s19 t4 s183 jump9 s30 s70 s2 jumpTrue s3 s4 s60 s135 s5 s49 s6 s62 s10 s9 s166 jump1 s13 s26 jump2 s52 jump3 t0 jump4 currentBlock s116 jump5 t1 jumpNext | + t0 := ClassReg. + t1 := SendNumArgsReg. + t2 := Extra0Reg. + t3 := Extra1Reg. + t4 := Extra2Reg. self annotateBytecode: self Label. s3 := byte1. s4 := extA. s5 := s4 << 8. s6 := s3 + s5. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). - (self ssValue: 0) copyToReg: t0. - self ensureReceiverResultRegContainsSelf. - t1 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t1). + self MoveMw: 0 << 3 r: SPReg R: ClassReg. + needsFrame ifTrue: + [self putSelfInReceiverResultReg].. self MoveR: ReceiverResultReg R: t1. s9 := ReceiverIndex. - t2 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t2). - t3 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t3). s6 <= s9 ifTrue: [ - | jump1 jump10 jumpNext jump9 jump6 jump3 jump8 jump5 jumpTrue jump2 jump7 jump4 | + | jump1 jumpNext jump9 jump6 jump3 jump8 jump5 jumpTrue jump2 jump7 jump4 | self MoveM64: 0 r: t1 R: t2. self AndCq: 16r3FFFFF R: t2. s13 := ClassMethodContextCompactIndex. - self MoveCq: s13 R: t3. - self CmpR: t3 R: t2. - jumpTrue := self JumpZero: 0. - self MoveCq: 0 R: t2. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t2. - jumpNext jmpTarget: self Label. - self MoveR: t2 R: t3. - self ssFlushStack. - self CmpCq: 1 R: t3. + self CmpCq: s13 R: t2. jump1 := self JumpNonZero: 0. self deoptimize. jump2 := self Jump: 0. - deadCode := false. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveM64: 0 r: t1 R: t3. - self ArithmeticShiftRightCq: 23 R: t3. - self AndCq: 1 R: t3. - self CmpCq: 0 R: t3. - jump1 := self JumpZero: 0. - self deoptimize. + self MoveR: t0 R: t2. + s19 := s6. + self MoveM64: 0 r: t1 R: t0. + self LogicalShiftRightCq: 23 R: t0. + self AndCq: 1 R: t0. + self CmpCq: 0 R: t0. + jump1 := self JumpNonZero: 0. + self MoveR: t1 R: t0. + s26 := s19. jump3 := self Jump: 0. - deadCode := false. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveR: t1 R: t3. - self AndCq: 7 R: t3. - self CmpCq: 0 R: t3. - jump1 := self JumpNonZero: 0. - s35 := objectMemory getMemoryMap getSpaceMaskToUse. - self MoveCq: s35 R: t3. - self MoveR: t1 R: t2. - self AndR: t3 R: t2. - s39 := objectMemory getMemoryMap getOldSpaceMask. - self CmpCq: s39 R: t2. + self deoptimize. + jump1 := self Jump: 0. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + self MoveR: t0 R: t1. + self AndCq: 7 R: t1. + self CmpCq: 0 R: t1. + jump3 := self JumpNonZero: 0. + s49 := objectMemory getMemoryMap getSpaceMaskToUse. + self MoveR: t0 R: t1. + self AndCq: s49 R: t1. + s52 := objectMemory getMemoryMap getOldSpaceMask. + self CmpCq: s52 R: t1. jump4 := self JumpNonZero: 0. - self MoveR: t0 R: t2. - self AndCq: 7 R: t2. - self CmpCq: 0 R: t2. + self MoveR: t2 R: t1. + self AndCq: 7 R: t1. + self CmpCq: 0 R: t1. jump5 := self JumpNonZero: 0. - s44 := objectMemory getMemoryMap getSpaceMaskToUse. - self MoveCq: s44 R: t2. - self MoveR: t0 R: t3. - self AndR: t2 R: t3. - s48 := objectMemory getMemoryMap getNewSpaceMask. - self CmpCq: s48 R: t3. + s57 := objectMemory getMemoryMap getSpaceMaskToUse. + self MoveR: t2 R: t1. + self AndCq: s57 R: t1. + s60 := objectMemory getMemoryMap getNewSpaceMask. + self CmpCq: s60 R: t1. jump6 := self JumpNonZero: 0. - s50 := objectMemory getMemoryMap getNewSpaceStart. - self MoveCq: s50 R: t3. - self MoveR: t0 R: t2. - self CmpR: t3 R: t2. + s62 := objectMemory getMemoryMap getNewSpaceStart. + self MoveR: t2 R: t1. + self CmpCq: s62 R: t1. jumpTrue := self JumpAboveOrEqual: 0. - self MoveCq: 0 R: t2. + self MoveCq: 0 R: t1. jumpNext := self Jump: 0. jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t2. + self MoveCq: 1 R: t1. jumpNext jmpTarget: self Label. - self CmpCq: 1 R: t2. + s70 := s26. + self CmpCq: 1 R: t1. jump7 := self JumpNonZero: 0. - self MoveM64: 0 r: t1 R: t2. - self ArithmeticShiftRightCq: 29 R: t2. - self AndCq: 1 R: t2. - self CmpCq: 0 R: t2. + self MoveR: t2 R: t1. + self MoveCq: s70 R: t2. + self MoveM64: 0 r: t0 R: t3. + self LogicalShiftRightCq: 29 R: t3. + self AndCq: 1 R: t3. + self CmpCq: 0 R: t3. jump8 := self JumpNonZero: 0. - self MoveR: t1 R: TempReg. + self MoveR: t0 R: TempReg. backEnd saveAndRestoreLinkRegAround: [ self CallRT: ceStoreCheckTrampoline ]. - self TstCq: 7 R: t0. - jump9 := self JumpNonZero: 0. - jump10 := self JumpZero: 0. + currentBlock := self Label. + jump8 jmpTarget: currentBlock. + self MoveR: t2 R: t3. + jump8 := self Jump: 0. + currentBlock := self Label. + jump7 jmpTarget: currentBlock. + self MoveR: t2 R: t1. + self MoveCq: s70 R: t3. + jump7 := self Jump: 0. currentBlock := self Label. jump6 jmpTarget: currentBlock. - s64 := 0. - s66 := s64. + self MoveR: t2 R: t3. + s102 := s26. + self MoveR: t3 R: t1. + self MoveCq: s102 R: t3. currentBlock := self Label. jump7 jmpTarget: currentBlock. + jump7 := self Jump: 0. currentBlock := self Label. - jump1 jmpTarget: currentBlock. - jump4 jmpTarget: currentBlock. jump5 jmpTarget: currentBlock. + self MoveR: t2 R: t3. + s116 := s26. + self MoveR: t3 R: t1. + self MoveCq: s116 R: t3. + currentBlock := self Label. + jump7 jmpTarget: currentBlock. + currentBlock := self Label. jump8 jmpTarget: currentBlock. - self TstCq: 7 R: t0. - jump8 := self JumpNonZero: 0. + jump8 := self Jump: 0. currentBlock := self Label. - jump10 jmpTarget: currentBlock. - self genMoveConstant: objectMemory nilObject R: t2. - self CmpR: t2 R: t0. - jump10 := self JumpBelow: 0. - s72 := objectMemory trueObject. - self MoveCq: s72 R: t2. + jump3 jmpTarget: currentBlock. + jump4 jmpTarget: currentBlock. + s135 := s26. self MoveR: t0 R: t3. - self CmpR: t2 R: t3. - jumpTrue := self JumpBelowOrEqual: 0. - self MoveCq: 0 R: t3. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t3. - jumpNext jmpTarget: self Label. - jump5 := self Jump: 0. + self MoveR: t2 R: t1. + self MoveR: t3 R: t0. + self MoveCq: s135 R: t3. currentBlock := self Label. - jump10 jmpTarget: currentBlock. - s78 := 0. - self MoveCq: s78 R: t3. + jump8 jmpTarget: currentBlock. + self MoveM64: 0 r: t0 R: t2. + self LogicalShiftRightCq: 29 R: t2. + self AndCq: 1 R: t2. + self CmpCq: 0 R: t2. + jump8 := self JumpZero: 0. + self MoveR: t1 R: t2. + jump4 := self Jump: 0. currentBlock := self Label. - jump5 jmpTarget: currentBlock. - self CmpCq: 1 R: t3. - jump5 := self JumpZero: 0. - s83 := objectMemory getMemoryMap getNewSpaceStart. - self CmpCq: s83 R: t0. - jump10 := self JumpBelow: 0. - self MoveM64: 0 r: t1 R: t3. - self ArithmeticShiftRightCq: 29 R: t3. - self AndCq: 1 R: t3. - self CmpCq: 0 R: t3. - jump4 := self JumpNonZero: 0. - self MoveR: t1 R: t3. - self AndCq: 7 R: t3. - self CmpCq: 0 R: t3. - jump1 := self JumpNonZero: 0. - s92 := objectMemory getMemoryMap getSpaceMaskToUse. - self MoveCq: s92 R: t3. + jump8 jmpTarget: currentBlock. + self TstCq: 7 R: t1. + jump8 := self JumpZero: 0. self MoveR: t1 R: t2. - self AndR: t3 R: t2. - s96 := objectMemory getMemoryMap getPermSpaceMask. - self MoveCq: s96 R: t3. - self CmpR: t3 R: t2. - jumpTrue := self JumpZero: 0. + jump3 := self Jump: 0. + currentBlock := self Label. + jump8 jmpTarget: currentBlock. + self CmpCq: 16r20000000000 R: t0. + jump8 := self JumpLess: 0. + self CmpCq: 16r20000000000 R: t1. + jump7 := self JumpLess: 0. + self MoveR: t1 R: t2. + jump5 := self Jump: 0. + currentBlock := self Label. + jump7 jmpTarget: currentBlock. + self genMoveConstant: objectMemory nilObject R: t2. + self CmpR: t2 R: t1. + jump7 := self JumpBelow: 0. + s166 := objectMemory trueObject. + self MoveR: t1 R: t2. + self CmpCq: s166 R: t2. + jumpTrue := self JumpBelowOrEqual: 0. self MoveCq: 0 R: t2. jumpNext := self Jump: 0. jumpTrue jmpTarget: self Label. self MoveCq: 1 R: t2. jumpNext jmpTarget: self Label. - self MoveR: t2 R: t3. - jump7 := self Jump: 0. - currentBlock := self Label. - jump1 jmpTarget: currentBlock. - s101 := 0. - self MoveCq: s101 R: t3. + self CmpCq: 1 R: t2. + jump6 := self JumpNonZero: 0. + self MoveR: t1 R: t2. + jump9 := self Jump: 0. currentBlock := self Label. jump7 jmpTarget: currentBlock. - self CmpCq: 1 R: t3. - jump7 := self JumpNonZero: 0. - s106 := objectMemory getMemoryMap getSpaceMaskToUse. - self MoveCq: s106 R: t3. + jump6 jmpTarget: currentBlock. self MoveR: t0 R: t2. - self AndR: t3 R: t2. - s110 := objectMemory getMemoryMap getPermSpaceMask. - self CmpCq: s110 R: t2. - jump1 := self JumpZero: 0. - self MoveR: t1 R: TempReg. + self MoveR: t1 R: t4. + s183 := objectMemory getMemoryMap getNewSpaceStart. + self CmpCq: s183 R: t4. + jump6 := self JumpBelow: 0. + self MoveR: t2 R: TempReg. backEnd saveAndRestoreLinkRegAround: [ self CallRT: ceStoreCheckTrampoline ]. + self MoveR: t1 R: t2. + jump7 := self Jump: 0. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + self MoveR: t1 R: t2. + jump6 := self Jump: 0. currentBlock := self Label. - jump9 jmpTarget: currentBlock. jump8 jmpTarget: currentBlock. - jump5 jmpTarget: currentBlock. - jump10 jmpTarget: currentBlock. + self MoveR: t1 R: t2. + currentBlock := self Label. jump4 jmpTarget: currentBlock. + jump3 jmpTarget: currentBlock. + jump5 jmpTarget: currentBlock. + jump9 jmpTarget: currentBlock. jump7 jmpTarget: currentBlock. - jump1 jmpTarget: currentBlock. - s114 := s6 << 3. - self MoveCq: s114 R: t2. - self AddR: t2 R: t1. - self MoveR: t0 M64: 8 r: t1. + jump6 jmpTarget: currentBlock. + self LogicalShiftLeftCq: 3 R: t3. + self AddR: t3 R: t0. + self MoveR: t2 M64: 8 r: t0. currentBlock := self Label. jump2 jmpTarget: currentBlock. - jump3 jmpTarget: currentBlock. + jump1 jmpTarget: currentBlock. extA := 0. ^ 0 ]. - s18 := 0. - self MoveCq: s18 R: t3. - self ssFlushStack. - self CmpCq: 1 R: t3. - jump3 := self JumpNonZero: 0. + self MoveR: t0 R: t2. + s30 := s6. + self MoveM64: 0 r: t1 R: t0. + self LogicalShiftRightCq: 23 R: t0. + self AndCq: 1 R: t0. + self CmpCq: 0 R: t0. + jump1 := self JumpZero: 0. self deoptimize. jump2 := self Jump: 0. - deadCode := false. - currentBlock := self Label. - jump3 jmpTarget: currentBlock. - self MoveM64: 0 r: t1 R: t3. - self ArithmeticShiftRightCq: 23 R: t3. - self AndCq: 1 R: t3. - self CmpCq: 0 R: t3. - jump3 := self JumpZero: 0. - self deoptimize. - jump1 := self Jump: 0. - deadCode := false. currentBlock := self Label. - jump3 jmpTarget: currentBlock. - self MoveR: t1 R: t3. - self AndCq: 7 R: t3. - self CmpCq: 0 R: t3. - jump3 := self JumpNonZero: 0. - s35 := objectMemory getMemoryMap getSpaceMaskToUse. - self MoveCq: s35 R: t3. - self MoveR: t1 R: t2. - self AndR: t3 R: t2. - s39 := objectMemory getMemoryMap getOldSpaceMask. - self CmpCq: s39 R: t2. + jump1 jmpTarget: currentBlock. + self MoveR: t1 R: t0. + s26 := s30. + self MoveR: t0 R: t1. + self AndCq: 7 R: t1. + self CmpCq: 0 R: t1. + jump1 := self JumpNonZero: 0. + s49 := objectMemory getMemoryMap getSpaceMaskToUse. + self MoveR: t0 R: t1. + self AndCq: s49 R: t1. + s52 := objectMemory getMemoryMap getOldSpaceMask. + self CmpCq: s52 R: t1. + jump6 := self JumpNonZero: 0. + self MoveR: t2 R: t1. + self AndCq: 7 R: t1. + self CmpCq: 0 R: t1. jump7 := self JumpNonZero: 0. - self MoveR: t0 R: t2. - self AndCq: 7 R: t2. - self CmpCq: 0 R: t2. - jump4 := self JumpNonZero: 0. - s44 := objectMemory getMemoryMap getSpaceMaskToUse. - self MoveCq: s44 R: t2. - self MoveR: t0 R: t3. - self AndR: t2 R: t3. - s48 := objectMemory getMemoryMap getNewSpaceMask. - self CmpCq: s48 R: t3. - jump10 := self JumpNonZero: 0. - s50 := objectMemory getMemoryMap getNewSpaceStart. - self MoveCq: s50 R: t3. - self MoveR: t0 R: t2. - self CmpR: t3 R: t2. + s57 := objectMemory getMemoryMap getSpaceMaskToUse. + self MoveR: t2 R: t1. + self AndCq: s57 R: t1. + s60 := objectMemory getMemoryMap getNewSpaceMask. + self CmpCq: s60 R: t1. + jump9 := self JumpNonZero: 0. + s62 := objectMemory getMemoryMap getNewSpaceStart. + self MoveR: t2 R: t1. + self CmpCq: s62 R: t1. jumpTrue := self JumpAboveOrEqual: 0. - self MoveCq: 0 R: t2. + self MoveCq: 0 R: t1. jumpNext := self Jump: 0. jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t2. + self MoveCq: 1 R: t1. jumpNext jmpTarget: self Label. - self CmpCq: 1 R: t2. + s70 := s26. + self CmpCq: 1 R: t1. jump5 := self JumpNonZero: 0. - self MoveM64: 0 r: t1 R: t2. - self ArithmeticShiftRightCq: 29 R: t2. - self AndCq: 1 R: t2. - self CmpCq: 0 R: t2. - jump8 := self JumpNonZero: 0. - self MoveR: t1 R: TempReg. + self MoveR: t2 R: t1. + self MoveCq: s70 R: t2. + self MoveM64: 0 r: t0 R: t3. + self LogicalShiftRightCq: 29 R: t3. + self AndCq: 1 R: t3. + self CmpCq: 0 R: t3. + jump3 := self JumpNonZero: 0. + self MoveR: t0 R: TempReg. backEnd saveAndRestoreLinkRegAround: [ self CallRT: ceStoreCheckTrampoline ]. - self TstCq: 7 R: t0. - jump9 := self JumpNonZero: 0. - jump6 := self JumpZero: 0. currentBlock := self Label. - jump10 jmpTarget: currentBlock. - s64 := 0. - s66 := s64. + jump3 jmpTarget: currentBlock. + self MoveR: t2 R: t3. + jump3 := self Jump: 0. currentBlock := self Label. jump5 jmpTarget: currentBlock. + self MoveR: t2 R: t1. + self MoveCq: s70 R: t3. + jump5 := self Jump: 0. + currentBlock := self Label. + jump9 jmpTarget: currentBlock. + self MoveR: t2 R: t3. + s102 := s26. + self MoveR: t3 R: t1. + self MoveCq: s102 R: t3. + currentBlock := self Label. + jump5 jmpTarget: currentBlock. + jump5 := self Jump: 0. currentBlock := self Label. - jump3 jmpTarget: currentBlock. jump7 jmpTarget: currentBlock. - jump4 jmpTarget: currentBlock. - jump8 jmpTarget: currentBlock. - self TstCq: 7 R: t0. - jump8 := self JumpNonZero: 0. + self MoveR: t2 R: t3. + s116 := s26. + self MoveR: t3 R: t1. + self MoveCq: s116 R: t3. + currentBlock := self Label. + jump5 jmpTarget: currentBlock. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + jump3 := self Jump: 0. currentBlock := self Label. + jump1 jmpTarget: currentBlock. jump6 jmpTarget: currentBlock. - self genMoveConstant: objectMemory nilObject R: t2. - self CmpR: t2 R: t0. - jump6 := self JumpBelow: 0. - s72 := objectMemory trueObject. - self MoveCq: s72 R: t2. + s135 := s26. self MoveR: t0 R: t3. - self CmpR: t2 R: t3. - jumpTrue := self JumpBelowOrEqual: 0. - self MoveCq: 0 R: t3. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t3. - jumpNext jmpTarget: self Label. - jump4 := self Jump: 0. + self MoveR: t2 R: t1. + self MoveR: t3 R: t0. + self MoveCq: s135 R: t3. currentBlock := self Label. - jump6 jmpTarget: currentBlock. - s78 := 0. - self MoveCq: s78 R: t3. + jump3 jmpTarget: currentBlock. + self MoveM64: 0 r: t0 R: t2. + self LogicalShiftRightCq: 29 R: t2. + self AndCq: 1 R: t2. + self CmpCq: 0 R: t2. + jump3 := self JumpZero: 0. + self MoveR: t1 R: t2. + jump6 := self Jump: 0. currentBlock := self Label. - jump4 jmpTarget: currentBlock. - self CmpCq: 1 R: t3. - jump4 := self JumpZero: 0. - s83 := objectMemory getMemoryMap getNewSpaceStart. - self CmpCq: s83 R: t0. - jump6 := self JumpBelow: 0. - self MoveM64: 0 r: t1 R: t3. - self ArithmeticShiftRightCq: 29 R: t3. - self AndCq: 1 R: t3. - self CmpCq: 0 R: t3. - jump7 := self JumpNonZero: 0. - self MoveR: t1 R: t3. - self AndCq: 7 R: t3. - self CmpCq: 0 R: t3. - jump3 := self JumpNonZero: 0. - s92 := objectMemory getMemoryMap getSpaceMaskToUse. - self MoveCq: s92 R: t3. + jump3 jmpTarget: currentBlock. + self TstCq: 7 R: t1. + jump3 := self JumpZero: 0. self MoveR: t1 R: t2. - self AndR: t3 R: t2. - s96 := objectMemory getMemoryMap getPermSpaceMask. - self MoveCq: s96 R: t3. - self CmpR: t3 R: t2. - jumpTrue := self JumpZero: 0. + jump1 := self Jump: 0. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + self CmpCq: 16r20000000000 R: t0. + jump3 := self JumpLess: 0. + self CmpCq: 16r20000000000 R: t1. + jump5 := self JumpLess: 0. + self MoveR: t1 R: t2. + jump7 := self Jump: 0. + currentBlock := self Label. + jump5 jmpTarget: currentBlock. + self genMoveConstant: objectMemory nilObject R: t2. + self CmpR: t2 R: t1. + jump5 := self JumpBelow: 0. + s166 := objectMemory trueObject. + self MoveR: t1 R: t2. + self CmpCq: s166 R: t2. + jumpTrue := self JumpBelowOrEqual: 0. self MoveCq: 0 R: t2. jumpNext := self Jump: 0. jumpTrue jmpTarget: self Label. self MoveCq: 1 R: t2. jumpNext jmpTarget: self Label. - self MoveR: t2 R: t3. - jump5 := self Jump: 0. - currentBlock := self Label. - jump3 jmpTarget: currentBlock. - s101 := 0. - self MoveCq: s101 R: t3. + self CmpCq: 1 R: t2. + jump9 := self JumpNonZero: 0. + self MoveR: t1 R: t2. + jump4 := self Jump: 0. currentBlock := self Label. jump5 jmpTarget: currentBlock. - self CmpCq: 1 R: t3. - jump5 := self JumpNonZero: 0. - s106 := objectMemory getMemoryMap getSpaceMaskToUse. - self MoveCq: s106 R: t3. + jump9 jmpTarget: currentBlock. self MoveR: t0 R: t2. - self AndR: t3 R: t2. - s110 := objectMemory getMemoryMap getPermSpaceMask. - self CmpCq: s110 R: t2. - jump3 := self JumpZero: 0. - self MoveR: t1 R: TempReg. + self MoveR: t1 R: t4. + s183 := objectMemory getMemoryMap getNewSpaceStart. + self CmpCq: s183 R: t4. + jump9 := self JumpBelow: 0. + self MoveR: t2 R: TempReg. backEnd saveAndRestoreLinkRegAround: [ self CallRT: ceStoreCheckTrampoline ]. + self MoveR: t1 R: t2. + jump5 := self Jump: 0. currentBlock := self Label. jump9 jmpTarget: currentBlock. - jump8 jmpTarget: currentBlock. - jump4 jmpTarget: currentBlock. + self MoveR: t1 R: t2. + jump9 := self Jump: 0. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + self MoveR: t1 R: t2. + currentBlock := self Label. jump6 jmpTarget: currentBlock. + jump1 jmpTarget: currentBlock. jump7 jmpTarget: currentBlock. + jump4 jmpTarget: currentBlock. jump5 jmpTarget: currentBlock. - jump3 jmpTarget: currentBlock. - s114 := s6 << 3. - self MoveCq: s114 R: t2. - self AddR: t2 R: t1. - self MoveR: t0 M64: 8 r: t1. + jump9 jmpTarget: currentBlock. + self LogicalShiftLeftCq: 3 R: t3. + self AddR: t3 R: t0. + self MoveR: t2 M64: 8 r: t0. currentBlock := self Label. jump2 jmpTarget: currentBlock. - jump1 jmpTarget: currentBlock. extA := 0. ^ 0 ] @@ -1644,36 +1428,28 @@ SimpleDruidTestRTLCompiler >> gen_extStoreReceiverVariableBytecode [ SimpleDruidTestRTLCompiler >> gen_extUnconditionalJump [ "AutoGenerated by Druid" - | s6 s3 s19 s28 s13 s10 t1 s8 s5 s2 jump1 currentBlock s27 t0 s4 live s11 s9 | - live := 0. + | s6 s4 s29 s31 s9 s2 s27 currentBlock t1 s19 s12 s7 jump1 s10 s5 s3 s28 s8 s26 t0 s18 | + t0 := ClassReg. + t1 := SendNumArgsReg. self annotateBytecode: self Label. s3 := byte1. s4 := extB. s5 := s4 << 8. s6 := s3 + s5. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). - t1 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t1). s6 < 0 ifTrue: [ | jump1 | s8 := numExtB. - s9 := 2. - s10 := s9 * s8. - s11 := s10. + s9 := s8 << 1. + s10 := s9. extB := 0. numExtB := 0. - s19 := s6 + s11. - self ssFlushStack. - s19 >= 0 ifTrue: [ - s27 := s6 + bytecodePC. - s28 := s27 + 2. - self Jump: (self ensureFixupAt: s28). - deadCode := true. + s18 := s6 + s10. + s18 >= 0 ifTrue: [ + s26 := s6. + s27 := bytecodePC. + s28 := s27 + s26. + s29 := s28 + 2. + self Jump: (self ensureFixupAt: s29). ^ 0 ]. self MoveR: SPReg R: t0. self MoveAw: coInterpreter stackLimitAddress R: t1. @@ -1682,22 +1458,23 @@ SimpleDruidTestRTLCompiler >> gen_extUnconditionalJump [ self CallRT: ceCheckForInterruptTrampoline. currentBlock := self Label. jump1 jmpTarget: currentBlock. - s27 := s6 + bytecodePC. - s28 := s27 + 2. - self Jump: (self ensureFixupAt: s28). - deadCode := true. + s26 := s6. + s27 := bytecodePC. + s28 := s27 + s26. + s29 := s28 + 2. + self Jump: (self ensureFixupAt: s29). ^ 0 ]. - s13 := 0. - s11 := s13. + s12 := 0. + s10 := s12. extB := 0. numExtB := 0. - s19 := s6 + s11. - self ssFlushStack. - s19 >= 0 ifTrue: [ - s27 := s6 + bytecodePC. - s28 := s27 + 2. - self Jump: (self ensureFixupAt: s28). - deadCode := true. + s18 := s6 + s10. + s18 >= 0 ifTrue: [ + s26 := s6. + s27 := bytecodePC. + s28 := s27 + s26. + s29 := s28 + 2. + self Jump: (self ensureFixupAt: s29). ^ 0 ]. self MoveR: SPReg R: t0. self MoveAw: coInterpreter stackLimitAddress R: t1. @@ -1706,10 +1483,11 @@ SimpleDruidTestRTLCompiler >> gen_extUnconditionalJump [ self CallRT: ceCheckForInterruptTrampoline. currentBlock := self Label. jump1 jmpTarget: currentBlock. - s27 := s6 + bytecodePC. - s28 := s27 + 2. - self Jump: (self ensureFixupAt: s28). - deadCode := true. + s26 := s6. + s27 := bytecodePC. + s28 := s27 + s26. + s29 := s28 + 2. + self Jump: (self ensureFixupAt: s29). ^ 0 ] @@ -1717,94 +1495,74 @@ SimpleDruidTestRTLCompiler >> gen_extUnconditionalJump [ SimpleDruidTestRTLCompiler >> gen_extendedPushBytecode [ "AutoGenerated by Druid" - | s6 s4 s29 s2 t1 currentBlock s20 s19 s58 live s5 s3 s28 s30 s21 t2 s8 t0 s57 | - live := 0. + | s6 s55 s4 s29 s2 s20 currentBlock t1 s19 s17 s5 s54 s3 s28 s30 s21 s13 s8 s26 t0 | + t0 := ClassReg. + t1 := SendNumArgsReg. s2 := byte1. s3 := s2 >> 6. s4 := s3 bitAnd: 3. s5 := s2 bitAnd: 63. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). - t1 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t1). s4 = 0 ifTrue: [ - self ensureReceiverResultRegContainsSelf. + needsFrame ifTrue: + [self putSelfInReceiverResultReg].. self MoveR: ReceiverResultReg R: t0. s8 := s5 << 3. - self MoveCq: s8 R: t1. - self AddR: t1 R: t0. - self ssPushBase: t0 offset: 8. + self AddCq: s8 R: t0. + self MoveM64: 8 r: t0 R: t0. + self PushR: t0. ^ 0 ]. s4 = 1 ifTrue: [ - (self simStackTempAt: s5) copyToReg: t1. - self ssPushRegister: t1. + self MoveMw: (self frameOffsetOfTemporary: s5) r: FPReg R: ClassReg. + self PushR: t0. ^ 0 ]. s4 = 2 ifTrue: [ - self genMoveConstant: methodObj R: t1. + self genMoveConstant: methodObj R: t0. s19 := LiteralStart. s20 := s5 + s19. s21 := s20 << 3. - self MoveCq: s21 R: t0. - self AddR: t0 R: t1. - self ssPushBase: t1 offset: 8. + self AddCq: s21 R: t0. + self MoveM64: 8 r: t0 R: t0. + self PushR: t0. ^ 0 ]. - t2 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t2). s4 = 3 ifTrue: [ - | jumpNext jumpTrue jump1 jump3 b323 jump4 jump2 | + | jump3 jump1 b318 jump4 jump2 | self genMoveConstant: methodObj R: t0. s28 := LiteralStart. s29 := s5 + s28. s30 := s29 << 3. - self MoveCq: s30 R: t1. - self AddR: t1 R: t0. + self AddCq: s30 R: t0. + self MoveM64: 8 r: t0 R: t0. + self MoveM64: 0 r: t0 R: t1. + self AndCq: 16r3FFFF7 R: t1. + self CmpCq: 0 R: t1. + jump1 := self JumpNonZero: 0. self MoveM64: 8 r: t0 R: t1. + b318 := self Label. + self MoveR: t1 R: t0. + self AndCq: 7 R: t0. + self CmpCq: 0 R: t0. + jump2 := self JumpNonZero: 0. self MoveM64: 0 r: t1 R: t0. self AndCq: 16r3FFFF7 R: t0. self CmpCq: 0 R: t0. - jump1 := self JumpNonZero: 0. + jump3 := self JumpNonZero: 0. self MoveM64: 8 r: t1 R: t0. - b323 := self Label. self MoveR: t0 R: t1. - self AndCq: 7 R: t1. - self CmpCq: 0 R: t1. - jump2 := self JumpNonZero: 0. - self MoveM64: 0 r: t0 R: t1. - self AndCq: 16r3FFFF7 R: t1. - self MoveR: t1 R: t2. - self CmpCq: 0 R: t2. - jumpTrue := self JumpZero: 0. - self MoveCq: 0 R: t2. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t2. - jumpNext jmpTarget: self Label. - self CmpCq: 0 R: t1. - jump3 := self JumpNonZero: 0. - self MoveM64: 8 r: t0 R: t2. - self MoveR: t2 R: t0. - jump4 := self Jump: b323. + jump4 := self Jump: b318. currentBlock := self Label. jump2 jmpTarget: currentBlock. jump3 jmpTarget: currentBlock. - self MoveR: t0 R: t2. + self MoveR: t1 R: t0. jump3 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveR: t1 R: t2. currentBlock := self Label. jump3 jmpTarget: currentBlock. - s57 := ValueIndex. - s58 := s57 << 3. - self MoveCq: s58 R: t0. - self AddR: t0 R: t2. - self ssPushBase: t2 offset: 8. + s54 := ValueIndex. + s55 := s54 << 3. + self AddCq: s55 R: t0. + self MoveM64: 8 r: t0 R: t0. + self PushR: t0. ^ 0 ]. ^ 0 ] @@ -1841,6 +1599,24 @@ SimpleDruidTestRTLCompiler >> gen_failingSuccess [ ^ CompletePrimitive ] +{ #category : #generated } +SimpleDruidTestRTLCompiler >> gen_fakePushConstantTrueBytecode [ + "AutoGenerated by Druid" + + | nextFixup s2 nextBytecode currentBlock | + nextFixup := self fixupAt: bytecodePC + 1. + nextFixup notAFixup ifTrue: [ + nextBytecode := objectMemory + fetchByte: bytecodePC + 1 + ofObject: methodObj. + nextBytecode = 92 ifTrue: [ + bytecodePC := bytecodePC + 1. + ^ self gen_pushConstantTrueBytecode_returnTopFromMethod_1 ] ]. + s2 := objectMemory trueObject. + self genPushConstant: s2. + ^ 0 +] + { #category : #generated } SimpleDruidTestRTLCompiler >> gen_ifZeroFailPrimitive [ "AutoGenerated by Druid" @@ -5293,9 +5069,9 @@ SimpleDruidTestRTLCompiler >> gen_primitiveIntegerDivideByConstant [ self DivR: SendNumArgsReg R: ClassReg - Quo: SendNumArgsReg - Rem: ClassReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. + Quo: ClassReg + Rem: SendNumArgsReg. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -7172,10 +6948,9 @@ SimpleDruidTestRTLCompiler >> gen_primitiveWithTwoArgs [ SimpleDruidTestRTLCompiler >> gen_pushConstantOneBytecode [ "AutoGenerated by Druid" - | live currentBlock s2 | - live := 0. + | currentBlock s2 | s2 := ConstOne. - self ssPushConstant: s2. + self genPushConstant: s2. ^ 0 ] @@ -7183,10 +6958,101 @@ SimpleDruidTestRTLCompiler >> gen_pushConstantOneBytecode [ SimpleDruidTestRTLCompiler >> gen_pushConstantTrueBytecode [ "AutoGenerated by Druid" - | live currentBlock s2 | - live := 0. + | currentBlock s2 | + s2 := objectMemory trueObject. + self genPushConstant: s2. + ^ 0 +] + +{ #category : #generated } +SimpleDruidTestRTLCompiler >> gen_pushConstantTrueBytecode_returnTopFromMethod [ + "AutoGenerated by Druid" + + | t0 currentBlock s2 | + t0 := ClassReg. + s2 := objectMemory trueObject. + self genPushConstant: s2. + self MoveMw: 0 r: SPReg R: ClassReg. + self PopN: 1. + self MoveR: t0 R: ReceiverResultReg. + self genUpArrowReturn. + ^ 0 +] + +{ #category : #generated } +SimpleDruidTestRTLCompiler >> gen_pushConstantTrueBytecode_returnTopFromMethod_1 [ + "AutoGenerated by Druid" + + | t0 currentBlock s2 | + t0 := ClassReg. + s2 := objectMemory trueObject. + self genPushConstant: s2. + self MoveMw: 0 r: SPReg R: ClassReg. + self PopN: 1. + self MoveR: t0 R: ReceiverResultReg. + self genUpArrowReturn. + ^ 0 +] + +{ #category : #generated } +SimpleDruidTestRTLCompiler >> gen_pushConstantTrueBytecode_shortConditionalJumpFalse [ + "AutoGenerated by Druid" + + | jump1 s10 s2 currentBlock s12 t0 s7 s4 jump2 s14 s9 | + t0 := ClassReg. + s2 := objectMemory trueObject. + self genPushConstant: s2. + self annotateBytecode: self Label. + self MoveMw: 0 r: SPReg R: ClassReg. + self PopN: 1. + s7 := objectMemory falseObject. + self CmpCq: s7 R: t0. + jump1 := self JumpNonZero: 0. + s9 := bytecodePC. + s10 := s9 + 2. + self Jump: (self ensureFixupAt: s10). + jump2 := self Jump: 0. + currentBlock := self Label. + jump1 jmpTarget: currentBlock. + s14 := objectMemory trueObject. + self CmpCq: s14 R: t0. + jump1 := self JumpZero: 0. + self MoveR: t0 R: TempReg. + self CallRT: ceSendMustBeBooleanTrampoline. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + jump1 jmpTarget: currentBlock. + ^ 0 +] + +{ #category : #generated } +SimpleDruidTestRTLCompiler >> gen_pushConstantTrueBytecode_shortConditionalJumpTrue [ + "AutoGenerated by Druid" + + | jump1 s10 s2 currentBlock s12 t0 s7 s4 jump2 s14 s9 | + t0 := ClassReg. s2 := objectMemory trueObject. - self ssPushConstant: s2. + self genPushConstant: s2. + self annotateBytecode: self Label. + self MoveMw: 0 r: SPReg R: ClassReg. + self PopN: 1. + s7 := objectMemory trueObject. + self CmpCq: s7 R: t0. + jump1 := self JumpNonZero: 0. + s9 := bytecodePC. + s10 := s9 + 2. + self Jump: (self ensureFixupAt: s10). + jump2 := self Jump: 0. + currentBlock := self Label. + jump1 jmpTarget: currentBlock. + s14 := objectMemory falseObject. + self CmpCq: s14 R: t0. + jump1 := self JumpZero: 0. + self MoveR: t0 R: TempReg. + self CallRT: ceSendMustBeBooleanTrampoline. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + jump1 jmpTarget: currentBlock. ^ 0 ] @@ -7194,10 +7060,9 @@ SimpleDruidTestRTLCompiler >> gen_pushConstantTrueBytecode [ SimpleDruidTestRTLCompiler >> gen_pushConstantZeroBytecode [ "AutoGenerated by Druid" - | live currentBlock s2 | - live := 0. + | currentBlock s2 | s2 := ConstZero. - self ssPushConstant: s2. + self genPushConstant: s2. ^ 0 ] @@ -7205,90 +7070,61 @@ SimpleDruidTestRTLCompiler >> gen_pushConstantZeroBytecode [ SimpleDruidTestRTLCompiler >> gen_pushLiteralConstantBytecode [ "AutoGenerated by Druid" - | s3 t0 s4 t1 currentBlock live s5 | - live := 0. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). + | t0 s4 currentBlock s5 s3 | + t0 := ClassReg. self genMoveConstant: methodObj R: t0. s3 := LiteralStart. s4 := s3 + 1. s5 := s4 << 3. - t1 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t1). - self MoveCq: s5 R: t1. - self AddR: t1 R: t0. - self ssPushBase: t0 offset: 8. + self AddCq: s5 R: t0. + self MoveM64: 8 r: t0 R: t0. + self PushR: t0. ^ 0 ] -{ #category : #generated } -SimpleDruidTestRTLCompiler >> gen_pushLiteralVariable16CasesBytecode [ - "AutoGenerated by Druid" - - | jump1 s31 s3 jumpNext t1 jump3 currentBlock t0 jump2 s32 s4 b233 jumpTrue live t2 jump4 | - live := 0. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). +{ #category : #generated } +SimpleDruidTestRTLCompiler >> gen_pushLiteralVariable16CasesBytecode [ + "AutoGenerated by Druid" + + | jump1 s3 s28 b232 t1 jump3 currentBlock t0 jump2 s4 s29 jump4 | + t0 := ClassReg. + t1 := SendNumArgsReg. self genMoveConstant: methodObj R: t0. s3 := LiteralStart. s4 := s3 << 3. - t1 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t1). - self MoveCq: s4 R: t1. - self AddR: t1 R: t0. + self AddCq: s4 R: t0. + self MoveM64: 8 r: t0 R: t0. + self MoveM64: 0 r: t0 R: t1. + self AndCq: 16r3FFFF7 R: t1. + self CmpCq: 0 R: t1. + jump1 := self JumpNonZero: 0. self MoveM64: 8 r: t0 R: t1. + b232 := self Label. + self MoveR: t1 R: t0. + self AndCq: 7 R: t0. + self CmpCq: 0 R: t0. + jump2 := self JumpNonZero: 0. self MoveM64: 0 r: t1 R: t0. self AndCq: 16r3FFFF7 R: t0. self CmpCq: 0 R: t0. - jump1 := self JumpNonZero: 0. + jump3 := self JumpNonZero: 0. self MoveM64: 8 r: t1 R: t0. - b233 := self Label. self MoveR: t0 R: t1. - self AndCq: 7 R: t1. - self CmpCq: 0 R: t1. - jump2 := self JumpNonZero: 0. - self MoveM64: 0 r: t0 R: t1. - self AndCq: 16r3FFFF7 R: t1. - t2 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t2). - self MoveR: t1 R: t2. - self CmpCq: 0 R: t2. - jumpTrue := self JumpZero: 0. - self MoveCq: 0 R: t2. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t2. - jumpNext jmpTarget: self Label. - self CmpCq: 0 R: t1. - jump3 := self JumpNonZero: 0. - self MoveM64: 8 r: t0 R: t2. - self MoveR: t2 R: t0. - jump4 := self Jump: b233. + jump4 := self Jump: b232. currentBlock := self Label. jump2 jmpTarget: currentBlock. jump3 jmpTarget: currentBlock. - self MoveR: t0 R: t2. + self MoveR: t1 R: t0. jump3 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self MoveR: t1 R: t2. currentBlock := self Label. jump3 jmpTarget: currentBlock. - s31 := ValueIndex. - s32 := s31 << 3. - self MoveCq: s32 R: t0. - self AddR: t0 R: t2. - self ssPushBase: t2 offset: 8. + s28 := ValueIndex. + s29 := s28 << 3. + self AddCq: s29 R: t0. + self MoveM64: 8 r: t0 R: t0. + self PushR: t0. ^ 0 ] @@ -7296,15 +7132,12 @@ SimpleDruidTestRTLCompiler >> gen_pushLiteralVariable16CasesBytecode [ SimpleDruidTestRTLCompiler >> gen_pushReceiverBytecode [ "AutoGenerated by Druid" - | live currentBlock t0 | - live := 0. - self ensureReceiverResultRegContainsSelf. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). + | currentBlock t0 | + t0 := ClassReg. + needsFrame ifTrue: + [self putSelfInReceiverResultReg].. self MoveR: ReceiverResultReg R: t0. - self ssPushRegister: t0. + self PushR: t0. ^ 0 ] @@ -7312,15 +7145,13 @@ SimpleDruidTestRTLCompiler >> gen_pushReceiverBytecode [ SimpleDruidTestRTLCompiler >> gen_pushReceiverVariableBytecode [ "AutoGenerated by Druid" - | live currentBlock t0 | - live := 0. - self ensureReceiverResultRegContainsSelf. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). + | currentBlock t0 | + t0 := ClassReg. + needsFrame ifTrue: + [self putSelfInReceiverResultReg].. self MoveR: ReceiverResultReg R: t0. - self ssPushBase: t0 offset: 16. + self MoveM64: 16 r: t0 R: t0. + self PushR: t0. ^ 0 ] @@ -7328,14 +7159,10 @@ SimpleDruidTestRTLCompiler >> gen_pushReceiverVariableBytecode [ SimpleDruidTestRTLCompiler >> gen_pushTemporaryVariableBytecode [ "AutoGenerated by Druid" - | live currentBlock t0 | - live := 0. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). - (self simStackTempAt: 0) copyToReg: t0. - self ssPushRegister: t0. + | currentBlock t0 | + t0 := ClassReg. + self MoveMw: (self frameOffsetOfTemporary: 2) r: FPReg R: ClassReg. + self PushR: t0. ^ 0 ] @@ -7343,8 +7170,7 @@ SimpleDruidTestRTLCompiler >> gen_pushTemporaryVariableBytecode [ SimpleDruidTestRTLCompiler >> gen_returnFalse [ "AutoGenerated by Druid" - | live currentBlock s2 | - live := 0. + | currentBlock s2 | s2 := objectMemory falseObject. self MoveCq: s2 R: ReceiverResultReg. self genUpArrowReturn. @@ -7355,10 +7181,10 @@ SimpleDruidTestRTLCompiler >> gen_returnFalse [ SimpleDruidTestRTLCompiler >> gen_returnNil [ "AutoGenerated by Druid" - | live currentBlock s2 | - live := 0. - s2 := objectMemory nilObject. - self MoveCq: s2 R: ReceiverResultReg. + | currentBlock t0 | + t0 := ClassReg. + self genMoveConstant: objectMemory nilObject R: t0. + self MoveR: t0 R: ReceiverResultReg. self genUpArrowReturn. ^ 0 ] @@ -7367,13 +7193,10 @@ SimpleDruidTestRTLCompiler >> gen_returnNil [ SimpleDruidTestRTLCompiler >> gen_returnReceiver [ "AutoGenerated by Druid" - | live currentBlock t0 | - live := 0. - self ensureReceiverResultRegContainsSelf. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). + | currentBlock t0 | + t0 := ClassReg. + needsFrame ifTrue: + [self putSelfInReceiverResultReg].. self MoveR: ReceiverResultReg R: t0. self MoveR: t0 R: ReceiverResultReg. self genUpArrowReturn. @@ -7384,14 +7207,10 @@ SimpleDruidTestRTLCompiler >> gen_returnReceiver [ SimpleDruidTestRTLCompiler >> gen_returnTopFromMethod [ "AutoGenerated by Druid" - | live currentBlock t0 | - live := 0. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). - (self ssValue: 0) copyToReg: t0. - self ssPop: 1. + | currentBlock t0 | + t0 := ClassReg. + self MoveMw: 0 << 3 r: SPReg R: ClassReg. + self PopN: 1. self MoveR: t0 R: ReceiverResultReg. self genUpArrowReturn. ^ 0 @@ -7401,8 +7220,7 @@ SimpleDruidTestRTLCompiler >> gen_returnTopFromMethod [ SimpleDruidTestRTLCompiler >> gen_returnTrue [ "AutoGenerated by Druid" - | live currentBlock s2 | - live := 0. + | currentBlock s2 | s2 := objectMemory trueObject. self MoveCq: s2 R: ReceiverResultReg. self genUpArrowReturn. @@ -7413,13 +7231,8 @@ SimpleDruidTestRTLCompiler >> gen_returnTrue [ SimpleDruidTestRTLCompiler >> gen_sendLiteralSelector0ArgsBytecode [ "AutoGenerated by Druid" - | live currentBlock | - live := 0. - self marshallSendArguments: 0. - self - genMarshalledSend: 1 - numArgs: 0 - sendTable: ordinarySendTrampolines. + | currentBlock | + self genSend: 1 numArgs: 0 sendTable: ordinarySendTrampolines. ^ 0 ] @@ -7427,25 +7240,18 @@ SimpleDruidTestRTLCompiler >> gen_sendLiteralSelector0ArgsBytecode [ SimpleDruidTestRTLCompiler >> gen_shortConditionalJumpFalse [ "AutoGenerated by Druid" - | jump1 s8 s5 s2 currentBlock s12 t0 jump2 live s9 | - live := 0. + | jump1 s10 s8 s5 s2 currentBlock s12 t0 jump2 s7 | + t0 := ClassReg. self annotateBytecode: self Label. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). - (self ssValue: 0) copyToReg: t0. - self ssPop: 1. + self MoveMw: 0 << 3 r: SPReg R: ClassReg. + self PopN: 1. s5 := objectMemory falseObject. - self ssFlushStack. self CmpCq: s5 R: t0. jump1 := self JumpNonZero: 0. - s8 := bytecodePC. - s9 := s8 + 2. - self Jump: (self ensureFixupAt: s9). - deadCode := true. + s7 := bytecodePC. + s8 := s7 + 2. + self Jump: (self ensureFixupAt: s8). jump2 := self Jump: 0. - deadCode := false. currentBlock := self Label. jump1 jmpTarget: currentBlock. s12 := objectMemory trueObject. @@ -7463,25 +7269,18 @@ SimpleDruidTestRTLCompiler >> gen_shortConditionalJumpFalse [ SimpleDruidTestRTLCompiler >> gen_shortConditionalJumpTrue [ "AutoGenerated by Druid" - | jump1 s8 s5 s2 currentBlock s12 t0 jump2 live s9 | - live := 0. + | jump1 s10 s8 s5 s2 currentBlock s12 t0 jump2 s7 | + t0 := ClassReg. self annotateBytecode: self Label. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). - (self ssValue: 0) copyToReg: t0. - self ssPop: 1. + self MoveMw: 0 << 3 r: SPReg R: ClassReg. + self PopN: 1. s5 := objectMemory trueObject. - self ssFlushStack. self CmpCq: s5 R: t0. jump1 := self JumpNonZero: 0. - s8 := bytecodePC. - s9 := s8 + 2. - self Jump: (self ensureFixupAt: s9). - deadCode := true. + s7 := bytecodePC. + s8 := s7 + 2. + self Jump: (self ensureFixupAt: s8). jump2 := self Jump: 0. - deadCode := false. currentBlock := self Label. jump1 jmpTarget: currentBlock. s12 := objectMemory falseObject. @@ -7499,13 +7298,10 @@ SimpleDruidTestRTLCompiler >> gen_shortConditionalJumpTrue [ SimpleDruidTestRTLCompiler >> gen_shortUnconditionalJump [ "AutoGenerated by Druid" - | s5 s2 currentBlock live s3 | - live := 0. + | s3 s5 currentBlock s2 | s2 := bytecodePC. s3 := s2 + 2. - self ssFlushStack. self Jump: (self ensureFixupAt: s3). - deadCode := true. ^ 0 ] @@ -7513,176 +7309,165 @@ SimpleDruidTestRTLCompiler >> gen_shortUnconditionalJump [ SimpleDruidTestRTLCompiler >> gen_storeAndPopReceiverVariableBytecode [ "AutoGenerated by Druid" - | jump5 s16 s64 s29 s77 s31 t3 jump3 s53 jump8 s2 s20 currentBlock t1 jump1 s51 jumpNext s25 s73 s82 s47 jump6 live jump4 s87 jumpTrue s45 jump9 jump2 t2 s59 s91 jump7 t0 | - live := 0. + | jump5 s24 s16 jump3 t3 s29 s125 jump8 jump1 t1 s2 currentBlock s19 s27 jumpNext jump6 jump4 jumpTrue jump2 t2 s111 jump7 t0 | + t0 := ClassReg. + t1 := SendNumArgsReg. + t2 := Extra0Reg. + t3 := Extra1Reg. self annotateBytecode: self Label. - self ensureReceiverResultRegContainsSelf. - t0 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t0). + needsFrame ifTrue: + [self putSelfInReceiverResultReg].. self MoveR: ReceiverResultReg R: t0. - t1 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t1). - (self ssValue: 0) copyToReg: t1. - t2 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t2). + self MoveMw: 0 << 3 r: SPReg R: SendNumArgsReg. self MoveM64: 0 r: t0 R: t2. - self ArithmeticShiftRightCq: 23 R: t2. + self LogicalShiftRightCq: 23 R: t2. self AndCq: 1 R: t2. - self ssFlushStack. self CmpCq: 0 R: t2. jump1 := self JumpZero: 0. self deoptimize. jump2 := self Jump: 0. - deadCode := false. currentBlock := self Label. jump1 jmpTarget: currentBlock. - self ssPop: 1. + self PopN: 1. self MoveR: t0 R: t2. self AndCq: 7 R: t2. self CmpCq: 0 R: t2. jump1 := self JumpNonZero: 0. s16 := objectMemory getMemoryMap getSpaceMaskToUse. - self MoveCq: s16 R: t2. - t3 := self - allocateRegNotConflictingWith: live - ifNone: [ ^ self unknownBytecode ]. - live := live bitOr: (self registerMaskFor: t3). - self MoveR: t0 R: t3. - self AndR: t2 R: t3. - s20 := objectMemory getMemoryMap getOldSpaceMask. - self CmpCq: s20 R: t3. + self MoveR: t0 R: t2. + self AndCq: s16 R: t2. + s19 := objectMemory getMemoryMap getOldSpaceMask. + self CmpCq: s19 R: t2. jump3 := self JumpNonZero: 0. - self MoveR: t1 R: t3. - self AndCq: 7 R: t3. - self CmpCq: 0 R: t3. + self MoveR: t1 R: t2. + self AndCq: 7 R: t2. + self CmpCq: 0 R: t2. jump4 := self JumpNonZero: 0. - s25 := objectMemory getMemoryMap getSpaceMaskToUse. - self MoveCq: s25 R: t3. + s24 := objectMemory getMemoryMap getSpaceMaskToUse. self MoveR: t1 R: t2. - self AndR: t3 R: t2. - s29 := objectMemory getMemoryMap getNewSpaceMask. - self CmpCq: s29 R: t2. + self AndCq: s24 R: t2. + s27 := objectMemory getMemoryMap getNewSpaceMask. + self CmpCq: s27 R: t2. jump5 := self JumpNonZero: 0. - s31 := objectMemory getMemoryMap getNewSpaceStart. - self MoveCq: s31 R: t2. - self MoveR: t1 R: t3. - self CmpR: t2 R: t3. + s29 := objectMemory getMemoryMap getNewSpaceStart. + self MoveR: t1 R: t2. + self CmpCq: s29 R: t2. jumpTrue := self JumpAboveOrEqual: 0. - self MoveCq: 0 R: t3. + self MoveCq: 0 R: t2. jumpNext := self Jump: 0. jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t3. + self MoveCq: 1 R: t2. jumpNext jmpTarget: self Label. - self CmpCq: 1 R: t3. + self CmpCq: 1 R: t2. jump6 := self JumpNonZero: 0. - self MoveM64: 0 r: t0 R: t3. - self ArithmeticShiftRightCq: 29 R: t3. - self AndCq: 1 R: t3. - self CmpCq: 0 R: t3. + self MoveR: t1 R: t2. + self MoveM64: 0 r: t0 R: t1. + self LogicalShiftRightCq: 29 R: t1. + self AndCq: 1 R: t1. + self CmpCq: 0 R: t1. jump7 := self JumpNonZero: 0. self MoveR: t0 R: TempReg. backEnd saveAndRestoreLinkRegAround: [ self CallRT: ceStoreCheckTrampoline ]. - self TstCq: 7 R: t1. - jump8 := self JumpNonZero: 0. - jump9 := self JumpZero: 0. + currentBlock := self Label. + jump7 jmpTarget: currentBlock. + self MoveR: t0 R: t1. + jump7 := self Jump: 0. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + self MoveR: t1 R: t2. + jump6 := self Jump: 0. currentBlock := self Label. jump5 jmpTarget: currentBlock. - s45 := 0. - s47 := s45. + self MoveR: t1 R: t2. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + jump6 := self Jump: 0. + currentBlock := self Label. + jump4 jmpTarget: currentBlock. + self MoveR: t1 R: t2. currentBlock := self Label. jump6 jmpTarget: currentBlock. + self MoveR: t0 R: t1. + currentBlock := self Label. + jump7 jmpTarget: currentBlock. + self MoveR: t2 R: t0. + jump7 := self Jump: 0. currentBlock := self Label. jump1 jmpTarget: currentBlock. jump3 jmpTarget: currentBlock. - jump4 jmpTarget: currentBlock. + self MoveR: t0 R: t2. + self MoveR: t1 R: t0. + self MoveR: t2 R: t1. + currentBlock := self Label. jump7 jmpTarget: currentBlock. - self TstCq: 7 R: t1. - jump7 := self JumpNonZero: 0. + self MoveM64: 0 r: t1 R: t2. + self LogicalShiftRightCq: 29 R: t2. + self AndCq: 1 R: t2. + self CmpCq: 0 R: t2. + jump7 := self JumpZero: 0. + self MoveR: t0 R: t2. + jump3 := self Jump: 0. currentBlock := self Label. - jump9 jmpTarget: currentBlock. - s51 := objectMemory nilObject. - self CmpCq: s51 R: t1. - jump9 := self JumpBelow: 0. - s53 := objectMemory trueObject. - self MoveCq: s53 R: t3. - self MoveR: t1 R: t2. - self CmpR: t3 R: t2. + jump7 jmpTarget: currentBlock. + self TstCq: 7 R: t0. + jump7 := self JumpZero: 0. + self MoveR: t0 R: t2. + jump1 := self Jump: 0. + currentBlock := self Label. + jump7 jmpTarget: currentBlock. + self CmpCq: 16r20000000000 R: t1. + jump7 := self JumpLess: 0. + self CmpCq: 16r20000000000 R: t0. + jump6 := self JumpLess: 0. + self MoveR: t0 R: t2. + jump4 := self Jump: 0. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + self genMoveConstant: objectMemory nilObject R: t2. + self CmpR: t2 R: t0. + jump6 := self JumpBelow: 0. + s111 := objectMemory trueObject. + self MoveR: t0 R: t2. + self CmpCq: s111 R: t2. jumpTrue := self JumpBelowOrEqual: 0. self MoveCq: 0 R: t2. jumpNext := self Jump: 0. jumpTrue jmpTarget: self Label. self MoveCq: 1 R: t2. jumpNext jmpTarget: self Label. - jump4 := self Jump: 0. - currentBlock := self Label. - jump9 jmpTarget: currentBlock. - s59 := 0. - self MoveCq: s59 R: t2. - currentBlock := self Label. - jump4 jmpTarget: currentBlock. self CmpCq: 1 R: t2. - jump4 := self JumpZero: 0. - s64 := objectMemory getMemoryMap getNewSpaceStart. - self CmpCq: s64 R: t1. - jump9 := self JumpBelow: 0. - self MoveM64: 0 r: t0 R: t2. - self ArithmeticShiftRightCq: 29 R: t2. - self AndCq: 1 R: t2. - self CmpCq: 0 R: t2. - jump3 := self JumpNonZero: 0. + jump5 := self JumpNonZero: 0. self MoveR: t0 R: t2. - self AndCq: 7 R: t2. - self CmpCq: 0 R: t2. - jump1 := self JumpNonZero: 0. - s73 := objectMemory getMemoryMap getSpaceMaskToUse. - self MoveCq: s73 R: t2. - self MoveR: t0 R: t3. - self AndR: t2 R: t3. - s77 := objectMemory getMemoryMap getPermSpaceMask. - self MoveCq: s77 R: t2. - self CmpR: t2 R: t3. - jumpTrue := self JumpZero: 0. - self MoveCq: 0 R: t3. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: t3. - jumpNext jmpTarget: self Label. - self MoveR: t3 R: t2. - jump6 := self Jump: 0. - currentBlock := self Label. - jump1 jmpTarget: currentBlock. - s82 := 0. - self MoveCq: s82 R: t2. + jump8 := self Jump: 0. currentBlock := self Label. jump6 jmpTarget: currentBlock. - self CmpCq: 1 R: t2. - jump6 := self JumpNonZero: 0. - s87 := objectMemory getMemoryMap getSpaceMaskToUse. - self MoveCq: s87 R: t2. - self MoveR: t1 R: t3. - self AndR: t2 R: t3. - s91 := objectMemory getMemoryMap getPermSpaceMask. - self CmpCq: s91 R: t3. - jump1 := self JumpZero: 0. - self MoveR: t0 R: TempReg. + jump5 jmpTarget: currentBlock. + self MoveR: t1 R: t2. + self MoveR: t0 R: t3. + s125 := objectMemory getMemoryMap getNewSpaceStart. + self CmpCq: s125 R: t3. + jump5 := self JumpBelow: 0. + self MoveR: t2 R: TempReg. backEnd saveAndRestoreLinkRegAround: [ self CallRT: ceStoreCheckTrampoline ]. + self MoveR: t0 R: t2. + jump6 := self Jump: 0. + currentBlock := self Label. + jump5 jmpTarget: currentBlock. + self MoveR: t0 R: t2. + jump5 := self Jump: 0. currentBlock := self Label. - jump8 jmpTarget: currentBlock. jump7 jmpTarget: currentBlock. - jump4 jmpTarget: currentBlock. - jump9 jmpTarget: currentBlock. + self MoveR: t0 R: t2. + currentBlock := self Label. jump3 jmpTarget: currentBlock. - jump6 jmpTarget: currentBlock. jump1 jmpTarget: currentBlock. - self MoveR: t1 M64: 8 r: t0. + jump4 jmpTarget: currentBlock. + jump8 jmpTarget: currentBlock. + jump6 jmpTarget: currentBlock. + jump5 jmpTarget: currentBlock. + self MoveR: t2 M64: 8 r: t1. currentBlock := self Label. jump2 jmpTarget: currentBlock. ^ 0 @@ -7698,11 +7483,15 @@ SimpleDruidTestRTLCompiler >> hasAnnotatedAbstractInstructions: annotation [ ^ false ] -{ #category : #'trait candidates' } -SimpleDruidTestRTLCompiler >> initialize [ +{ #category : #accessing } +SimpleDruidTestRTLCompiler >> methodOrBlockNumTemps [ + ^ methodOrBlockNumTemps +] + +{ #category : #testing } +SimpleDruidTestRTLCompiler >> methodOrBlockNumTemps: anInteger [ - super initialize. - deadCode := false + methodOrBlockNumTemps := anInteger ] { #category : #generated } From aa1e7f2f11d933f14c382f37a2bf1507a3f0f8a1 Mon Sep 17 00:00:00 2001 From: palumbon Date: Wed, 25 Sep 2024 18:05:20 +0200 Subject: [PATCH 11/20] Fix SimpleDruid generation: genLoadArg:into: -> genLoadArgAtDepth:into: --- Druid/DRCogitSimpleStackPrimitiveCodeGenerator.class.st | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Druid/DRCogitSimpleStackPrimitiveCodeGenerator.class.st b/Druid/DRCogitSimpleStackPrimitiveCodeGenerator.class.st index f4add18d..acf37dc4 100644 --- a/Druid/DRCogitSimpleStackPrimitiveCodeGenerator.class.st +++ b/Druid/DRCogitSimpleStackPrimitiveCodeGenerator.class.st @@ -10,7 +10,7 @@ DRCogitSimpleStackPrimitiveCodeGenerator >> visitLoadArgument: aDRLoadArgument [ generatorMethodBuilder addStatement: (RBMessageNode receiver: RBVariableNode selfNode - selector: #genLoadArg:into: + selector: #genLoadArgAtDepth:into: arguments: { (RBLiteralValueNode value: aDRLoadArgument argNum). (RBVariableNode named: aDRLoadArgument result name) }) From b990f4c66af3bcbf7dbf1b8e545efae7927116be Mon Sep 17 00:00:00 2001 From: palumbon Date: Wed, 2 Oct 2024 15:18:02 +0200 Subject: [PATCH 12/20] Fix genLoadArg index with slots for spilling --- Druid/DRCogitSimpleStackPrimitiveCodeGenerator.class.st | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Druid/DRCogitSimpleStackPrimitiveCodeGenerator.class.st b/Druid/DRCogitSimpleStackPrimitiveCodeGenerator.class.st index acf37dc4..381b5ee0 100644 --- a/Druid/DRCogitSimpleStackPrimitiveCodeGenerator.class.st +++ b/Druid/DRCogitSimpleStackPrimitiveCodeGenerator.class.st @@ -6,12 +6,13 @@ Class { { #category : #visiting } DRCogitSimpleStackPrimitiveCodeGenerator >> visitLoadArgument: aDRLoadArgument [ - "cogit genLoadArgAtDepth: 0 into: Arg0Reg." + "cogit genLoadArg: i spilled: n into: Reg." - generatorMethodBuilder addStatement: (RBMessageNode + self generatorMethodBuilder addStatement: (RBMessageNode receiver: RBVariableNode selfNode - selector: #genLoadArgAtDepth:into: + selector: #genLoadArg:spilled:into: arguments: { (RBLiteralValueNode value: aDRLoadArgument argNum). + (RBLiteralValueNode value: aDRLoadArgument controlFlowGraph numberOfSpillSlots ). (RBVariableNode named: aDRLoadArgument result name) }) ] From e0ff3f24fb050f4319a47c2c953a44fb0a47a86a Mon Sep 17 00:00:00 2001 From: palumbon Date: Wed, 2 Oct 2024 15:19:00 +0200 Subject: [PATCH 13/20] Running PrimitiveCompilationTests for SimpleDruid --- ...roductionPrimitiveCompilationTest.class.st | 49 +- Druid-Tests/DruidTestRTLCompiler.class.st | 360 +++--- .../SimpleDruidTestRTLCompiler.class.st | 1105 ++++++++--------- 3 files changed, 683 insertions(+), 831 deletions(-) diff --git a/Druid-Tests/DRProductionPrimitiveCompilationTest.class.st b/Druid-Tests/DRProductionPrimitiveCompilationTest.class.st index 90f1c10f..70ba7dec 100644 --- a/Druid-Tests/DRProductionPrimitiveCompilationTest.class.st +++ b/Druid-Tests/DRProductionPrimitiveCompilationTest.class.st @@ -68,8 +68,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAsFloat [ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAt [ | class array | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveAt. @@ -90,8 +88,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAt [ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtByteArrayPadding1 [ | array | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveAt. @@ -111,8 +107,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtByteArrayPadding1 DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtByteArrayPadding5 [ | array | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveAt. @@ -132,8 +126,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtByteArrayPadding5 DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtByteArrayPadding6 [ | array index | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveAt. @@ -154,8 +146,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtByteArrayPadding6 DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtByteArrayPadding7 [ | array | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveAt. @@ -175,8 +165,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtByteArrayPadding7 DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtContext [ | context | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveAt. @@ -194,8 +182,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtContext [ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtFaillingWithNegativeIndex [ | class array | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveAt. @@ -213,8 +199,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtFaillingWithNegati DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtFaillingWithOverflowIndex [ | class array | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveAt. @@ -232,8 +216,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtFaillingWithOverfl DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtFaillingWithZeroIndex [ | class array | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveAt. @@ -250,8 +232,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtFaillingWithZeroIn { #category : #'tests-object-access' } DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtIsNotCompletePrimitive [ - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitiveGenerator: #primitiveAt @@ -266,8 +246,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtIsNotCompletePrimi DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtManyElements [ | class array | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveAt. @@ -289,8 +267,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtManyElements [ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtMethod [ | class method | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveAt. @@ -311,7 +287,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtOnNonArray [ | ephemeron | self skip. "FIXME" - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveAt. @@ -328,9 +303,7 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtOnNonArray [ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveAtPut [ | class array | - self skip. "FIXME" - - self timeLimit: (Duration minutes: 2). + self timeLimit: (Duration minutes: 5). cogit ceStoreCheckTrampoline: fakeTrampoline. self compileDruidPrimitive: #primitiveAtPut. @@ -791,8 +764,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveSizeWeakArray [ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInitializesArray [ | class | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveNewWithArg. @@ -816,8 +787,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInitialize DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInitializesByteArray [ | class | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveNewWithArg. @@ -841,8 +810,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInitialize DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInitializesInteger16Array [ | class | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveNewWithArg. @@ -866,8 +833,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInitialize DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInitializesInteger32Array [ | class | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveNewWithArg. @@ -891,8 +856,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInitialize DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInitializesInteger64Array [ | class | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveNewWithArg. @@ -916,8 +879,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInitialize DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInstantiatesArray [ | class | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveNewWithArg. @@ -939,8 +900,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInstantiat DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInstantiatesByteArray [ | class | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveNewWithArg. @@ -962,8 +921,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInstantiat DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInstantiatesInteger16Array [ | class | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveNewWithArg. @@ -985,8 +942,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInstantiat DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInstantiatesInteger32Array [ | class | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveNewWithArg. @@ -1008,8 +963,6 @@ DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInstantiat DRProductionPrimitiveCompilationTest >> testCompilePrimitiveWithArgNewInstantiatesInteger64Array [ | class | - (cogit isKindOf: SimpleDruidTestRTLCompiler) ifTrue: [ ^ self skip ]. - self timeLimit: (Duration minutes: 2). self compileDruidPrimitive: #primitiveNewWithArg. diff --git a/Druid-Tests/DruidTestRTLCompiler.class.st b/Druid-Tests/DruidTestRTLCompiler.class.st index b5482bbd..b059fa61 100644 --- a/Druid-Tests/DruidTestRTLCompiler.class.st +++ b/Druid-Tests/DruidTestRTLCompiler.class.st @@ -5918,12 +5918,13 @@ DruidTestRTLCompiler >> gen_primitiveAt [ currentBlock := self Label. jump6 jmpTarget: currentBlock. s73 := 0. - self MoveCq: s73 R: Extra2Reg. + self MoveCq: s73 R: SendNumArgsReg. jump6 := self Jump: 0. currentBlock := self Label. jump9 jmpTarget: currentBlock. self CmpCq: 2 R: Extra1Reg. jump9 := self JumpAboveOrEqual: 0. + self MoveR: Extra2Reg R: SendNumArgsReg. self MoveR: Extra2Reg R: ClassReg. jump7 := self Jump: 0. currentBlock := self Label. @@ -5973,8 +5974,8 @@ DruidTestRTLCompiler >> gen_primitiveAt [ self MoveM64: 24 r: ClassReg R: Extra0Reg. self ArithmeticShiftRightCq: 3 R: Extra0Reg. self AndCq: 16rFFFF R: Extra0Reg. + self MoveR: Extra0Reg R: SendNumArgsReg. self MoveR: Extra2Reg R: ClassReg. - self MoveR: Extra0Reg R: Extra2Reg. currentBlock := self Label. jump6 jmpTarget: currentBlock. jump7 jmpTarget: currentBlock. @@ -5988,7 +5989,7 @@ DruidTestRTLCompiler >> gen_primitiveAt [ jump6 := self JumpZero: 0. currentBlock := self Label. jump7 jmpTarget: currentBlock. - self SubR: Extra2Reg R: ClassReg. + self SubR: SendNumArgsReg R: ClassReg. self CmpCq: 24 R: Extra1Reg. jump7 := self JumpAboveOrEqual: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. @@ -5998,7 +5999,7 @@ DruidTestRTLCompiler >> gen_primitiveAt [ self CmpR: ClassReg R: Extra3Reg. jump4 := self JumpAbove: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. - self AddR: Extra2Reg R: Extra3Reg. + self AddR: SendNumArgsReg R: Extra3Reg. self MoveR: Extra3Reg Mw: 8 r: SPReg. self CmpCq: 5 R: Extra1Reg. jump9 := self JumpAbove: 0. @@ -6097,7 +6098,7 @@ DruidTestRTLCompiler >> gen_primitiveAt [ DruidTestRTLCompiler >> gen_primitiveAtPut [ "AutoGenerated by Druid" - | s131 jump5 s153 jump10 jump17 jump3 jump15 s121 jump8 jump1 currentBlock jump13 jumpNext s60 jump6 jump11 jump4 s80 jumpTrue s126 jump9 jump2 jump16 s118 jump14 s52 jump7 s155 jump12 s129 | + | s131 jump5 jump17 jump10 s94 jump3 jump15 jump8 jump1 s134 currentBlock jump13 s139 jump6 jumpNext jump18 jump11 jump4 s168 jumpTrue jump16 jump9 jump2 s144 s166 s59 jump14 jump7 s142 s74 jump12 | self SubCq: 24 R: SPReg. self MoveR: ReceiverResultReg R: Extra3Reg. self MoveR: Extra3Reg Mw: 0 r: SPReg. @@ -6113,6 +6114,11 @@ DruidTestRTLCompiler >> gen_primitiveAtPut [ self AndCq: 1 R: Extra1Reg. self CmpCq: 0 R: Extra1Reg. jump2 := self JumpZero: 0. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveM64: 0 r: Extra3Reg R: Extra1Reg. + self AndCq: 16r3FFFF7 R: Extra1Reg. + self CmpCq: 0 R: Extra1Reg. + jump3 := self JumpZero: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. self ArithmeticShiftRightCq: 3 R: Extra3Reg. self MoveR: Extra3Reg Mw: 8 r: SPReg. @@ -6121,155 +6127,157 @@ DruidTestRTLCompiler >> gen_primitiveAtPut [ self MoveR: Extra1Reg R: Extra2Reg. self AndCq: 16r3FFFFF R: Extra2Reg. self CmpCq: 36 R: Extra2Reg. - jump3 := self JumpZero: 0. + jump4 := self JumpZero: 0. self LogicalShiftRightCq: 24 R: Extra1Reg. self AndCq: 31 R: Extra1Reg. self MoveMw: 0 r: SPReg R: Extra3Reg. self MoveMb: 7 r: Extra3Reg R: Extra2Reg. self AndCq: 255 R: Extra2Reg. self CmpCq: 255 R: Extra2Reg. - jump4 := self JumpNonZero: 0. + jump5 := self JumpNonZero: 0. self MoveMw: 0 r: SPReg R: Extra3Reg. self MoveM64: -8 r: Extra3Reg R: Extra2Reg. self LogicalShiftLeftCq: 8 R: Extra2Reg. self LogicalShiftRightCq: 8 R: Extra2Reg. - jump5 := self Jump: 0. - currentBlock := self Label. - jump4 jmpTarget: currentBlock. + jump6 := self Jump: 0. currentBlock := self Label. jump5 jmpTarget: currentBlock. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. self CmpCq: 5 R: Extra1Reg. - jump5 := self JumpAbove: 0. - self MoveR: Extra2Reg R: ClassReg. - jump4 := self Jump: 0. + jump6 := self JumpAbove: 0. + jump5 := self Jump: 0. currentBlock := self Label. - jump5 jmpTarget: currentBlock. + jump6 jmpTarget: currentBlock. self CmpCq: 16 R: Extra1Reg. - jump5 := self JumpBelow: 0. - jump6 := self Jump: 0. - currentBlock := self Label. - jump5 jmpTarget: currentBlock. - self CmpCq: 12 R: Extra1Reg. - jump5 := self JumpBelow: 0. + jump6 := self JumpBelow: 0. + self LogicalShiftLeftCq: 3 R: Extra2Reg. + self MoveR: Extra1Reg R: ClassReg. + self AndCq: 7 R: ClassReg. + self SubR: ClassReg R: Extra2Reg. self MoveR: Extra2Reg R: ClassReg. - self LogicalShiftLeftCq: 2 R: ClassReg. - self MoveR: Extra1Reg R: SendNumArgsReg. - self AndCq: 3 R: SendNumArgsReg. - self SubR: SendNumArgsReg R: ClassReg. jump7 := self Jump: 0. currentBlock := self Label. - jump5 jmpTarget: currentBlock. + jump6 jmpTarget: currentBlock. + self CmpCq: 12 R: Extra1Reg. + jump6 := self JumpBelow: 0. + self LogicalShiftLeftCq: 2 R: Extra2Reg. + self MoveR: Extra1Reg R: ClassReg. + self AndCq: 3 R: ClassReg. + self SubR: ClassReg R: Extra2Reg. + jump8 := self Jump: 0. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. self CmpCq: 10 R: Extra1Reg. - jump5 := self JumpBelow: 0. - self MoveR: Extra2Reg R: SendNumArgsReg. - self LogicalShiftLeftCq: 1 R: SendNumArgsReg. + jump6 := self JumpBelow: 0. + self LogicalShiftLeftCq: 1 R: Extra2Reg. self MoveR: Extra1Reg R: ClassReg. self AndCq: 1 R: ClassReg. - self SubR: ClassReg R: SendNumArgsReg. - self MoveR: SendNumArgsReg R: ClassReg. - jump8 := self Jump: 0. + self SubR: ClassReg R: Extra2Reg. + jump9 := self Jump: 0. currentBlock := self Label. - jump5 jmpTarget: currentBlock. + jump6 jmpTarget: currentBlock. self CmpCq: 9 R: Extra1Reg. - jump5 := self JumpNonZero: 0. - self MoveR: Extra2Reg R: ClassReg. - jump9 := self Jump: 0. + jump6 := self JumpNonZero: 0. + jump10 := self Jump: 0. currentBlock := self Label. - jump5 jmpTarget: currentBlock. - s52 := 0. - self MoveCq: s52 R: ClassReg. + jump6 jmpTarget: currentBlock. + s59 := 0. + self MoveCq: s59 R: Extra2Reg. currentBlock := self Label. - jump4 jmpTarget: currentBlock. - jump7 jmpTarget: currentBlock. + jump5 jmpTarget: currentBlock. jump8 jmpTarget: currentBlock. jump9 jmpTarget: currentBlock. + jump10 jmpTarget: currentBlock. self CmpCq: 9 R: Extra1Reg. - jump9 := self JumpBelow: 0. + jump10 := self JumpBelow: 0. + self MoveR: Extra2Reg R: ClassReg. currentBlock := self Label. - jump6 jmpTarget: currentBlock. - jump6 := self Jump: 0. + jump7 jmpTarget: currentBlock. + jump7 := self Jump: 0. currentBlock := self Label. - jump9 jmpTarget: currentBlock. + jump10 jmpTarget: currentBlock. self CmpCq: 2 R: Extra1Reg. - jump9 := self JumpNonZero: 0. + jump10 := self JumpNonZero: 0. + self MoveR: Extra2Reg R: ClassReg. currentBlock := self Label. - jump6 jmpTarget: currentBlock. - s60 := 0. - self MoveCq: s60 R: SendNumArgsReg. - jump6 := self Jump: 0. + jump7 jmpTarget: currentBlock. + s74 := 0. + self MoveCq: s74 R: SendNumArgsReg. + jump7 := self Jump: 0. currentBlock := self Label. - jump9 jmpTarget: currentBlock. + jump10 jmpTarget: currentBlock. self CmpCq: 2 R: Extra1Reg. - jump9 := self JumpAboveOrEqual: 0. - self MoveR: ClassReg R: SendNumArgsReg. - self MoveR: ClassReg R: Extra2Reg. - jump8 := self Jump: 0. + jump10 := self JumpAboveOrEqual: 0. + self MoveR: Extra2Reg R: SendNumArgsReg. + self MoveR: Extra2Reg R: ClassReg. + jump9 := self Jump: 0. currentBlock := self Label. - jump9 jmpTarget: currentBlock. + jump10 jmpTarget: currentBlock. self MoveMw: 0 r: SPReg R: Extra3Reg. - self MoveM64: 0 r: Extra3Reg R: Extra2Reg. - self AndCq: 16r3FFFFF R: Extra2Reg. - self CmpCq: 31 R: Extra2Reg. - jump9 := self JumpAbove: 0. - self CmpCq: 31 R: Extra2Reg. - jump7 := self JumpNonZero: 0. + self MoveM64: 0 r: Extra3Reg R: ClassReg. + self AndCq: 16r3FFFFF R: ClassReg. + self CmpCq: 31 R: ClassReg. + jump10 := self JumpAbove: 0. + self CmpCq: 31 R: ClassReg. + jump8 := self JumpNonZero: 0. self MoveMw: 0 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg R: Extra2Reg. - jump4 := self Jump: 0. - currentBlock := self Label. - jump7 jmpTarget: currentBlock. - self CmpCq: 8 R: Extra2Reg. - jump7 := self JumpNonZero: 0. - self genMoveConstant: objectMemory nilObject R: Extra2Reg. + self MoveR: Extra3Reg R: ClassReg. jump5 := self Jump: 0. currentBlock := self Label. - jump9 jmpTarget: currentBlock. - jump7 jmpTarget: currentBlock. - self MoveR: Extra2Reg R: SendNumArgsReg. + jump8 jmpTarget: currentBlock. + self CmpCq: 8 R: ClassReg. + jump8 := self JumpNonZero: 0. + self genMoveConstant: objectMemory nilObject R: ClassReg. + jump6 := self Jump: 0. + currentBlock := self Label. + jump10 jmpTarget: currentBlock. + jump8 jmpTarget: currentBlock. + self MoveR: ClassReg R: SendNumArgsReg. self LogicalShiftRightCq: 10 R: SendNumArgsReg. - s80 := objectMemory hiddenRootsObject. + s94 := objectMemory hiddenRootsObject. self LogicalShiftLeftCq: 3 R: SendNumArgsReg. - self AddCq: s80 R: SendNumArgsReg. + self AddCq: s94 R: SendNumArgsReg. self MoveM64: 8 r: SendNumArgsReg R: SendNumArgsReg. self genMoveConstant: objectMemory nilObject R: Extra0Reg. self CmpR: Extra0Reg R: SendNumArgsReg. - jump7 := self JumpNonZero: 0. + jump8 := self JumpNonZero: 0. self genMoveConstant: objectMemory nilObject R: Extra0Reg. - jump9 := self Jump: 0. + jump10 := self Jump: 0. currentBlock := self Label. - jump7 jmpTarget: currentBlock. - self AndCq: 1023 R: Extra2Reg. - self LogicalShiftLeftCq: 3 R: Extra2Reg. - self AddR: Extra2Reg R: SendNumArgsReg. + jump8 jmpTarget: currentBlock. + self AndCq: 1023 R: ClassReg. + self LogicalShiftLeftCq: 3 R: ClassReg. + self AddR: ClassReg R: SendNumArgsReg. self MoveM64: 8 r: SendNumArgsReg R: Extra0Reg. currentBlock := self Label. - jump9 jmpTarget: currentBlock. - self MoveR: Extra0Reg R: Extra2Reg. + jump10 jmpTarget: currentBlock. + self MoveR: Extra0Reg R: ClassReg. currentBlock := self Label. - jump4 jmpTarget: currentBlock. jump5 jmpTarget: currentBlock. - self MoveM64: 24 r: Extra2Reg R: Extra0Reg. + jump6 jmpTarget: currentBlock. + self MoveM64: 24 r: ClassReg R: Extra0Reg. self ArithmeticShiftRightCq: 3 R: Extra0Reg. self AndCq: 16rFFFF R: Extra0Reg. self MoveR: Extra0Reg R: SendNumArgsReg. - self MoveR: ClassReg R: Extra2Reg. + self MoveR: Extra2Reg R: ClassReg. currentBlock := self Label. - jump6 jmpTarget: currentBlock. - jump8 jmpTarget: currentBlock. - self SubR: SendNumArgsReg R: Extra2Reg. + jump7 jmpTarget: currentBlock. + jump9 jmpTarget: currentBlock. + self SubR: SendNumArgsReg R: ClassReg. self CmpCq: 24 R: Extra1Reg. - jump8 := self JumpAboveOrEqual: 0. + jump9 := self JumpAboveOrEqual: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. self CmpCq: 1 R: Extra3Reg. - jump6 := self JumpBelow: 0. + jump7 := self JumpBelow: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. - self CmpR: Extra2Reg R: Extra3Reg. - jump5 := self JumpAbove: 0. + self CmpR: ClassReg R: Extra3Reg. + jump6 := self JumpAbove: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. self AddR: SendNumArgsReg R: Extra3Reg. self MoveR: Extra3Reg Mw: 8 r: SPReg. self CmpCq: 5 R: Extra1Reg. - jump4 := self JumpAbove: 0. + jump5 := self JumpAbove: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. self SubCq: 1 R: Extra3Reg. self MoveR: Extra3Reg Mw: 8 r: SPReg. @@ -6277,30 +6285,30 @@ DruidTestRTLCompiler >> gen_primitiveAtPut [ self MoveR: Extra3Reg R: Extra0Reg. self AndCq: 7 R: Extra0Reg. self CmpCq: 0 R: Extra0Reg. - jump9 := self JumpNonZero: 0. - s118 := objectMemory getMemoryMap getSpaceMaskToUse. + jump10 := self JumpNonZero: 0. + s131 := objectMemory getMemoryMap getSpaceMaskToUse. self MoveMw: 0 r: SPReg R: Extra3Reg. self MoveR: Extra3Reg R: Extra0Reg. - self AndCq: s118 R: Extra0Reg. - s121 := objectMemory getMemoryMap getOldSpaceMask. - self CmpCq: s121 R: Extra0Reg. - jump7 := self JumpNonZero: 0. + self AndCq: s131 R: Extra0Reg. + s134 := objectMemory getMemoryMap getOldSpaceMask. + self CmpCq: s134 R: Extra0Reg. + jump8 := self JumpNonZero: 0. self MoveMw: 16 r: SPReg R: Extra3Reg. self MoveR: Extra3Reg R: Extra0Reg. self AndCq: 7 R: Extra0Reg. self CmpCq: 0 R: Extra0Reg. - jump10 := self JumpNonZero: 0. - s126 := objectMemory getMemoryMap getSpaceMaskToUse. + jump11 := self JumpNonZero: 0. + s139 := objectMemory getMemoryMap getSpaceMaskToUse. self MoveMw: 16 r: SPReg R: Extra3Reg. self MoveR: Extra3Reg R: Extra0Reg. - self AndCq: s126 R: Extra0Reg. - s129 := objectMemory getMemoryMap getNewSpaceMask. - self CmpCq: s129 R: Extra0Reg. - jump11 := self JumpNonZero: 0. - s131 := objectMemory getMemoryMap getNewSpaceStart. + self AndCq: s139 R: Extra0Reg. + s142 := objectMemory getMemoryMap getNewSpaceMask. + self CmpCq: s142 R: Extra0Reg. + jump12 := self JumpNonZero: 0. + s144 := objectMemory getMemoryMap getNewSpaceStart. self MoveMw: 16 r: SPReg R: Extra3Reg. self MoveR: Extra3Reg R: Extra0Reg. - self CmpCq: s131 R: Extra0Reg. + self CmpCq: s144 R: Extra0Reg. jumpTrue := self JumpAboveOrEqual: 0. self MoveCq: 0 R: Extra0Reg. jumpNext := self Jump: 0. @@ -6308,67 +6316,67 @@ DruidTestRTLCompiler >> gen_primitiveAtPut [ self MoveCq: 1 R: Extra0Reg. jumpNext jmpTarget: self Label. self CmpCq: 1 R: Extra0Reg. - jump12 := self JumpNonZero: 0. + jump13 := self JumpNonZero: 0. self MoveMw: 0 r: SPReg R: Extra3Reg. self MoveM64: 0 r: Extra3Reg R: Extra0Reg. self LogicalShiftRightCq: 29 R: Extra0Reg. self AndCq: 1 R: Extra0Reg. self CmpCq: 0 R: Extra0Reg. - jump13 := self JumpNonZero: 0. + jump14 := self JumpNonZero: 0. self MoveMw: 0 r: SPReg R: Extra3Reg. self MoveR: Extra3Reg R: TempReg. backEnd saveAndRestoreLinkRegAround: [ self CallRT: ceStoreCheckTrampoline ]. - jump14 := self Jump: 0. + jump15 := self Jump: 0. currentBlock := self Label. - jump11 jmpTarget: currentBlock. + jump12 jmpTarget: currentBlock. currentBlock := self Label. - jump9 jmpTarget: currentBlock. - jump7 jmpTarget: currentBlock. jump10 jmpTarget: currentBlock. - jump12 jmpTarget: currentBlock. + jump8 jmpTarget: currentBlock. + jump11 jmpTarget: currentBlock. jump13 jmpTarget: currentBlock. jump14 jmpTarget: currentBlock. + jump15 jmpTarget: currentBlock. self MoveMw: 0 r: SPReg R: Extra3Reg. self MoveM64: 0 r: Extra3Reg R: Extra0Reg. self LogicalShiftRightCq: 29 R: Extra0Reg. self AndCq: 1 R: Extra0Reg. self CmpCq: 0 R: Extra0Reg. - jump14 := self JumpNonZero: 0. + jump15 := self JumpNonZero: 0. self MoveMw: 16 r: SPReg R: Extra3Reg. self TstCq: 7 R: Extra3Reg. - jump13 := self JumpNonZero: 0. + jump14 := self JumpNonZero: 0. self MoveMw: 0 r: SPReg R: Extra3Reg. self CmpCq: 16r20000000000 R: Extra3Reg. - jump12 := self JumpBelow: 0. + jump13 := self JumpBelow: 0. self MoveMw: 16 r: SPReg R: Extra3Reg. self CmpCq: 16r20000000000 R: Extra3Reg. - jump10 := self JumpAboveOrEqual: 0. + jump11 := self JumpAboveOrEqual: 0. self genMoveConstant: objectMemory nilObject R: Extra0Reg. self MoveMw: 16 r: SPReg R: Extra3Reg. self CmpR: Extra0Reg R: Extra3Reg. - jump7 := self JumpBelow: 0. - s153 := objectMemory trueObject. + jump8 := self JumpBelow: 0. + s166 := objectMemory trueObject. self MoveMw: 16 r: SPReg R: Extra3Reg. - self CmpCq: s153 R: Extra3Reg. - jump9 := self JumpBelowOrEqual: 0. + self CmpCq: s166 R: Extra3Reg. + jump10 := self JumpBelowOrEqual: 0. currentBlock := self Label. - jump7 jmpTarget: currentBlock. - s155 := objectMemory getMemoryMap getNewSpaceStart. + jump8 jmpTarget: currentBlock. + s168 := objectMemory getMemoryMap getNewSpaceStart. self MoveMw: 16 r: SPReg R: Extra3Reg. - self CmpCq: s155 R: Extra3Reg. - jump7 := self JumpBelow: 0. + self CmpCq: s168 R: Extra3Reg. + jump8 := self JumpBelow: 0. self MoveMw: 0 r: SPReg R: Extra3Reg. self MoveR: Extra3Reg R: TempReg. backEnd saveAndRestoreLinkRegAround: [ self CallRT: ceStoreCheckTrampoline ]. currentBlock := self Label. + jump15 jmpTarget: currentBlock. jump14 jmpTarget: currentBlock. jump13 jmpTarget: currentBlock. - jump12 jmpTarget: currentBlock. + jump11 jmpTarget: currentBlock. jump10 jmpTarget: currentBlock. - jump9 jmpTarget: currentBlock. - jump7 jmpTarget: currentBlock. + jump8 jmpTarget: currentBlock. self MoveMw: 8 r: SPReg R: Extra3Reg. self LogicalShiftLeftCq: 3 R: Extra3Reg. self MoveR: Extra3Reg Mw: 8 r: SPReg. @@ -6379,23 +6387,21 @@ DruidTestRTLCompiler >> gen_primitiveAtPut [ self MoveMw: 16 r: SPReg R: Extra3Reg. self MoveMw: 0 r: SPReg R: Extra4Reg. self MoveR: Extra3Reg M64: 8 r: Extra4Reg. - self MoveMw: 16 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg R: ReceiverResultReg. - jump7 := self Jump: 0. + jump8 := self Jump: 0. currentBlock := self Label. - jump4 jmpTarget: currentBlock. + jump5 jmpTarget: currentBlock. self CmpCq: 16 R: Extra1Reg. - jump4 := self JumpBelow: 0. + jump5 := self JumpBelow: 0. self MoveMw: 16 r: SPReg R: Extra3Reg. self TstCq: 1 R: Extra3Reg. - jump9 := self JumpZero: 0. + jump10 := self JumpZero: 0. self MoveMw: 16 r: SPReg R: Extra3Reg. self MoveR: Extra3Reg R: Extra0Reg. self ArithmeticShiftRightCq: 3 R: Extra0Reg. self CmpCq: 0 R: Extra0Reg. - jump10 := self JumpBelow: 0. + jump11 := self JumpBelow: 0. self CmpCq: 255 R: Extra0Reg. - jump12 := self JumpAbove: 0. + jump13 := self JumpAbove: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. self MoveMw: 0 r: SPReg R: Extra4Reg. self AddR: Extra4Reg R: Extra3Reg. @@ -6405,23 +6411,21 @@ DruidTestRTLCompiler >> gen_primitiveAtPut [ self MoveR: Extra3Reg Mw: 8 r: SPReg. self MoveMw: 8 r: SPReg R: Extra3Reg. self MoveR: Extra0Reg Mb: 8 r: Extra3Reg. - self MoveMw: 16 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg R: ReceiverResultReg. - jump13 := self Jump: 0. + jump14 := self Jump: 0. currentBlock := self Label. - jump4 jmpTarget: currentBlock. + jump5 jmpTarget: currentBlock. self CmpCq: 12 R: Extra1Reg. - jump4 := self JumpBelow: 0. + jump5 := self JumpBelow: 0. self MoveMw: 16 r: SPReg R: Extra3Reg. self TstCq: 1 R: Extra3Reg. - jump14 := self JumpZero: 0. + jump15 := self JumpZero: 0. self MoveMw: 16 r: SPReg R: Extra3Reg. self MoveR: Extra3Reg R: Extra0Reg. self ArithmeticShiftRightCq: 3 R: Extra0Reg. self CmpCq: 0 R: Extra0Reg. - jump11 := self JumpBelow: 0. + jump12 := self JumpBelow: 0. self CmpCq: 16rFFFF R: Extra0Reg. - jump15 := self JumpAbove: 0. + jump16 := self JumpAbove: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. self SubCq: 1 R: Extra3Reg. self MoveR: Extra3Reg Mw: 8 r: SPReg. @@ -6433,12 +6437,12 @@ DruidTestRTLCompiler >> gen_primitiveAtPut [ self AddR: Extra4Reg R: Extra3Reg. self MoveR: Extra3Reg Mw: 0 r: SPReg. self MoveMw: 0 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg R: ClassReg. - self AddCq: 8 R: ClassReg. - self MoveR: ClassReg R: Extra1Reg. + self MoveR: Extra3Reg R: Extra2Reg. + self AddCq: 8 R: Extra2Reg. + self MoveR: Extra2Reg R: Extra1Reg. self AndCq: 2 R: Extra1Reg. self CmpCq: 0 R: Extra1Reg. - jump16 := self JumpNonZero: 0. + jump17 := self JumpNonZero: 0. self MoveMw: 0 r: SPReg R: Extra3Reg. self MoveM32: 8 r: Extra3Reg R: Extra1Reg. self AndCq: 16rFFFFFFFF R: Extra1Reg. @@ -6446,38 +6450,38 @@ DruidTestRTLCompiler >> gen_primitiveAtPut [ self OrR: Extra0Reg R: Extra1Reg. self MoveMw: 0 r: SPReg R: Extra3Reg. self MoveR: Extra1Reg M32: 8 r: Extra3Reg. - jump17 := self Jump: 0. + jump18 := self Jump: 0. currentBlock := self Label. - jump16 jmpTarget: currentBlock. - self MoveM32: -2 r: ClassReg R: Extra1Reg. + jump17 jmpTarget: currentBlock. + self MoveM32: -2 r: Extra2Reg R: Extra1Reg. self AndCq: 16rFFFFFFFF R: Extra1Reg. self AndCq: 16rFFFF R: Extra1Reg. self LogicalShiftLeftCq: 16 R: Extra0Reg. self OrR: Extra0Reg R: Extra1Reg. - self MoveR: Extra1Reg M32: -2 r: ClassReg. + self MoveR: Extra1Reg M32: -2 r: Extra2Reg. currentBlock := self Label. - jump17 jmpTarget: currentBlock. + jump8 jmpTarget: currentBlock. + jump14 jmpTarget: currentBlock. + jump18 jmpTarget: currentBlock. self MoveMw: 16 r: SPReg R: Extra3Reg. self MoveR: Extra3Reg R: ReceiverResultReg. - currentBlock := self Label. - jump7 jmpTarget: currentBlock. - jump13 jmpTarget: currentBlock. self AddCq: 24 R: SPReg. self genPrimReturn. currentBlock := self Label. jump1 jmpTarget: currentBlock. jump2 jmpTarget: currentBlock. jump3 jmpTarget: currentBlock. - jump8 jmpTarget: currentBlock. - jump6 jmpTarget: currentBlock. - jump5 jmpTarget: currentBlock. + jump4 jmpTarget: currentBlock. jump9 jmpTarget: currentBlock. + jump7 jmpTarget: currentBlock. + jump6 jmpTarget: currentBlock. jump10 jmpTarget: currentBlock. - jump12 jmpTarget: currentBlock. - jump4 jmpTarget: currentBlock. - jump14 jmpTarget: currentBlock. jump11 jmpTarget: currentBlock. + jump13 jmpTarget: currentBlock. + jump5 jmpTarget: currentBlock. jump15 jmpTarget: currentBlock. + jump12 jmpTarget: currentBlock. + jump16 jmpTarget: currentBlock. self AddCq: 24 R: SPReg. ^ 0 ] @@ -7525,9 +7529,9 @@ DruidTestRTLCompiler >> gen_primitiveDivide [ self DivR: SendNumArgsReg R: ClassReg - Quo: SendNumArgsReg - Rem: ClassReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. + Quo: ClassReg + Rem: SendNumArgsReg. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -9450,9 +9454,9 @@ DruidTestRTLCompiler >> gen_primitiveIntegerDivide [ self DivR: SendNumArgsReg R: ClassReg - Quo: ClassReg - Rem: SendNumArgsReg. - self MoveR: ClassReg R: ReceiverResultReg. + Quo: SendNumArgsReg + Rem: ClassReg. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -9468,9 +9472,9 @@ DruidTestRTLCompiler >> gen_primitiveIntegerDivideByConstant [ self DivR: SendNumArgsReg R: ClassReg - Quo: ClassReg - Rem: SendNumArgsReg. - self MoveR: ClassReg R: ReceiverResultReg. + Quo: SendNumArgsReg + Rem: ClassReg. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -10203,15 +10207,15 @@ DruidTestRTLCompiler >> gen_primitiveNewWithArg [ self DivR: Extra2Reg R: Extra0Reg - Quo: Extra0Reg - Rem: Extra2Reg. + Quo: Extra2Reg + Rem: Extra0Reg. s101 := 8. - self MoveCq: s101 R: Extra2Reg. - self SubR: SendNumArgsReg R: Extra2Reg. - self AndCq: 7 R: Extra2Reg. - self AddR: Extra2Reg R: Extra1Reg. + self MoveCq: s101 R: Extra0Reg. + self SubR: SendNumArgsReg R: Extra0Reg. + self AndCq: 7 R: Extra0Reg. + self AddR: Extra0Reg R: Extra1Reg. self MoveCq: s94 R: ClassReg. - self MoveR: Extra0Reg R: SendNumArgsReg. + self MoveR: Extra2Reg R: SendNumArgsReg. jump12 := self Jump: 0. currentBlock := self Label. jump3 jmpTarget: currentBlock. diff --git a/Druid-Tests/SimpleDruidTestRTLCompiler.class.st b/Druid-Tests/SimpleDruidTestRTLCompiler.class.st index c6298e22..f3ea27ee 100644 --- a/Druid-Tests/SimpleDruidTestRTLCompiler.class.st +++ b/Druid-Tests/SimpleDruidTestRTLCompiler.class.st @@ -1660,7 +1660,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAdd [ | jump1 jump2 currentBlock | self mclassIsSmallInteger ifFalse: [ ^ UnimplementedPrimitive ]. self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArgAtDepth: 0 into: SendNumArgsReg. self TstCq: 1 R: SendNumArgsReg. jump1 := self JumpZero: 0. self AddCq: -1 R: SendNumArgsReg. @@ -1766,7 +1766,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAsCharacter [ s13 := self methodNumArgs. s13 = 1 ifTrue: [ | jump3 jump2 jump1 | - self genLoadArg: 0 into: ClassReg. + self genLoadArgAtDepth: 0 into: ClassReg. self TstCq: 1 R: ClassReg. jump3 := self JumpZero: 0. self ArithmeticShiftRightCq: 3 R: ClassReg. @@ -1981,11 +1981,11 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAssertIsIgnored [ SimpleDruidTestRTLCompiler >> gen_primitiveAt [ "AutoGenerated by Druid" - | jump1 s60 jumpNext s114 jump9 jump6 jump3 currentBlock s91 jump5 jumpTrue jump2 jump8 jump7 jump4 | + | jump1 jump10 jump9 jump6 jump3 jump12 currentBlock jump8 jump5 jump2 s73 jump11 s55 s93 jump7 jump4 | self SubCq: 24 R: SPReg. self MoveR: ReceiverResultReg R: Extra3Reg. self MoveR: Extra3Reg Mw: 0 r: SPReg. - self genLoadArgAtDepth: 0 into: Extra3Reg. + self genLoadArgAtDepth: 3 into: Extra3Reg. self MoveR: Extra3Reg Mw: 8 r: SPReg. self MoveMw: 0 r: SPReg R: Extra3Reg. self TstCq: 7 R: Extra3Reg. @@ -1995,6 +1995,11 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAt [ self AndCq: 1 R: Extra0Reg. self CmpCq: 0 R: Extra0Reg. jump2 := self JumpZero: 0. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveM64: 0 r: Extra3Reg R: Extra0Reg. + self AndCq: 16r3FFFF7 R: Extra0Reg. + self CmpCq: 0 R: Extra0Reg. + jump3 := self JumpZero: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. self ArithmeticShiftRightCq: 3 R: Extra3Reg. self MoveR: Extra3Reg Mw: 8 r: SPReg. @@ -2009,45 +2014,33 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAt [ self MoveMb: 7 r: Extra3Reg R: Extra2Reg. self AndCq: 255 R: Extra2Reg. self CmpCq: 255 R: Extra2Reg. - jump3 := self JumpNonZero: 0. + jump4 := self JumpNonZero: 0. self MoveMw: 0 r: SPReg R: Extra3Reg. self MoveM64: -8 r: Extra3Reg R: Extra2Reg. self LogicalShiftLeftCq: 8 R: Extra2Reg. self LogicalShiftRightCq: 8 R: Extra2Reg. - jump4 := self Jump: 0. - currentBlock := self Label. - jump3 jmpTarget: currentBlock. + jump5 := self Jump: 0. currentBlock := self Label. jump4 jmpTarget: currentBlock. + currentBlock := self Label. + jump5 jmpTarget: currentBlock. self CmpCq: 5 R: Extra1Reg. - jump4 := self JumpAbove: 0. - jump3 := self Jump: 0. + jump5 := self JumpAbove: 0. + jump4 := self Jump: 0. currentBlock := self Label. - jump4 jmpTarget: currentBlock. + jump5 jmpTarget: currentBlock. self CmpCq: 16 R: Extra1Reg. - jump4 := self JumpBelow: 0. + jump5 := self JumpBelow: 0. self LogicalShiftLeftCq: 3 R: Extra2Reg. self MoveR: Extra1Reg R: ClassReg. self AndCq: 7 R: ClassReg. self SubR: ClassReg R: Extra2Reg. - self MoveR: Extra1Reg R: ClassReg. - self CmpCq: 9 R: ClassReg. - jumpTrue := self JumpAboveOrEqual: 0. - self MoveCq: 0 R: ClassReg. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: ClassReg. - jumpNext jmpTarget: self Label. - self CmpCq: 1 R: ClassReg. - jump5 := self JumpNonZero: 0. + self MoveR: Extra2Reg R: ClassReg. jump6 := self Jump: 0. currentBlock := self Label. jump5 jmpTarget: currentBlock. - jump5 := self Jump: 0. - currentBlock := self Label. - jump4 jmpTarget: currentBlock. self CmpCq: 12 R: Extra1Reg. - jump4 := self JumpBelow: 0. + jump5 := self JumpBelow: 0. self LogicalShiftLeftCq: 2 R: Extra2Reg. self MoveR: Extra1Reg R: ClassReg. self AndCq: 3 R: ClassReg. @@ -2055,128 +2048,106 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAt [ self MoveR: Extra2Reg R: ClassReg. jump7 := self Jump: 0. currentBlock := self Label. - jump4 jmpTarget: currentBlock. + jump5 jmpTarget: currentBlock. self CmpCq: 10 R: Extra1Reg. - jump4 := self JumpBelow: 0. + jump5 := self JumpBelow: 0. self LogicalShiftLeftCq: 1 R: Extra2Reg. self MoveR: Extra1Reg R: ClassReg. self AndCq: 1 R: ClassReg. self SubR: ClassReg R: Extra2Reg. - self MoveR: Extra2Reg R: ClassReg. jump8 := self Jump: 0. currentBlock := self Label. - jump4 jmpTarget: currentBlock. + jump5 jmpTarget: currentBlock. self CmpCq: 9 R: Extra1Reg. - jump4 := self JumpNonZero: 0. - self MoveR: Extra2Reg R: ClassReg. + jump5 := self JumpNonZero: 0. jump9 := self Jump: 0. currentBlock := self Label. - jump4 jmpTarget: currentBlock. - s60 := 0. - self MoveCq: s60 R: ClassReg. + jump5 jmpTarget: currentBlock. + s55 := 0. + self MoveCq: s55 R: Extra2Reg. currentBlock := self Label. - jump7 jmpTarget: currentBlock. + jump4 jmpTarget: currentBlock. jump8 jmpTarget: currentBlock. jump9 jmpTarget: currentBlock. - self MoveR: Extra1Reg R: Extra2Reg. - self CmpCq: 9 R: Extra2Reg. - jumpTrue := self JumpAboveOrEqual: 0. - self MoveCq: 0 R: Extra2Reg. - jumpNext := self Jump: 0. - jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: Extra2Reg. - jumpNext jmpTarget: self Label. self CmpCq: 9 R: Extra1Reg. jump9 := self JumpBelow: 0. - self CmpCq: 1 R: Extra2Reg. - jump8 := self JumpNonZero: 0. - self MoveR: ClassReg R: Extra2Reg. - currentBlock := self Label. - jump6 jmpTarget: currentBlock. self MoveR: Extra2Reg R: ClassReg. - jump6 := self Jump: 0. currentBlock := self Label. - jump8 jmpTarget: currentBlock. - self MoveR: ClassReg R: Extra2Reg. + jump7 jmpTarget: currentBlock. currentBlock := self Label. - jump5 jmpTarget: currentBlock. - self MoveR: Extra2Reg R: ClassReg. - jump5 := self Jump: 0. + jump6 jmpTarget: currentBlock. + jump6 := self Jump: 0. currentBlock := self Label. jump9 jmpTarget: currentBlock. - self MoveR: ClassReg R: Extra2Reg. - currentBlock := self Label. - jump3 jmpTarget: currentBlock. self CmpCq: 2 R: Extra1Reg. - jump3 := self JumpNonZero: 0. + jump9 := self JumpNonZero: 0. self MoveR: Extra2Reg R: ClassReg. currentBlock := self Label. jump6 jmpTarget: currentBlock. - s91 := 0. - self MoveCq: s91 R: Extra2Reg. + s73 := 0. + self MoveCq: s73 R: SendNumArgsReg. jump6 := self Jump: 0. currentBlock := self Label. - jump3 jmpTarget: currentBlock. - self MoveR: Extra2Reg R: ClassReg. - currentBlock := self Label. - jump5 jmpTarget: currentBlock. + jump9 jmpTarget: currentBlock. self CmpCq: 2 R: Extra1Reg. - jump5 := self JumpAboveOrEqual: 0. - self MoveR: ClassReg R: Extra2Reg. - jump3 := self Jump: 0. + jump9 := self JumpAboveOrEqual: 0. + self MoveR: Extra2Reg R: SendNumArgsReg. + self MoveR: Extra2Reg R: ClassReg. + jump7 := self Jump: 0. currentBlock := self Label. - jump5 jmpTarget: currentBlock. + jump9 jmpTarget: currentBlock. self MoveMw: 0 r: SPReg R: Extra3Reg. - self MoveM64: 0 r: Extra3Reg R: Extra2Reg. - self AndCq: 16r3FFFFF R: Extra2Reg. - self CmpCq: 31 R: Extra2Reg. - jump5 := self JumpAbove: 0. - self CmpCq: 31 R: Extra2Reg. - jump9 := self JumpNonZero: 0. + self MoveM64: 0 r: Extra3Reg R: ClassReg. + self AndCq: 16r3FFFFF R: ClassReg. + self CmpCq: 31 R: ClassReg. + jump9 := self JumpAbove: 0. + self CmpCq: 31 R: ClassReg. + jump8 := self JumpNonZero: 0. self MoveMw: 0 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg R: Extra2Reg. - jump8 := self Jump: 0. + self MoveR: Extra3Reg R: ClassReg. + jump4 := self Jump: 0. currentBlock := self Label. - jump9 jmpTarget: currentBlock. - self CmpCq: 8 R: Extra2Reg. - jump9 := self JumpNonZero: 0. - self genMoveConstant: objectMemory nilObject R: Extra2Reg. - jump7 := self Jump: 0. + jump8 jmpTarget: currentBlock. + self CmpCq: 8 R: ClassReg. + jump8 := self JumpNonZero: 0. + self genMoveConstant: objectMemory nilObject R: ClassReg. + jump5 := self Jump: 0. currentBlock := self Label. - jump5 jmpTarget: currentBlock. jump9 jmpTarget: currentBlock. - self MoveR: Extra2Reg R: SendNumArgsReg. + jump8 jmpTarget: currentBlock. + self MoveR: ClassReg R: SendNumArgsReg. self LogicalShiftRightCq: 10 R: SendNumArgsReg. - s114 := objectMemory hiddenRootsObject. + s93 := objectMemory hiddenRootsObject. self LogicalShiftLeftCq: 3 R: SendNumArgsReg. - self AddCq: s114 R: SendNumArgsReg. + self AddCq: s93 R: SendNumArgsReg. self MoveM64: 8 r: SendNumArgsReg R: SendNumArgsReg. self genMoveConstant: objectMemory nilObject R: Extra0Reg. self CmpR: Extra0Reg R: SendNumArgsReg. - jump9 := self JumpNonZero: 0. + jump8 := self JumpNonZero: 0. self genMoveConstant: objectMemory nilObject R: Extra0Reg. - jump5 := self Jump: 0. + jump9 := self Jump: 0. currentBlock := self Label. - jump9 jmpTarget: currentBlock. - self AndCq: 1023 R: Extra2Reg. - self LogicalShiftLeftCq: 3 R: Extra2Reg. - self AddR: Extra2Reg R: SendNumArgsReg. + jump8 jmpTarget: currentBlock. + self AndCq: 1023 R: ClassReg. + self LogicalShiftLeftCq: 3 R: ClassReg. + self AddR: ClassReg R: SendNumArgsReg. self MoveM64: 8 r: SendNumArgsReg R: Extra0Reg. currentBlock := self Label. - jump5 jmpTarget: currentBlock. - self MoveR: Extra0Reg R: Extra2Reg. + jump9 jmpTarget: currentBlock. + self MoveR: Extra0Reg R: ClassReg. currentBlock := self Label. - jump8 jmpTarget: currentBlock. - jump7 jmpTarget: currentBlock. - self MoveM64: 24 r: Extra2Reg R: Extra0Reg. + jump4 jmpTarget: currentBlock. + jump5 jmpTarget: currentBlock. + self MoveM64: 24 r: ClassReg R: Extra0Reg. self ArithmeticShiftRightCq: 3 R: Extra0Reg. self AndCq: 16rFFFF R: Extra0Reg. - self MoveR: Extra0Reg R: Extra2Reg. + self MoveR: Extra0Reg R: SendNumArgsReg. + self MoveR: Extra2Reg R: ClassReg. currentBlock := self Label. jump6 jmpTarget: currentBlock. - jump3 jmpTarget: currentBlock. + jump7 jmpTarget: currentBlock. self CmpCq: 3 R: Extra1Reg. - jump3 := self JumpNonZero: 0. + jump7 := self JumpNonZero: 0. self MoveMw: 16 r: SPReg R: Extra3Reg. self AndCq: 16r3FFFFF R: Extra3Reg. self MoveR: Extra3Reg Mw: 16 r: SPReg. @@ -2184,21 +2155,21 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAt [ self CmpCq: 36 R: Extra3Reg. jump6 := self JumpZero: 0. currentBlock := self Label. - jump3 jmpTarget: currentBlock. - self SubR: Extra2Reg R: ClassReg. + jump7 jmpTarget: currentBlock. + self SubR: SendNumArgsReg R: ClassReg. self CmpCq: 24 R: Extra1Reg. - jump3 := self JumpAboveOrEqual: 0. + jump7 := self JumpAboveOrEqual: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. self CmpCq: 1 R: Extra3Reg. - jump7 := self JumpBelow: 0. + jump5 := self JumpBelow: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. self CmpR: ClassReg R: Extra3Reg. - jump8 := self JumpAbove: 0. + jump4 := self JumpAbove: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. - self AddR: Extra2Reg R: Extra3Reg. + self AddR: SendNumArgsReg R: Extra3Reg. self MoveR: Extra3Reg Mw: 8 r: SPReg. self CmpCq: 5 R: Extra1Reg. - jump5 := self JumpAbove: 0. + jump9 := self JumpAbove: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. self SubCq: 1 R: Extra3Reg. self MoveR: Extra3Reg Mw: 8 r: SPReg. @@ -2211,12 +2182,11 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAt [ self MoveR: Extra3Reg Mw: 0 r: SPReg. self MoveMw: 0 r: SPReg R: Extra3Reg. self MoveM64: 8 r: Extra3Reg R: Extra0Reg. - self MoveR: Extra0Reg R: ReceiverResultReg. - jump9 := self Jump: 0. + jump8 := self Jump: 0. currentBlock := self Label. - jump5 jmpTarget: currentBlock. + jump9 jmpTarget: currentBlock. self CmpCq: 16 R: Extra1Reg. - jump5 := self JumpBelow: 0. + jump9 := self JumpBelow: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. self MoveMw: 0 r: SPReg R: Extra4Reg. self AddR: Extra4Reg R: Extra3Reg. @@ -2229,12 +2199,11 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAt [ self AndCq: 255 R: Extra0Reg. self LogicalShiftLeftCq: 3 R: Extra0Reg. self AddCq: 1 R: Extra0Reg. - self MoveR: Extra0Reg R: ReceiverResultReg. - jump4 := self Jump: 0. + jump10 := self Jump: 0. currentBlock := self Label. - jump5 jmpTarget: currentBlock. + jump9 jmpTarget: currentBlock. self CmpCq: 12 R: Extra1Reg. - jump5 := self JumpBelow: 0. + jump9 := self JumpBelow: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. self SubCq: 1 R: Extra3Reg. self MoveR: Extra3Reg Mw: 8 r: SPReg. @@ -2250,20 +2219,44 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAt [ self AndCq: 16rFFFF R: Extra0Reg. self LogicalShiftLeftCq: 3 R: Extra0Reg. self AddCq: 1 R: Extra0Reg. - self MoveR: Extra0Reg R: ReceiverResultReg. + jump11 := self Jump: 0. currentBlock := self Label. jump9 jmpTarget: currentBlock. - jump4 jmpTarget: currentBlock. + self CmpCq: 9 R: Extra1Reg. + jump9 := self JumpNonZero: 0. + self MoveMw: 8 r: SPReg R: Extra3Reg. + self SubCq: 1 R: Extra3Reg. + self MoveR: Extra3Reg Mw: 8 r: SPReg. + self MoveMw: 8 r: SPReg R: Extra3Reg. + self LogicalShiftLeftCq: 3 R: Extra3Reg. + self MoveR: Extra3Reg Mw: 8 r: SPReg. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveMw: 8 r: SPReg R: Extra4Reg. + self AddR: Extra4Reg R: Extra3Reg. + self MoveR: Extra3Reg Mw: 0 r: SPReg. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveM64: 8 r: Extra3Reg R: Extra0Reg. + self CmpCq: 16rFFFFFFFFFFFFFFF R: Extra0Reg. + jump12 := self JumpAbove: 0. + self LogicalShiftLeftCq: 3 R: Extra0Reg. + self AddCq: 1 R: Extra0Reg. + currentBlock := self Label. + jump8 jmpTarget: currentBlock. + jump10 jmpTarget: currentBlock. + jump11 jmpTarget: currentBlock. + self MoveR: Extra0Reg R: ReceiverResultReg. self AddCq: 24 R: SPReg. self genPrimReturn. currentBlock := self Label. jump1 jmpTarget: currentBlock. jump2 jmpTarget: currentBlock. - jump6 jmpTarget: currentBlock. jump3 jmpTarget: currentBlock. + jump6 jmpTarget: currentBlock. jump7 jmpTarget: currentBlock. - jump8 jmpTarget: currentBlock. jump5 jmpTarget: currentBlock. + jump4 jmpTarget: currentBlock. + jump9 jmpTarget: currentBlock. + jump12 jmpTarget: currentBlock. self AddCq: 24 R: SPReg. ^ 0 ] @@ -2272,444 +2265,391 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAt [ SimpleDruidTestRTLCompiler >> gen_primitiveAtPut [ "AutoGenerated by Druid" - | jump5 s206 s263 jump10 s94 s246 s55 jump3 s190 s62 jump1 s202 currentBlock jump8 jump13 jumpNext jump6 s154 jump11 s146 jump4 s159 jumpTrue jump9 s183 jump2 s157 jump14 s149 s181 jump7 s210 jump12 | - self SubCq: 48 R: SPReg. + | s131 jump5 jump17 jump10 s94 jump3 jump15 jump8 jump1 s134 currentBlock jump13 s139 jump6 jumpNext jump18 jump11 jump4 s168 jumpTrue jump16 jump9 jump2 s144 s166 s59 jump14 jump7 s142 s74 jump12 | + self SubCq: 24 R: SPReg. self MoveR: ReceiverResultReg R: Extra3Reg. self MoveR: Extra3Reg Mw: 0 r: SPReg. - self genLoadArgAtDepth: 0 into: Extra3Reg. - self MoveR: Extra3Reg Mw: 40 r: SPReg. - self genLoadArgAtDepth: 1 into: Extra0Reg. + self genLoadArg: 0 spilled: 3 into: Extra3Reg. + self MoveR: Extra3Reg Mw: 8 r: SPReg. + self genLoadArg: 1 spilled: 3 into: Extra3Reg. + self MoveR: Extra3Reg Mw: 16 r: SPReg. self MoveMw: 0 r: SPReg R: Extra3Reg. self TstCq: 7 R: Extra3Reg. jump1 := self JumpNonZero: 0. - self MoveMw: 40 r: SPReg R: Extra3Reg. + self MoveMw: 8 r: SPReg R: Extra3Reg. self MoveR: Extra3Reg R: Extra1Reg. self AndCq: 1 R: Extra1Reg. self CmpCq: 0 R: Extra1Reg. - jump2 := self JumpNonZero: 0. + jump2 := self JumpZero: 0. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveM64: 0 r: Extra3Reg R: Extra1Reg. + self AndCq: 16r3FFFF7 R: Extra1Reg. self CmpCq: 0 R: Extra1Reg. jump3 := self JumpZero: 0. - currentBlock := self Label. - jump2 jmpTarget: currentBlock. - self MoveMw: 40 r: SPReg R: Extra3Reg. + self MoveMw: 8 r: SPReg R: Extra3Reg. self ArithmeticShiftRightCq: 3 R: Extra3Reg. - self MoveR: Extra3Reg Mw: 40 r: SPReg. + self MoveR: Extra3Reg Mw: 8 r: SPReg. self MoveMw: 0 r: SPReg R: Extra3Reg. self MoveM64: 0 r: Extra3Reg R: Extra1Reg. self MoveR: Extra1Reg R: Extra2Reg. self AndCq: 16r3FFFFF R: Extra2Reg. self CmpCq: 36 R: Extra2Reg. - jump2 := self JumpZero: 0. + jump4 := self JumpZero: 0. self LogicalShiftRightCq: 24 R: Extra1Reg. self AndCq: 31 R: Extra1Reg. self MoveMw: 0 r: SPReg R: Extra3Reg. self MoveMb: 7 r: Extra3Reg R: Extra2Reg. self AndCq: 255 R: Extra2Reg. self CmpCq: 255 R: Extra2Reg. - jump4 := self JumpNonZero: 0. + jump5 := self JumpNonZero: 0. self MoveMw: 0 r: SPReg R: Extra3Reg. self MoveM64: -8 r: Extra3Reg R: Extra2Reg. self LogicalShiftLeftCq: 8 R: Extra2Reg. self LogicalShiftRightCq: 8 R: Extra2Reg. - jump5 := self Jump: 0. - currentBlock := self Label. - jump4 jmpTarget: currentBlock. + jump6 := self Jump: 0. currentBlock := self Label. jump5 jmpTarget: currentBlock. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. self CmpCq: 5 R: Extra1Reg. - jump5 := self JumpAbove: 0. - self MoveR: Extra2Reg R: Extra3Reg. - self MoveR: Extra3Reg Mw: 32 r: SPReg. - jump4 := self Jump: 0. + jump6 := self JumpAbove: 0. + jump5 := self Jump: 0. currentBlock := self Label. - jump5 jmpTarget: currentBlock. + jump6 jmpTarget: currentBlock. self CmpCq: 16 R: Extra1Reg. - jump5 := self JumpBelow: 0. + jump6 := self JumpBelow: 0. self LogicalShiftLeftCq: 3 R: Extra2Reg. self MoveR: Extra1Reg R: ClassReg. self AndCq: 7 R: ClassReg. self SubR: ClassReg R: Extra2Reg. - self MoveR: Extra2Reg R: Extra3Reg. - self MoveR: Extra3Reg Mw: 32 r: SPReg. - jump6 := self Jump: 0. + self MoveR: Extra2Reg R: ClassReg. + jump7 := self Jump: 0. currentBlock := self Label. - jump5 jmpTarget: currentBlock. + jump6 jmpTarget: currentBlock. self CmpCq: 12 R: Extra1Reg. - jump5 := self JumpBelow: 0. + jump6 := self JumpBelow: 0. self LogicalShiftLeftCq: 2 R: Extra2Reg. self MoveR: Extra1Reg R: ClassReg. self AndCq: 3 R: ClassReg. self SubR: ClassReg R: Extra2Reg. - self MoveR: Extra2Reg R: Extra3Reg. - self MoveR: Extra3Reg Mw: 32 r: SPReg. - jump7 := self Jump: 0. + jump8 := self Jump: 0. currentBlock := self Label. - jump5 jmpTarget: currentBlock. + jump6 jmpTarget: currentBlock. self CmpCq: 10 R: Extra1Reg. - jump5 := self JumpBelow: 0. + jump6 := self JumpBelow: 0. self LogicalShiftLeftCq: 1 R: Extra2Reg. self MoveR: Extra1Reg R: ClassReg. self AndCq: 1 R: ClassReg. self SubR: ClassReg R: Extra2Reg. - self MoveR: Extra2Reg R: Extra3Reg. - self MoveR: Extra3Reg Mw: 32 r: SPReg. - jump8 := self Jump: 0. - currentBlock := self Label. - jump5 jmpTarget: currentBlock. - self CmpCq: 9 R: Extra1Reg. - jump5 := self JumpNonZero: 0. - self MoveR: Extra2Reg R: Extra3Reg. - self MoveR: Extra3Reg Mw: 32 r: SPReg. jump9 := self Jump: 0. currentBlock := self Label. - jump5 jmpTarget: currentBlock. - s55 := 0. - self MoveCq: s55 R: Extra3Reg. - self MoveR: Extra3Reg Mw: 32 r: SPReg. + jump6 jmpTarget: currentBlock. + self CmpCq: 9 R: Extra1Reg. + jump6 := self JumpNonZero: 0. + jump10 := self Jump: 0. currentBlock := self Label. - jump4 jmpTarget: currentBlock. jump6 jmpTarget: currentBlock. - jump7 jmpTarget: currentBlock. + s59 := 0. + self MoveCq: s59 R: Extra2Reg. + currentBlock := self Label. + jump5 jmpTarget: currentBlock. jump8 jmpTarget: currentBlock. jump9 jmpTarget: currentBlock. + jump10 jmpTarget: currentBlock. self CmpCq: 9 R: Extra1Reg. - jump9 := self JumpBelow: 0. - self CmpCq: 9 R: Extra1Reg. - jump8 := self JumpAboveOrEqual: 0. - jump7 := self JumpBelow: 0. + jump10 := self JumpBelow: 0. + self MoveR: Extra2Reg R: ClassReg. currentBlock := self Label. - jump9 jmpTarget: currentBlock. - self CmpCq: 2 R: Extra1Reg. - jump9 := self JumpNonZero: 0. + jump7 jmpTarget: currentBlock. + jump7 := self Jump: 0. currentBlock := self Label. - jump8 jmpTarget: currentBlock. - s62 := 0. - self MoveCq: s62 R: Extra3Reg. - self MoveR: Extra3Reg Mw: 8 r: SPReg. - self MoveR: Extra3Reg Mw: 24 r: SPReg. - self MoveR: Extra3Reg Mw: 16 r: SPReg. - jump8 := self Jump: 0. + jump10 jmpTarget: currentBlock. + self CmpCq: 2 R: Extra1Reg. + jump10 := self JumpNonZero: 0. + self MoveR: Extra2Reg R: ClassReg. currentBlock := self Label. jump7 jmpTarget: currentBlock. - jump9 jmpTarget: currentBlock. - self CmpCq: 2 R: Extra1Reg. - jump9 := self JumpAboveOrEqual: 0. - self MoveMw: 32 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg Mw: 24 r: SPReg. - self MoveR: Extra3Reg Mw: 8 r: SPReg. - self MoveR: Extra1Reg R: Extra3Reg. - self MoveR: Extra3Reg Mw: 16 r: SPReg. - self MoveMw: 32 r: SPReg R: Extra3Reg. - self MoveMw: 0 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg R: ClassReg. - self MoveR: Extra0Reg R: Extra1Reg. - self MoveMw: 40 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg R: SendNumArgsReg. - self MoveMw: 0 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg R: Extra2Reg. + s74 := 0. + self MoveCq: s74 R: SendNumArgsReg. jump7 := self Jump: 0. currentBlock := self Label. - jump9 jmpTarget: currentBlock. + jump10 jmpTarget: currentBlock. + self CmpCq: 2 R: Extra1Reg. + jump10 := self JumpAboveOrEqual: 0. + self MoveR: Extra2Reg R: SendNumArgsReg. + self MoveR: Extra2Reg R: ClassReg. + jump9 := self Jump: 0. + currentBlock := self Label. + jump10 jmpTarget: currentBlock. self MoveMw: 0 r: SPReg R: Extra3Reg. self MoveM64: 0 r: Extra3Reg R: ClassReg. self AndCq: 16r3FFFFF R: ClassReg. self CmpCq: 31 R: ClassReg. - jump9 := self JumpAbove: 0. + jump10 := self JumpAbove: 0. self CmpCq: 31 R: ClassReg. - jump6 := self JumpNonZero: 0. + jump8 := self JumpNonZero: 0. self MoveMw: 0 r: SPReg R: Extra3Reg. self MoveR: Extra3Reg R: ClassReg. - jump4 := self Jump: 0. + jump5 := self Jump: 0. currentBlock := self Label. - jump6 jmpTarget: currentBlock. + jump8 jmpTarget: currentBlock. self CmpCq: 8 R: ClassReg. - jump6 := self JumpNonZero: 0. + jump8 := self JumpNonZero: 0. self genMoveConstant: objectMemory nilObject R: ClassReg. - jump5 := self Jump: 0. + jump6 := self Jump: 0. currentBlock := self Label. - jump9 jmpTarget: currentBlock. - jump6 jmpTarget: currentBlock. - self MoveR: ClassReg R: Extra2Reg. - self LogicalShiftRightCq: 10 R: Extra2Reg. + jump10 jmpTarget: currentBlock. + jump8 jmpTarget: currentBlock. + self MoveR: ClassReg R: SendNumArgsReg. + self LogicalShiftRightCq: 10 R: SendNumArgsReg. s94 := objectMemory hiddenRootsObject. - self LogicalShiftLeftCq: 3 R: Extra2Reg. - self AddCq: s94 R: Extra2Reg. - self MoveM64: 8 r: Extra2Reg R: Extra2Reg. - self genMoveConstant: objectMemory nilObject R: SendNumArgsReg. - self CmpR: SendNumArgsReg R: Extra2Reg. - jump6 := self JumpNonZero: 0. - self genMoveConstant: objectMemory nilObject R: SendNumArgsReg. - jump9 := self Jump: 0. + self LogicalShiftLeftCq: 3 R: SendNumArgsReg. + self AddCq: s94 R: SendNumArgsReg. + self MoveM64: 8 r: SendNumArgsReg R: SendNumArgsReg. + self genMoveConstant: objectMemory nilObject R: Extra0Reg. + self CmpR: Extra0Reg R: SendNumArgsReg. + jump8 := self JumpNonZero: 0. + self genMoveConstant: objectMemory nilObject R: Extra0Reg. + jump10 := self Jump: 0. currentBlock := self Label. - jump6 jmpTarget: currentBlock. + jump8 jmpTarget: currentBlock. self AndCq: 1023 R: ClassReg. self LogicalShiftLeftCq: 3 R: ClassReg. - self AddR: ClassReg R: Extra2Reg. - self MoveM64: 8 r: Extra2Reg R: SendNumArgsReg. + self AddR: ClassReg R: SendNumArgsReg. + self MoveM64: 8 r: SendNumArgsReg R: Extra0Reg. currentBlock := self Label. - jump9 jmpTarget: currentBlock. - self MoveR: SendNumArgsReg R: ClassReg. + jump10 jmpTarget: currentBlock. + self MoveR: Extra0Reg R: ClassReg. currentBlock := self Label. - jump4 jmpTarget: currentBlock. jump5 jmpTarget: currentBlock. - self MoveM64: 24 r: ClassReg R: SendNumArgsReg. - self ArithmeticShiftRightCq: 3 R: SendNumArgsReg. - self AndCq: 16rFFFF R: SendNumArgsReg. - self MoveR: SendNumArgsReg R: Extra3Reg. - self MoveR: Extra3Reg Mw: 8 r: SPReg. - self MoveR: Extra1Reg R: Extra3Reg. - self MoveR: Extra3Reg Mw: 16 r: SPReg. - self MoveMw: 32 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg Mw: 24 r: SPReg. - self MoveMw: 0 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg R: ClassReg. - self MoveR: Extra0Reg R: Extra1Reg. - self MoveMw: 40 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg R: SendNumArgsReg. - self MoveMw: 0 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg R: Extra2Reg. - currentBlock := self Label. - jump8 jmpTarget: currentBlock. - jump7 jmpTarget: currentBlock. - self MoveMw: 24 r: SPReg R: Extra3Reg. - self MoveMw: 8 r: SPReg R: Extra4Reg. - self SubR: Extra4Reg R: Extra3Reg. - self MoveR: Extra3Reg Mw: 24 r: SPReg. - self MoveMw: 16 r: SPReg R: Extra3Reg. - self CmpCq: 24 R: Extra3Reg. - jump7 := self JumpBelow: 0. - self MoveR: Extra2Reg R: ReceiverResultReg. - jump8 := self Jump: 0. + jump6 jmpTarget: currentBlock. + self MoveM64: 24 r: ClassReg R: Extra0Reg. + self ArithmeticShiftRightCq: 3 R: Extra0Reg. + self AndCq: 16rFFFF R: Extra0Reg. + self MoveR: Extra0Reg R: SendNumArgsReg. + self MoveR: Extra2Reg R: ClassReg. currentBlock := self Label. jump7 jmpTarget: currentBlock. - self CmpCq: 1 R: SendNumArgsReg. + jump9 jmpTarget: currentBlock. + self SubR: SendNumArgsReg R: ClassReg. + self CmpCq: 24 R: Extra1Reg. + jump9 := self JumpAboveOrEqual: 0. + self MoveMw: 8 r: SPReg R: Extra3Reg. + self CmpCq: 1 R: Extra3Reg. jump7 := self JumpBelow: 0. - self MoveMw: 24 r: SPReg R: Extra3Reg. - self CmpR: Extra3Reg R: SendNumArgsReg. + self MoveMw: 8 r: SPReg R: Extra3Reg. + self CmpR: ClassReg R: Extra3Reg. + jump6 := self JumpAbove: 0. + self MoveMw: 8 r: SPReg R: Extra3Reg. + self AddR: SendNumArgsReg R: Extra3Reg. + self MoveR: Extra3Reg Mw: 8 r: SPReg. + self CmpCq: 5 R: Extra1Reg. jump5 := self JumpAbove: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. - self AddR: Extra3Reg R: SendNumArgsReg. - self MoveMw: 16 r: SPReg R: Extra3Reg. - self CmpCq: 5 R: Extra3Reg. - jump4 := self JumpAbove: 0. - self SubCq: 1 R: SendNumArgsReg. - self MoveR: ClassReg R: Extra2Reg. - self AndCq: 7 R: Extra2Reg. - self CmpCq: 0 R: Extra2Reg. - jump9 := self JumpNonZero: 0. - s146 := objectMemory getMemoryMap getSpaceMaskToUse. - self MoveR: ClassReg R: Extra2Reg. - self AndCq: s146 R: Extra2Reg. - s149 := objectMemory getMemoryMap getOldSpaceMask. - self CmpCq: s149 R: Extra2Reg. - jump6 := self JumpNonZero: 0. - self MoveR: Extra1Reg R: Extra2Reg. - self AndCq: 7 R: Extra2Reg. - self CmpCq: 0 R: Extra2Reg. + self SubCq: 1 R: Extra3Reg. + self MoveR: Extra3Reg Mw: 8 r: SPReg. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveR: Extra3Reg R: Extra0Reg. + self AndCq: 7 R: Extra0Reg. + self CmpCq: 0 R: Extra0Reg. jump10 := self JumpNonZero: 0. - s154 := objectMemory getMemoryMap getSpaceMaskToUse. - self MoveR: Extra1Reg R: Extra2Reg. - self AndCq: s154 R: Extra2Reg. - s157 := objectMemory getMemoryMap getNewSpaceMask. - self CmpCq: s157 R: Extra2Reg. + s131 := objectMemory getMemoryMap getSpaceMaskToUse. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveR: Extra3Reg R: Extra0Reg. + self AndCq: s131 R: Extra0Reg. + s134 := objectMemory getMemoryMap getOldSpaceMask. + self CmpCq: s134 R: Extra0Reg. + jump8 := self JumpNonZero: 0. + self MoveMw: 16 r: SPReg R: Extra3Reg. + self MoveR: Extra3Reg R: Extra0Reg. + self AndCq: 7 R: Extra0Reg. + self CmpCq: 0 R: Extra0Reg. jump11 := self JumpNonZero: 0. - s159 := objectMemory getMemoryMap getNewSpaceStart. - self MoveR: Extra1Reg R: Extra2Reg. - self CmpCq: s159 R: Extra2Reg. + s139 := objectMemory getMemoryMap getSpaceMaskToUse. + self MoveMw: 16 r: SPReg R: Extra3Reg. + self MoveR: Extra3Reg R: Extra0Reg. + self AndCq: s139 R: Extra0Reg. + s142 := objectMemory getMemoryMap getNewSpaceMask. + self CmpCq: s142 R: Extra0Reg. + jump12 := self JumpNonZero: 0. + s144 := objectMemory getMemoryMap getNewSpaceStart. + self MoveMw: 16 r: SPReg R: Extra3Reg. + self MoveR: Extra3Reg R: Extra0Reg. + self CmpCq: s144 R: Extra0Reg. jumpTrue := self JumpAboveOrEqual: 0. - self MoveCq: 0 R: Extra2Reg. + self MoveCq: 0 R: Extra0Reg. jumpNext := self Jump: 0. jumpTrue jmpTarget: self Label. - self MoveCq: 1 R: Extra2Reg. + self MoveCq: 1 R: Extra0Reg. jumpNext jmpTarget: self Label. - self CmpCq: 1 R: Extra2Reg. - jump12 := self JumpNonZero: 0. - self MoveM64: 0 r: ClassReg R: Extra2Reg. - self LogicalShiftRightCq: 29 R: Extra2Reg. - self AndCq: 1 R: Extra2Reg. - self CmpCq: 0 R: Extra2Reg. + self CmpCq: 1 R: Extra0Reg. jump13 := self JumpNonZero: 0. - self MoveR: ClassReg R: TempReg. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveM64: 0 r: Extra3Reg R: Extra0Reg. + self LogicalShiftRightCq: 29 R: Extra0Reg. + self AndCq: 1 R: Extra0Reg. + self CmpCq: 0 R: Extra0Reg. + jump14 := self JumpNonZero: 0. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveR: Extra3Reg R: TempReg. backEnd saveAndRestoreLinkRegAround: [ self CallRT: ceStoreCheckTrampoline ]. - jump14 := self Jump: 0. + jump15 := self Jump: 0. currentBlock := self Label. - jump11 jmpTarget: currentBlock. + jump12 jmpTarget: currentBlock. currentBlock := self Label. - jump9 jmpTarget: currentBlock. - jump6 jmpTarget: currentBlock. jump10 jmpTarget: currentBlock. - jump12 jmpTarget: currentBlock. + jump8 jmpTarget: currentBlock. + jump11 jmpTarget: currentBlock. jump13 jmpTarget: currentBlock. jump14 jmpTarget: currentBlock. - self MoveM64: 0 r: ClassReg R: Extra2Reg. - self LogicalShiftRightCq: 29 R: Extra2Reg. - self AndCq: 1 R: Extra2Reg. - self CmpCq: 0 R: Extra2Reg. + jump15 jmpTarget: currentBlock. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveM64: 0 r: Extra3Reg R: Extra0Reg. + self LogicalShiftRightCq: 29 R: Extra0Reg. + self AndCq: 1 R: Extra0Reg. + self CmpCq: 0 R: Extra0Reg. + jump15 := self JumpNonZero: 0. + self MoveMw: 16 r: SPReg R: Extra3Reg. + self TstCq: 7 R: Extra3Reg. jump14 := self JumpNonZero: 0. - self TstCq: 7 R: Extra1Reg. - jump13 := self JumpNonZero: 0. - self CmpCq: 16r20000000000 R: ClassReg. - jump12 := self JumpBelow: 0. - self CmpCq: 16r20000000000 R: Extra1Reg. - jump10 := self JumpGreaterOrEqual: 0. - self genMoveConstant: objectMemory nilObject R: Extra2Reg. - self CmpR: Extra2Reg R: Extra1Reg. - jump6 := self JumpBelow: 0. - s181 := objectMemory trueObject. - self CmpCq: s181 R: Extra1Reg. - jump9 := self JumpBelowOrEqual: 0. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self CmpCq: 16r20000000000 R: Extra3Reg. + jump13 := self JumpBelow: 0. + self MoveMw: 16 r: SPReg R: Extra3Reg. + self CmpCq: 16r20000000000 R: Extra3Reg. + jump11 := self JumpAboveOrEqual: 0. + self genMoveConstant: objectMemory nilObject R: Extra0Reg. + self MoveMw: 16 r: SPReg R: Extra3Reg. + self CmpR: Extra0Reg R: Extra3Reg. + jump8 := self JumpBelow: 0. + s166 := objectMemory trueObject. + self MoveMw: 16 r: SPReg R: Extra3Reg. + self CmpCq: s166 R: Extra3Reg. + jump10 := self JumpBelowOrEqual: 0. currentBlock := self Label. - jump6 jmpTarget: currentBlock. - s183 := objectMemory getMemoryMap getNewSpaceStart. - self CmpCq: s183 R: Extra1Reg. - jump6 := self JumpBelow: 0. - self MoveR: ClassReg R: TempReg. + jump8 jmpTarget: currentBlock. + s168 := objectMemory getMemoryMap getNewSpaceStart. + self MoveMw: 16 r: SPReg R: Extra3Reg. + self CmpCq: s168 R: Extra3Reg. + jump8 := self JumpBelow: 0. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveR: Extra3Reg R: TempReg. backEnd saveAndRestoreLinkRegAround: [ self CallRT: ceStoreCheckTrampoline ]. currentBlock := self Label. + jump15 jmpTarget: currentBlock. jump14 jmpTarget: currentBlock. jump13 jmpTarget: currentBlock. - jump12 jmpTarget: currentBlock. + jump11 jmpTarget: currentBlock. jump10 jmpTarget: currentBlock. - jump9 jmpTarget: currentBlock. - jump6 jmpTarget: currentBlock. - self LogicalShiftLeftCq: 3 R: SendNumArgsReg. - self AddR: SendNumArgsReg R: ClassReg. - self MoveR: Extra1Reg M64: 8 r: ClassReg. - s190 := 0. - self MoveCq: s190 R: Extra2Reg. - jump6 := self Jump: 0. - currentBlock := self Label. - jump4 jmpTarget: currentBlock. + jump8 jmpTarget: currentBlock. + self MoveMw: 8 r: SPReg R: Extra3Reg. + self LogicalShiftLeftCq: 3 R: Extra3Reg. + self MoveR: Extra3Reg Mw: 8 r: SPReg. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveMw: 8 r: SPReg R: Extra4Reg. + self AddR: Extra4Reg R: Extra3Reg. + self MoveR: Extra3Reg Mw: 0 r: SPReg. self MoveMw: 16 r: SPReg R: Extra3Reg. - self CmpCq: 16 R: Extra3Reg. - jump4 := self JumpBelow: 0. - self TstCq: 1 R: Extra1Reg. - jump9 := self JumpZero: 0. - self ArithmeticShiftRightCq: 3 R: Extra1Reg. - self CmpCq: 0 R: Extra1Reg. - jump10 := self JumpLess: 0. - self CmpCq: 255 R: Extra1Reg. - jump12 := self JumpGreater: 0. - self AddR: ClassReg R: SendNumArgsReg. - self AddCq: -1 R: SendNumArgsReg. - self MoveR: Extra1Reg Mb: 8 r: SendNumArgsReg. - s202 := 0. - self MoveCq: s202 R: Extra2Reg. - jump13 := self Jump: 0. - currentBlock := self Label. - jump10 jmpTarget: currentBlock. - jump12 jmpTarget: currentBlock. - s206 := 3. - self MoveCq: s206 R: Extra2Reg. - jump12 := self Jump: 0. - currentBlock := self Label. - jump9 jmpTarget: currentBlock. - s210 := 3. - self MoveCq: s210 R: Extra2Reg. - currentBlock := self Label. - jump6 jmpTarget: currentBlock. - jump13 jmpTarget: currentBlock. - jump12 jmpTarget: currentBlock. - jump12 := self Jump: 0. + self MoveMw: 0 r: SPReg R: Extra4Reg. + self MoveR: Extra3Reg M64: 8 r: Extra4Reg. + jump8 := self Jump: 0. currentBlock := self Label. - jump4 jmpTarget: currentBlock. + jump5 jmpTarget: currentBlock. + self CmpCq: 16 R: Extra1Reg. + jump5 := self JumpBelow: 0. self MoveMw: 16 r: SPReg R: Extra3Reg. - self CmpCq: 12 R: Extra3Reg. - jump4 := self JumpBelow: 0. - self TstCq: 1 R: Extra1Reg. - jump13 := self JumpZero: 0. - self ArithmeticShiftRightCq: 3 R: Extra1Reg. - self CmpCq: 0 R: Extra1Reg. - jump6 := self JumpLess: 0. - self CmpCq: 16rFFFF R: Extra1Reg. - jump9 := self JumpGreater: 0. - self SubCq: 1 R: SendNumArgsReg. - self LogicalShiftLeftCq: 1 R: SendNumArgsReg. - self AddR: SendNumArgsReg R: ClassReg. - self MoveR: ClassReg R: Extra2Reg. - self AddCq: 8 R: Extra2Reg. - self MoveR: Extra2Reg R: SendNumArgsReg. - self AndCq: 2 R: SendNumArgsReg. - self CmpCq: 0 R: SendNumArgsReg. - jump10 := self JumpNonZero: 0. - self MoveM32: 8 r: ClassReg R: SendNumArgsReg. - self AndCq: 16rFFFFFFFF R: SendNumArgsReg. - self AndCq: 16rFFFF0000 R: SendNumArgsReg. - self OrR: Extra1Reg R: SendNumArgsReg. - self MoveR: SendNumArgsReg M32: 8 r: ClassReg. - jump14 := self Jump: 0. - currentBlock := self Label. - jump10 jmpTarget: currentBlock. - self MoveM32: -2 r: Extra2Reg R: SendNumArgsReg. - self AndCq: 16rFFFFFFFF R: SendNumArgsReg. - self AndCq: 16rFFFF R: SendNumArgsReg. - self LogicalShiftLeftCq: 16 R: Extra1Reg. - self OrR: Extra1Reg R: SendNumArgsReg. - self MoveR: SendNumArgsReg M32: -2 r: Extra2Reg. - currentBlock := self Label. - jump14 jmpTarget: currentBlock. - self MoveR: Extra0Reg R: SendNumArgsReg. - s246 := 0. - self MoveCq: s246 R: Extra2Reg. - self MoveR: SendNumArgsReg R: Extra0Reg. - currentBlock := self Label. - jump12 jmpTarget: currentBlock. - self CmpCq: 0 R: Extra2Reg. - jump12 := self JumpNonZero: 0. - self MoveR: Extra2Reg R: SendNumArgsReg. - self MoveR: Extra2Reg R: ReceiverResultReg. - self CmpCq: 0 R: SendNumArgsReg. - jump14 := self JumpZero: 0. - jump10 := self JumpNonZero: 0. - currentBlock := self Label. - jump12 jmpTarget: currentBlock. - jump12 := self Jump: 0. + self TstCq: 1 R: Extra3Reg. + jump10 := self JumpZero: 0. + self MoveMw: 16 r: SPReg R: Extra3Reg. + self MoveR: Extra3Reg R: Extra0Reg. + self ArithmeticShiftRightCq: 3 R: Extra0Reg. + self CmpCq: 0 R: Extra0Reg. + jump11 := self JumpBelow: 0. + self CmpCq: 255 R: Extra0Reg. + jump13 := self JumpAbove: 0. + self MoveMw: 8 r: SPReg R: Extra3Reg. + self MoveMw: 0 r: SPReg R: Extra4Reg. + self AddR: Extra4Reg R: Extra3Reg. + self MoveR: Extra3Reg Mw: 8 r: SPReg. + self MoveMw: 8 r: SPReg R: Extra3Reg. + self AddCq: -1 R: Extra3Reg. + self MoveR: Extra3Reg Mw: 8 r: SPReg. + self MoveMw: 8 r: SPReg R: Extra3Reg. + self MoveR: Extra0Reg Mb: 8 r: Extra3Reg. + jump14 := self Jump: 0. currentBlock := self Label. - jump6 jmpTarget: currentBlock. - jump9 jmpTarget: currentBlock. - s263 := 3. - self MoveCq: s263 R: Extra2Reg. + jump5 jmpTarget: currentBlock. + self CmpCq: 12 R: Extra1Reg. + jump5 := self JumpBelow: 0. + self MoveMw: 16 r: SPReg R: Extra3Reg. + self TstCq: 1 R: Extra3Reg. + jump15 := self JumpZero: 0. + self MoveMw: 16 r: SPReg R: Extra3Reg. + self MoveR: Extra3Reg R: Extra0Reg. + self ArithmeticShiftRightCq: 3 R: Extra0Reg. + self CmpCq: 0 R: Extra0Reg. + jump12 := self JumpBelow: 0. + self CmpCq: 16rFFFF R: Extra0Reg. + jump16 := self JumpAbove: 0. + self MoveMw: 8 r: SPReg R: Extra3Reg. + self SubCq: 1 R: Extra3Reg. + self MoveR: Extra3Reg Mw: 8 r: SPReg. + self MoveMw: 8 r: SPReg R: Extra3Reg. + self LogicalShiftLeftCq: 1 R: Extra3Reg. + self MoveR: Extra3Reg Mw: 8 r: SPReg. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveMw: 8 r: SPReg R: Extra4Reg. + self AddR: Extra4Reg R: Extra3Reg. + self MoveR: Extra3Reg Mw: 0 r: SPReg. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveR: Extra3Reg R: Extra2Reg. + self AddCq: 8 R: Extra2Reg. + self MoveR: Extra2Reg R: Extra1Reg. + self AndCq: 2 R: Extra1Reg. + self CmpCq: 0 R: Extra1Reg. + jump17 := self JumpNonZero: 0. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveM32: 8 r: Extra3Reg R: Extra1Reg. + self AndCq: 16rFFFFFFFF R: Extra1Reg. + self AndCq: 16rFFFF0000 R: Extra1Reg. + self OrR: Extra0Reg R: Extra1Reg. + self MoveMw: 0 r: SPReg R: Extra3Reg. + self MoveR: Extra1Reg M32: 8 r: Extra3Reg. + jump18 := self Jump: 0. currentBlock := self Label. - jump12 jmpTarget: currentBlock. - self MoveR: Extra0Reg R: ReceiverResultReg. - self CmpCq: 0 R: Extra2Reg. - jump12 := self JumpNonZero: 0. + jump17 jmpTarget: currentBlock. + self MoveM32: -2 r: Extra2Reg R: Extra1Reg. + self AndCq: 16rFFFFFFFF R: Extra1Reg. + self AndCq: 16rFFFF R: Extra1Reg. + self LogicalShiftLeftCq: 16 R: Extra0Reg. + self OrR: Extra0Reg R: Extra1Reg. + self MoveR: Extra1Reg M32: -2 r: Extra2Reg. currentBlock := self Label. + jump8 jmpTarget: currentBlock. jump14 jmpTarget: currentBlock. - self AddCq: 48 R: SPReg. - self genPrimReturn. - currentBlock := self Label. - jump13 jmpTarget: currentBlock. - self MoveR: Extra0Reg R: ReceiverResultReg. - jump13 := self Jump: 0. - currentBlock := self Label. - jump4 jmpTarget: currentBlock. + jump18 jmpTarget: currentBlock. self MoveMw: 16 r: SPReg R: Extra3Reg. - self CmpCq: 9 R: Extra3Reg. - jump4 := self JumpNonZero: 0. - self MoveR: Extra2Reg R: ReceiverResultReg. - jump14 := self Jump: 0. - currentBlock := self Label. - jump4 jmpTarget: currentBlock. - self MoveR: Extra2Reg R: ReceiverResultReg. - jump4 := self Jump: 0. - currentBlock := self Label. - jump7 jmpTarget: currentBlock. - jump5 jmpTarget: currentBlock. - self MoveR: Extra2Reg R: ReceiverResultReg. + self MoveR: Extra3Reg R: ReceiverResultReg. + self AddCq: 24 R: SPReg. + self genPrimReturn. currentBlock := self Label. jump1 jmpTarget: currentBlock. - jump3 jmpTarget: currentBlock. jump2 jmpTarget: currentBlock. - jump8 jmpTarget: currentBlock. + jump3 jmpTarget: currentBlock. + jump4 jmpTarget: currentBlock. + jump9 jmpTarget: currentBlock. + jump7 jmpTarget: currentBlock. + jump6 jmpTarget: currentBlock. jump10 jmpTarget: currentBlock. - jump12 jmpTarget: currentBlock. + jump11 jmpTarget: currentBlock. jump13 jmpTarget: currentBlock. - jump14 jmpTarget: currentBlock. - jump4 jmpTarget: currentBlock. - self AddCq: 48 R: SPReg. + jump5 jmpTarget: currentBlock. + jump15 jmpTarget: currentBlock. + jump12 jmpTarget: currentBlock. + jump16 jmpTarget: currentBlock. + self AddCq: 24 R: SPReg. ^ 0 ] @@ -2719,7 +2659,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveBitAnd [ | jump1 currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArgAtDepth: 0 into: SendNumArgsReg. self MoveR: SendNumArgsReg R: Extra0Reg. self AndR: ClassReg R: Extra0Reg. self TstCq: 1 R: Extra0Reg. @@ -3022,7 +2962,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveClass [ s56 := self methodNumArgs. s56 = 1 ifTrue: [ | jump5 jump3 jump1 jump6 jump4 jump2 | - self genLoadArg: 0 into: Extra0Reg. + self genLoadArgAtDepth: 0 into: Extra0Reg. self MoveR: Extra0Reg R: ClassReg. self AndCq: 7 R: ClassReg. self CmpCq: 0 R: ClassReg. @@ -3312,9 +3252,9 @@ SimpleDruidTestRTLCompiler >> gen_primitiveDivide [ self DivR: SendNumArgsReg R: ClassReg - Quo: SendNumArgsReg - Rem: ClassReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. + Quo: ClassReg + Rem: SendNumArgsReg. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -3592,7 +3532,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatAdd [ | jump1 s89 jumpNext jump9 jump6 jump3 currentBlock jump8 jump5 jump2 s121 jumpTrue s118 s93 jump7 jump4 | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArgAtDepth: 0 into: SendNumArgsReg. self MoveR: ClassReg R: Extra0Reg. self AndCq: 7 R: Extra0Reg. self CmpCq: 0 R: Extra0Reg. @@ -3791,7 +3731,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatEqual [ | jump1 jump6 jump3 currentBlock s82 jump8 jump5 s79 jump2 jump7 jump4 | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArgAtDepth: 0 into: SendNumArgsReg. self MoveR: ClassReg R: Extra0Reg. self AndCq: 7 R: Extra0Reg. self CmpCq: 0 R: Extra0Reg. @@ -3909,7 +3849,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatMultiply [ | jump1 s89 jumpNext jump9 jump6 jump3 currentBlock jump8 jump5 jump2 s121 jumpTrue s118 s93 jump7 jump4 | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArgAtDepth: 0 into: SendNumArgsReg. self MoveR: ClassReg R: Extra0Reg. self AndCq: 7 R: Extra0Reg. self CmpCq: 0 R: Extra0Reg. @@ -4092,7 +4032,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatNotEqual [ | jump1 jump6 jump3 currentBlock s82 jump8 jump5 s79 jump2 jump7 jump4 | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArgAtDepth: 0 into: SendNumArgsReg. self MoveR: ClassReg R: Extra0Reg. self AndCq: 7 R: Extra0Reg. self CmpCq: 0 R: Extra0Reg. @@ -4210,7 +4150,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatSubtract [ | jump1 s89 jumpNext jump9 jump6 jump3 currentBlock jump8 jump5 jump2 s121 jumpTrue s118 s93 jump7 jump4 | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArgAtDepth: 0 into: SendNumArgsReg. self MoveR: ClassReg R: Extra0Reg. self AndCq: 7 R: Extra0Reg. self CmpCq: 0 R: Extra0Reg. @@ -4428,7 +4368,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFullClosureValue [ s22 = 1 ifTrue: [ | jump4 jump3 jump2 jump1 | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArgAtDepth: 0 into: SendNumArgsReg. self MoveM64: 24 r: ClassReg R: SendNumArgsReg. self ArithmeticShiftRightCq: 3 R: SendNumArgsReg. self CmpCq: 1 R: SendNumArgsReg. @@ -4461,8 +4401,8 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFullClosureValue [ s43 = 2 ifTrue: [ | jump1 jump2 jump3 jump4 | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. - self genLoadArg: 1 into: SendNumArgsReg. + self genLoadArgAtDepth: 0 into: SendNumArgsReg. + self genLoadArgAtDepth: 1 into: SendNumArgsReg. self MoveM64: 24 r: ClassReg R: SendNumArgsReg. self ArithmeticShiftRightCq: 3 R: SendNumArgsReg. self CmpCq: 2 R: SendNumArgsReg. @@ -4898,7 +4838,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveImmediateAsInteger [ s40 := self methodNumArgs. s40 = 1 ifTrue: [ | jump5 jump3 jump1 jump4 jump2 | - self genLoadArg: 0 into: ClassReg. + self genLoadArgAtDepth: 0 into: ClassReg. self TstCq: 1 R: ClassReg. jump1 := self JumpZero: 0. self ArithmeticShiftRightCq: 3 R: ClassReg. @@ -5051,9 +4991,9 @@ SimpleDruidTestRTLCompiler >> gen_primitiveIntegerDivide [ self DivR: SendNumArgsReg R: ClassReg - Quo: SendNumArgsReg - Rem: ClassReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. + Quo: ClassReg + Rem: SendNumArgsReg. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -5069,9 +5009,9 @@ SimpleDruidTestRTLCompiler >> gen_primitiveIntegerDivideByConstant [ self DivR: SendNumArgsReg R: ClassReg - Quo: ClassReg - Rem: SendNumArgsReg. - self MoveR: ClassReg R: ReceiverResultReg. + Quo: SendNumArgsReg + Rem: ClassReg. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -5668,11 +5608,11 @@ SimpleDruidTestRTLCompiler >> gen_primitiveNew [ SimpleDruidTestRTLCompiler >> gen_primitiveNewWithArg [ "AutoGenerated by Druid" - | jump5 s105 jump10 s64 jump3 s14 jump8 s182 jump1 currentBlock jump13 s90 jump6 s171 s47 jump11 jump4 b944 s87 jump9 jump2 s102 s59 s52 jump7 jump12 s66 | + | jump5 jump10 s94 s55 jump3 b690 jump8 jump1 s36 currentBlock s101 s58 jump13 jump6 s73 s82 s47 jump11 jump4 s78 s168 jump9 jump2 s85 s157 s98 jump7 jump12 | self SubCq: 32 R: SPReg. self MoveR: ReceiverResultReg R: Extra3Reg. self MoveR: Extra3Reg Mw: 0 r: SPReg. - self genLoadArgAtDepth: 0 into: SendNumArgsReg. + self genLoadArgAtDepth: 4 into: SendNumArgsReg. self TstCq: 1 R: SendNumArgsReg. jump1 := self JumpZero: 0. self ArithmeticShiftRightCq: 3 R: SendNumArgsReg. @@ -5685,13 +5625,16 @@ SimpleDruidTestRTLCompiler >> gen_primitiveNewWithArg [ self LogicalShiftRightCq: 16 R: Extra1Reg. self AndCq: 31 R: Extra1Reg. self MoveMw: 0 r: SPReg R: Extra3Reg. - self MoveM32: 4 r: Extra3Reg R: Extra2Reg. - self AndCq: 16rFFFFFFFF R: Extra2Reg. - self AndCq: 16r3FFFFF R: Extra2Reg. - s14 := 0. + self MoveM32: 4 r: Extra3Reg R: Extra3Reg. + self AndCq: 16rFFFFFFFF R: Extra3Reg. + self MoveR: Extra3Reg Mw: 8 r: SPReg. + self MoveMw: 8 r: SPReg R: Extra3Reg. + self AndCq: 16r3FFFFF R: Extra3Reg. + self MoveR: Extra3Reg Mw: 8 r: SPReg. self CmpCq: 2 R: Extra1Reg. jump3 := self JumpNonZero: 0. self genMoveConstant: objectMemory nilObject R: Extra0Reg. + self MoveR: Extra0Reg R: ClassReg. jump4 := self Jump: 0. currentBlock := self Label. jump3 jmpTarget: currentBlock. @@ -5701,7 +5644,6 @@ SimpleDruidTestRTLCompiler >> gen_primitiveNewWithArg [ self AddR: SendNumArgsReg R: Extra0Reg. self genMoveConstant: objectMemory nilObject R: ClassReg. self MoveR: Extra0Reg R: SendNumArgsReg. - self MoveR: ClassReg R: Extra0Reg. jump5 := self Jump: 0. currentBlock := self Label. jump3 jmpTarget: currentBlock. @@ -5711,19 +5653,20 @@ SimpleDruidTestRTLCompiler >> gen_primitiveNewWithArg [ self AddR: SendNumArgsReg R: Extra0Reg. self genMoveConstant: objectMemory nilObject R: ClassReg. self MoveR: Extra0Reg R: SendNumArgsReg. - self MoveR: ClassReg R: Extra0Reg. jump6 := self Jump: 0. currentBlock := self Label. jump3 jmpTarget: currentBlock. + s36 := 0. self CmpCq: 9 R: Extra1Reg. jump3 := self JumpNonZero: 0. - self MoveCq: s14 R: Extra0Reg. + self MoveCq: s36 R: ClassReg. jump7 := self Jump: 0. currentBlock := self Label. jump3 jmpTarget: currentBlock. self CmpCq: 10 R: Extra1Reg. jump3 := self JumpNonZero: 0. - self CmpCq: 34 R: Extra2Reg. + self MoveMw: 8 r: SPReg R: Extra3Reg. + self CmpCq: 34 R: Extra3Reg. jump8 := self JumpNonZero: 0. self CmpCq: 2 R: SendNumArgsReg. jump9 := self JumpNonZero: 0. @@ -5738,95 +5681,88 @@ SimpleDruidTestRTLCompiler >> gen_primitiveNewWithArg [ Rem: Extra0Reg. self AndCq: 1 R: SendNumArgsReg. self AddR: SendNumArgsReg R: Extra1Reg. - s52 := 0. - self MoveCq: s52 R: Extra0Reg. jump10 := self Jump: 0. currentBlock := self Label. jump8 jmpTarget: currentBlock. - self MoveR: SendNumArgsReg R: Extra0Reg. - self AddCq: 1 R: Extra0Reg. - s59 := 2. - self MoveCq: s59 R: ClassReg. + s55 := 0. + self MoveR: SendNumArgsReg R: ClassReg. + self AddCq: 1 R: ClassReg. + s58 := 2. + self MoveCq: s58 R: Extra0Reg. self - DivR: ClassReg - R: Extra0Reg - Quo: ClassReg - Rem: Extra0Reg. + DivR: Extra0Reg + R: ClassReg + Quo: Extra0Reg + Rem: ClassReg. self AndCq: 1 R: SendNumArgsReg. self AddR: SendNumArgsReg R: Extra1Reg. - s64 := 0. - self CmpCq: 0 R: Extra2Reg. + self MoveMw: 8 r: SPReg R: Extra3Reg. + self CmpCq: 0 R: Extra3Reg. jump8 := self JumpNonZero: 0. - s66 := s64. - self MoveR: Extra1Reg R: Extra0Reg. - self MoveR: Extra0Reg R: Extra1Reg. - self MoveCq: s66 R: Extra0Reg. + self MoveCq: s55 R: ClassReg. jump11 := self Jump: 0. currentBlock := self Label. jump8 jmpTarget: currentBlock. - self MoveCq: s64 R: Extra0Reg. + self MoveR: Extra0Reg R: ClassReg. currentBlock := self Label. jump10 jmpTarget: currentBlock. + s73 := 0. + self MoveCq: s73 R: Extra0Reg. jump10 := self Jump: 0. currentBlock := self Label. jump3 jmpTarget: currentBlock. + s78 := 0. self CmpCq: 12 R: Extra1Reg. jump3 := self JumpNonZero: 0. - self MoveR: SendNumArgsReg R: Extra0Reg. - self AddCq: 3 R: Extra0Reg. - s87 := 4. - self MoveCq: s87 R: ClassReg. + self MoveR: SendNumArgsReg R: ClassReg. + self AddCq: 3 R: ClassReg. + s82 := 4. + self MoveCq: s82 R: Extra0Reg. self - DivR: ClassReg - R: Extra0Reg - Quo: ClassReg + DivR: Extra0Reg + R: ClassReg + Quo: Extra2Reg Rem: Extra0Reg. - s90 := 4. - self MoveCq: s90 R: Extra0Reg. + s85 := 4. + self MoveCq: s85 R: Extra0Reg. self SubR: SendNumArgsReg R: Extra0Reg. self AndCq: 3 R: Extra0Reg. self AddR: Extra0Reg R: Extra1Reg. - self MoveR: ClassReg R: SendNumArgsReg. - self MoveCq: s14 R: Extra0Reg. + self MoveCq: s78 R: ClassReg. + self MoveR: Extra2Reg R: SendNumArgsReg. jump8 := self Jump: 0. currentBlock := self Label. jump3 jmpTarget: currentBlock. + s94 := 0. self CmpCq: 16 R: Extra1Reg. jump3 := self JumpNonZero: 0. self MoveR: SendNumArgsReg R: Extra0Reg. self AddCq: 7 R: Extra0Reg. - s102 := 8. - self MoveCq: s102 R: ClassReg. + s98 := 8. + self MoveCq: s98 R: Extra2Reg. self - DivR: ClassReg + DivR: Extra2Reg R: Extra0Reg Quo: Extra0Reg - Rem: ClassReg. - s105 := 8. - self MoveCq: s105 R: ClassReg. - self SubR: SendNumArgsReg R: ClassReg. - self AndCq: 7 R: ClassReg. - self AddR: ClassReg R: Extra1Reg. + Rem: Extra2Reg. + s101 := 8. + self MoveCq: s101 R: Extra2Reg. + self SubR: SendNumArgsReg R: Extra2Reg. + self AndCq: 7 R: Extra2Reg. + self AddR: Extra2Reg R: Extra1Reg. + self MoveCq: s94 R: ClassReg. self MoveR: Extra0Reg R: SendNumArgsReg. - self MoveCq: s14 R: Extra0Reg. jump12 := self Jump: 0. currentBlock := self Label. jump3 jmpTarget: currentBlock. self CmpCq: 0 R: SendNumArgsReg. jump3 := self JumpNonZero: 0. self CmpCq: 5 R: Extra1Reg. - jump13 := self JumpBelowOrEqual: 0. - currentBlock := self Label. - jump3 jmpTarget: currentBlock. - self MoveMw: 0 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg R: ClassReg. - jump3 := self Jump: 0. - currentBlock := self Label. - jump13 jmpTarget: currentBlock. + jump13 := self JumpAbove: 0. self AndCq: 16rFFFF R: Extra0Reg. - self genMoveConstant: objectMemory nilObject R: ClassReg. + self genMoveConstant: objectMemory nilObject R: Extra2Reg. + self MoveR: Extra2Reg R: ClassReg. self MoveR: Extra0Reg R: SendNumArgsReg. - self MoveR: ClassReg R: Extra0Reg. currentBlock := self Label. jump4 jmpTarget: currentBlock. jump5 jmpTarget: currentBlock. @@ -5834,9 +5770,10 @@ SimpleDruidTestRTLCompiler >> gen_primitiveNewWithArg [ jump7 jmpTarget: currentBlock. jump8 jmpTarget: currentBlock. jump12 jmpTarget: currentBlock. - self CmpCq: 0 R: Extra2Reg. + self MoveMw: 8 r: SPReg R: Extra3Reg. + self CmpCq: 0 R: Extra3Reg. jump12 := self JumpNonZero: 0. - self MoveR: SendNumArgsReg R: ClassReg. + self MoveR: SendNumArgsReg R: Extra0Reg. currentBlock := self Label. jump11 jmpTarget: currentBlock. self MoveMw: 0 r: SPReg R: Extra3Reg. @@ -5848,142 +5785,100 @@ SimpleDruidTestRTLCompiler >> gen_primitiveNewWithArg [ self CmpCq: 0 R: Extra2Reg. jump8 := self JumpBelow: 0. self MoveR: ClassReg R: Extra3Reg. - self MoveR: Extra3Reg Mw: 8 r: SPReg. - self MoveR: Extra1Reg R: Extra3Reg. self MoveR: Extra3Reg Mw: 16 r: SPReg. self MoveR: Extra0Reg R: Extra3Reg. self MoveR: Extra3Reg Mw: 24 r: SPReg. jump7 := self Jump: 0. currentBlock := self Label. jump12 jmpTarget: currentBlock. + self MoveR: ClassReg R: Extra0Reg. self MoveR: SendNumArgsReg R: ClassReg. currentBlock := self Label. jump10 jmpTarget: currentBlock. - self MoveR: ClassReg R: Extra3Reg. - self MoveR: Extra3Reg Mw: 8 r: SPReg. - self MoveR: Extra1Reg R: Extra3Reg. - self MoveR: Extra3Reg Mw: 16 r: SPReg. self MoveR: Extra0Reg R: Extra3Reg. + self MoveR: Extra3Reg Mw: 16 r: SPReg. + self MoveR: ClassReg R: Extra3Reg. self MoveR: Extra3Reg Mw: 24 r: SPReg. - currentBlock := self Label. - jump7 jmpTarget: currentBlock. - self MoveMw: 0 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg R: SendNumArgsReg. - self MoveMw: 8 r: SPReg R: Extra3Reg. - self CmpCq: 16rFFFF R: Extra3Reg. - jump7 := self JumpBelowOrEqual: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. - self CmpCq: 16r10000000000 R: Extra3Reg. - jump10 := self JumpBelowOrEqual: 0. - self MoveR: SendNumArgsReg R: ReceiverResultReg. - jump12 := self Jump: 0. - currentBlock := self Label. - jump10 jmpTarget: currentBlock. - self MoveR: SendNumArgsReg R: ReceiverResultReg. - jump10 := self Jump: 0. + self MoveR: Extra3Reg R: Extra2Reg. currentBlock := self Label. jump7 jmpTarget: currentBlock. - self MoveMw: 8 r: SPReg R: Extra3Reg. + self MoveMw: 24 r: SPReg R: Extra3Reg. + self CmpCq: 16rFFFF R: Extra3Reg. + jump7 := self JumpAbove: 0. + self MoveMw: 24 r: SPReg R: Extra3Reg. self CmpCq: 255 R: Extra3Reg. - jump7 := self JumpBelow: 0. - self MoveR: SendNumArgsReg R: ReceiverResultReg. - jump6 := self Jump: 0. - currentBlock := self Label. - jump7 jmpTarget: currentBlock. - self MoveMw: 8 r: SPReg R: Extra3Reg. + jump10 := self JumpAboveOrEqual: 0. + self MoveMw: 24 r: SPReg R: Extra3Reg. self CmpCq: 1 R: Extra3Reg. - jump7 := self JumpAboveOrEqual: 0. - s171 := 8. - self MoveCq: s171 R: ClassReg. - jump5 := self Jump: 0. + jump12 := self JumpAboveOrEqual: 0. + s157 := 8. + self MoveCq: s157 R: ClassReg. + jump6 := self Jump: 0. currentBlock := self Label. - jump7 jmpTarget: currentBlock. - self MoveMw: 8 r: SPReg R: Extra3Reg. + jump12 jmpTarget: currentBlock. + self MoveMw: 24 r: SPReg R: Extra3Reg. self MoveR: Extra3Reg R: ClassReg. self LogicalShiftLeftCq: 3 R: ClassReg. currentBlock := self Label. - jump5 jmpTarget: currentBlock. + jump6 jmpTarget: currentBlock. self AddCq: 8 R: ClassReg. - self MoveAw: objectMemory freeStartAddress R: Extra1Reg. - self AddR: ClassReg R: Extra1Reg. - s182 := objectMemory getScavengeThreshold. - self CmpCq: s182 R: Extra1Reg. - jump5 := self JumpBelowOrEqual: 0. - self CmpCq: s182 R: Extra1Reg. - jump7 := self JumpBelowOrEqual: 0. - self MoveR: SendNumArgsReg R: ReceiverResultReg. - jump4 := self Jump: 0. + self MoveAw: objectMemory freeStartAddress R: SendNumArgsReg. + self AddR: ClassReg R: SendNumArgsReg. + s168 := objectMemory getScavengeThreshold. + self CmpCq: s168 R: SendNumArgsReg. + jump6 := self JumpBelowOrEqual: 0. + self CmpCq: s168 R: SendNumArgsReg. + jump12 := self JumpAbove: 0. currentBlock := self Label. - jump5 jmpTarget: currentBlock. - jump7 jmpTarget: currentBlock. - self MoveAw: objectMemory freeStartAddress R: Extra1Reg. - self MoveMw: 8 r: SPReg R: Extra3Reg. + jump6 jmpTarget: currentBlock. + self MoveAw: objectMemory freeStartAddress R: SendNumArgsReg. + self MoveMw: 24 r: SPReg R: Extra3Reg. self MoveR: Extra3Reg R: Extra0Reg. self LogicalShiftLeftCq: 56 R: Extra0Reg. - self MoveMw: 16 r: SPReg R: Extra3Reg. - self LogicalShiftLeftCq: 24 R: Extra3Reg. - self MoveR: Extra3Reg Mw: 16 r: SPReg. - self MoveMw: 16 r: SPReg R: Extra3Reg. - self AddR: Extra3Reg R: Extra0Reg. + self LogicalShiftLeftCq: 24 R: Extra1Reg. + self AddR: Extra1Reg R: Extra0Reg. self AddR: Extra2Reg R: Extra0Reg. self OrCq: 0 R: Extra0Reg. - self MoveR: Extra0Reg M64: 0 r: Extra1Reg. + self MoveR: Extra0Reg M64: 0 r: SendNumArgsReg. self MoveAw: objectMemory freeStartAddress R: Extra0Reg. self AddR: ClassReg R: Extra0Reg. self MoveR: Extra0Reg Aw: objectMemory freeStartAddress. - self CmpCq: 0 R: Extra1Reg. - jump7 := self JumpNonZero: 0. self MoveR: SendNumArgsReg R: Extra0Reg. - jump5 := self Jump: 0. - currentBlock := self Label. - jump7 jmpTarget: currentBlock. - self MoveR: Extra1Reg R: Extra0Reg. self AddCq: 8 R: Extra0Reg. - self MoveMw: 8 r: SPReg R: Extra3Reg. + self MoveMw: 24 r: SPReg R: Extra3Reg. self LogicalShiftLeftCq: 3 R: Extra3Reg. - self MoveR: Extra3Reg Mw: 8 r: SPReg. - self MoveR: Extra1Reg R: ClassReg. - self MoveMw: 8 r: SPReg R: Extra3Reg. + self MoveR: Extra3Reg Mw: 24 r: SPReg. + self MoveR: SendNumArgsReg R: ClassReg. + self MoveMw: 24 r: SPReg R: Extra3Reg. self AddR: Extra3Reg R: ClassReg. self AddCq: 8 R: ClassReg. self SubCq: 1 R: ClassReg. - b944 := self Label. + b690 := self Label. self CmpR: Extra0Reg R: ClassReg. - jump7 := self JumpLess: 0. - self MoveMw: 24 r: SPReg R: Extra3Reg. + jump6 := self JumpLess: 0. + self MoveMw: 16 r: SPReg R: Extra3Reg. self MoveR: Extra3Reg M64: 0 r: Extra0Reg. self MoveR: Extra0Reg R: Extra2Reg. self AddCq: 8 R: Extra2Reg. self MoveR: Extra2Reg R: Extra0Reg. - jump13 := self Jump: b944. - currentBlock := self Label. - jump7 jmpTarget: currentBlock. - self MoveR: SendNumArgsReg R: Extra0Reg. - currentBlock := self Label. - jump5 jmpTarget: currentBlock. - self CmpCq: 0 R: Extra1Reg. - jump5 := self JumpNonZero: 0. - self MoveR: Extra0Reg R: ClassReg. - currentBlock := self Label. - jump3 jmpTarget: currentBlock. - self MoveR: ClassReg R: ReceiverResultReg. - jump3 := self Jump: 0. + jump5 := self Jump: b690. currentBlock := self Label. - jump5 jmpTarget: currentBlock. - self MoveR: Extra1Reg R: ReceiverResultReg. + jump6 jmpTarget: currentBlock. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self AddCq: 32 R: SPReg. self genPrimReturn. currentBlock := self Label. jump1 jmpTarget: currentBlock. jump2 jmpTarget: currentBlock. jump9 jmpTarget: currentBlock. + jump3 jmpTarget: currentBlock. + jump13 jmpTarget: currentBlock. jump11 jmpTarget: currentBlock. jump8 jmpTarget: currentBlock. - jump12 jmpTarget: currentBlock. + jump7 jmpTarget: currentBlock. jump10 jmpTarget: currentBlock. - jump6 jmpTarget: currentBlock. - jump4 jmpTarget: currentBlock. - jump3 jmpTarget: currentBlock. + jump12 jmpTarget: currentBlock. self AddCq: 32 R: SPReg. ^ 0 ] From 1f177fa6a9b7d36cf351288c887bbdcf12352fd9 Mon Sep 17 00:00:00 2001 From: palumbon Date: Wed, 2 Oct 2024 17:17:38 +0200 Subject: [PATCH 14/20] Refactoring DRLinearScanRegisterAllocatorTest --- ...DRLinearScanRegisterAllocatorTest.class.st | 73 ++++++++++++++----- 1 file changed, 53 insertions(+), 20 deletions(-) diff --git a/Druid-Tests/DRLinearScanRegisterAllocatorTest.class.st b/Druid-Tests/DRLinearScanRegisterAllocatorTest.class.st index 47fa906c..895232bd 100644 --- a/Druid-Tests/DRLinearScanRegisterAllocatorTest.class.st +++ b/Druid-Tests/DRLinearScanRegisterAllocatorTest.class.st @@ -877,6 +877,47 @@ DRLinearScanRegisterAllocatorTest >> testSpillIntroducesStore [ self assert: basicBlock instructions second operand1 equals: spillRegister. ] +{ #category : #'tests - spill' } +DRLinearScanRegisterAllocatorTest >> testSpillLoadStackValue [ + + | cfg basicBlock | + cfg := DRControlFlowGraph new. + basicBlock := cfg newBasicBlockWith: [ :block | | r0 r1 r2 | + r0 := block loadReceiver. + r1 := block loadStackValueAt: 0. + r2 := block loadStackValueAt: 1 ]. + cfg initialBasicBlock jumpTo: basicBlock. + + registerAllocator + integerRegisters: { }; + spillRegisters: { spillRegister1 }; + allocateRegistersIn: cfg. + + " + SPR1 := LoadReceriver + Store M0 SPR1 + SPR1 := Load-stack-value 0 + Store M1 SPR1 + SPR1 := Load-stack-value 1 + Store M2 SPR1 + " + + self assert: basicBlock instructions first isLoadReceiver. + self assert: basicBlock instructions first result equals: spillRegister1. + self assert: basicBlock instructions second isStore. + + self assert: basicBlock instructions third isLoadStackValue. + self assert: basicBlock instructions third operand1 value equals: 0. + self assert: basicBlock instructions third result equals: spillRegister1. + self assert: basicBlock instructions fourth isStore. + + self assert: basicBlock instructions fifth isLoadStackValue. + self assert: basicBlock instructions fifth operand1 value equals: 1. + self assert: basicBlock instructions fifth result equals: spillRegister1. + self assert: basicBlock instructions sixth isStore. + +] + { #category : #'tests - spill' } DRLinearScanRegisterAllocatorTest >> testSpillOnStores [ @@ -925,11 +966,8 @@ DRLinearScanRegisterAllocatorTest >> testSpillReceiverAndArguments [ | cfg basicBlock | cfg := DRControlFlowGraph new. basicBlock := cfg newBasicBlockWith: [ :block | | r0 r1 r2 | - "R0 := 2" r0 := block loadReceiver. - "R1 := 3" r1 := block loadArgument: 0. - "R2 := 4" r2 := block loadArgument: 1 ]. cfg initialBasicBlock jumpTo: basicBlock. @@ -946,11 +984,18 @@ DRLinearScanRegisterAllocatorTest >> testSpillReceiverAndArguments [ SPR1 := LoadArg1 Store M2 SPR1 " - + + self assert: basicBlock instructions first isLoadReceiver. self assert: basicBlock instructions first result equals: spillRegister1. self assert: basicBlock instructions second isStore. + + self assert: basicBlock instructions third isLoadArgument. + self assert: basicBlock instructions third operand1 value equals: 0. self assert: basicBlock instructions third result equals: spillRegister1. self assert: basicBlock instructions fourth isStore. + + self assert: basicBlock instructions fifth isLoadArgument. + self assert: basicBlock instructions fifth operand1 value equals: 1. self assert: basicBlock instructions fifth result equals: spillRegister1. self assert: basicBlock instructions sixth isStore. @@ -959,7 +1004,7 @@ DRLinearScanRegisterAllocatorTest >> testSpillReceiverAndArguments [ { #category : #'tests - spill' } DRLinearScanRegisterAllocatorTest >> testSpillStoresAndLoadsToSameAddress [ - | cfg basicBlock spillRegister1 spillRegister2 | + | cfg basicBlock | cfg := DRControlFlowGraph new. basicBlock := cfg newBasicBlockWith: [ :block | | r0 r1 r2 | "R0 := 2" @@ -970,9 +1015,6 @@ DRLinearScanRegisterAllocatorTest >> testSpillStoresAndLoadsToSameAddress [ r2 := block add: r0 to: r1 ]. cfg initialBasicBlock jumpTo: basicBlock. - "SPR1 is a spill register reserved for spill allocations" - spillRegister1 := DRPhysicalGeneralPurposeRegister name: 'SPR1'. - spillRegister2 := DRPhysicalGeneralPurposeRegister name: 'SPR2'. registerAllocator integerRegisters: { }; spillRegisters: { spillRegister1. spillRegister2 }; @@ -997,7 +1039,7 @@ DRLinearScanRegisterAllocatorTest >> testSpillStoresAndLoadsToSameAddress [ { #category : #'tests - spill' } DRLinearScanRegisterAllocatorTest >> testSpillTwice [ - | cfg basicBlock spillRegister1 spillRegister2 | + | cfg basicBlock | cfg := DRControlFlowGraph new. basicBlock := cfg newBasicBlockWith: [ :block | | r0 r1 r2 | "R0 := 2" @@ -1008,9 +1050,6 @@ DRLinearScanRegisterAllocatorTest >> testSpillTwice [ r2 := block add: r0 to: r1 ]. cfg initialBasicBlock jumpTo: basicBlock. - "SPR1 is a spill register reserved for spill allocations" - spillRegister1 := DRPhysicalGeneralPurposeRegister name: 'SPR1'. - spillRegister2 := DRPhysicalGeneralPurposeRegister name: 'SPR2'. registerAllocator integerRegisters: { }; spillRegisters: { spillRegister1. spillRegister2 }; @@ -1035,7 +1074,7 @@ DRLinearScanRegisterAllocatorTest >> testSpillTwice [ { #category : #'tests - spill' } DRLinearScanRegisterAllocatorTest >> testSpillTwiceIncrementsSpillSlotsToTwo [ - | cfg basicBlock spillRegister1 spillRegister2 | + | cfg basicBlock | cfg := DRControlFlowGraph new. basicBlock := cfg newBasicBlockWith: [ :block | | r0 r1 r2 | "R0 := 2" @@ -1046,9 +1085,6 @@ DRLinearScanRegisterAllocatorTest >> testSpillTwiceIncrementsSpillSlotsToTwo [ r2 := block add: r0 to: r1 ]. cfg initialBasicBlock jumpTo: basicBlock. - "SPR1 is a spill register reserved for spill allocations" - spillRegister1 := DRPhysicalGeneralPurposeRegister name: 'SPR1'. - spillRegister2 := DRPhysicalGeneralPurposeRegister name: 'SPR2'. registerAllocator integerRegisters: { }; spillRegisters: { spillRegister1. spillRegister2 }; @@ -1060,7 +1096,7 @@ DRLinearScanRegisterAllocatorTest >> testSpillTwiceIncrementsSpillSlotsToTwo [ { #category : #'tests - spill' } DRLinearScanRegisterAllocatorTest >> testSpillTwiceUsesDifferentAddresses [ - | cfg basicBlock spillRegister1 spillRegister2 | + | cfg basicBlock | cfg := DRControlFlowGraph new. basicBlock := cfg newBasicBlockWith: [ :block | | r0 r1 r2 | "R0 := 2" @@ -1071,9 +1107,6 @@ DRLinearScanRegisterAllocatorTest >> testSpillTwiceUsesDifferentAddresses [ r2 := block add: r0 to: r1 ]. cfg initialBasicBlock jumpTo: basicBlock. - "SPR1 is a spill register reserved for spill allocations" - spillRegister1 := DRPhysicalGeneralPurposeRegister name: 'SPR1'. - spillRegister2 := DRPhysicalGeneralPurposeRegister name: 'SPR2'. registerAllocator integerRegisters: { }; spillRegisters: { spillRegister1. spillRegister2 }; From d3291f2f41639e7b3a543b16de0a67331b57ebd6 Mon Sep 17 00:00:00 2001 From: palumbon Date: Wed, 2 Oct 2024 17:19:10 +0200 Subject: [PATCH 15/20] Fix offset for LoadStackValue with numberOfSpillSlots --- Druid/DRCogitCodeGenerator.class.st | 26 +++++++++---------- ...kToRegisterPrimitiveCodeGenerator.class.st | 6 ----- 2 files changed, 13 insertions(+), 19 deletions(-) diff --git a/Druid/DRCogitCodeGenerator.class.st b/Druid/DRCogitCodeGenerator.class.st index 2fa7746b..3c31f079 100644 --- a/Druid/DRCogitCodeGenerator.class.st +++ b/Druid/DRCogitCodeGenerator.class.st @@ -668,6 +668,12 @@ DRCogitCodeGenerator >> selectorCogitRTL: aMnemonic operands: operands instructi op rtlOperandQualifierForInstruction: anInstruction ])) ] +{ #category : #'code generation' } +DRCogitCodeGenerator >> spRegVariable [ + + ^ RBVariableNode named: 'SPReg' +] + { #category : #'code generation' } DRCogitCodeGenerator >> tempRegVariable [ @@ -1111,27 +1117,21 @@ DRCogitCodeGenerator >> visitLoad: aDRLoad [ { #category : #visiting } DRCogitCodeGenerator >> visitLoadStackValue: aDRLoadStackValue [ - | offset | - self assert: aDRLoadStackValue operand1 simpleConstantFold isNumber. - - offset := RBLiteralNode value: aDRLoadStackValue operand1 simpleConstantFold << 3. -" RBMessageNode - receiver: (aDRLoadStackValue operand1 rtlPushArgumentExpressions: self) first - selector: #<< - arguments: { RBVariableNode named: '3' }. -" + offset := aDRLoadStackValue operand1 simpleConstantFold + + aDRLoadStackValue controlFlowGraph numberOfSpillSlots + << 3. "bytes" - "cogit MoveMw: index r: SPReg R: TempReg" + "cogit MoveMw: offset r: SPReg R: t0" generatorMethodBuilder addStatement: (RBMessageNode receiver: RBVariableNode selfNode selector: #MoveMw:r:R: arguments: { - offset. - (RBVariableNode named: 'SPReg'). - (RBVariableNode named: aDRLoadStackValue result name) }) + (RBLiteralNode value: offset). + self spRegVariable. + (self rtlExpressionForValue: aDRLoadStackValue) }) ] { #category : #visiting } diff --git a/Druid/DRCogitStackToRegisterPrimitiveCodeGenerator.class.st b/Druid/DRCogitStackToRegisterPrimitiveCodeGenerator.class.st index 04aa7fb6..be4780e9 100644 --- a/Druid/DRCogitStackToRegisterPrimitiveCodeGenerator.class.st +++ b/Druid/DRCogitStackToRegisterPrimitiveCodeGenerator.class.st @@ -4,12 +4,6 @@ Class { #category : #'Druid-Cogit' } -{ #category : #'code generation' } -DRCogitStackToRegisterPrimitiveCodeGenerator >> spRegVariable [ - - ^ RBVariableNode named: 'SPReg' -] - { #category : #visiting } DRCogitStackToRegisterPrimitiveCodeGenerator >> visitLoadArgument: aDRLoadArgument [ "Just copy the Arg[X]Reg to the result" From 4f555e60f7023294a111a35bb8ab5c8dba52b03b Mon Sep 17 00:00:00 2001 From: palumbon Date: Wed, 2 Oct 2024 17:58:44 +0200 Subject: [PATCH 16/20] Fix replacement of stack dependencies --- .../SimpleDruidTestRTLCompiler.class.st | 171 +++++++++--------- Druid/DRStackInstruction.class.st | 3 +- 2 files changed, 87 insertions(+), 87 deletions(-) diff --git a/Druid-Tests/SimpleDruidTestRTLCompiler.class.st b/Druid-Tests/SimpleDruidTestRTLCompiler.class.st index f3ea27ee..4b11d308 100644 --- a/Druid-Tests/SimpleDruidTestRTLCompiler.class.st +++ b/Druid-Tests/SimpleDruidTestRTLCompiler.class.st @@ -642,7 +642,7 @@ SimpleDruidTestRTLCompiler >> gen_emptyPrimitiveWithArguments [ "AutoGenerated by Druid" | currentBlock | - self genLoadArg: 0 into: ClassReg. + self genLoadArg: 0 spilled: 0 into: ClassReg. self genPrimReturn. ^ CompletePrimitive ] @@ -1587,7 +1587,7 @@ SimpleDruidTestRTLCompiler >> gen_failingPrimitiveWithArg [ "AutoGenerated by Druid" | currentBlock | - self genLoadArg: 0 into: ClassReg. + self genLoadArg: 0 spilled: 0 into: ClassReg. ^ 0 ] @@ -1623,7 +1623,7 @@ SimpleDruidTestRTLCompiler >> gen_ifZeroFailPrimitive [ | jump1 currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self CmpCq: 0 R: ClassReg. jump1 := self JumpZero: 0. self MoveCq: 42 R: ReceiverResultReg. @@ -1660,7 +1660,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAdd [ | jump1 jump2 currentBlock | self mclassIsSmallInteger ifFalse: [ ^ UnimplementedPrimitive ]. self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArgAtDepth: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self TstCq: 1 R: SendNumArgsReg. jump1 := self JumpZero: 0. self AddCq: -1 R: SendNumArgsReg. @@ -1731,7 +1731,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveArithmeticBitShiftRight [ | currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self ArithmeticShiftRightR: SendNumArgsReg R: ClassReg. self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. @@ -1766,7 +1766,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAsCharacter [ s13 := self methodNumArgs. s13 = 1 ifTrue: [ | jump3 jump2 jump1 | - self genLoadArgAtDepth: 0 into: ClassReg. + self genLoadArg: 0 spilled: 0 into: ClassReg. self TstCq: 1 R: ClassReg. jump3 := self JumpZero: 0. self ArithmeticShiftRightCq: 3 R: ClassReg. @@ -1863,7 +1863,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAsFloatAddition [ | currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self ConvertR: SendNumArgsReg Rd: DPFPReg0. self ConvertR: ClassReg Rd: DPFPReg1. self AddRd: DPFPReg1 Rd: DPFPReg0. @@ -1879,7 +1879,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAsFloatDivision [ | currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self ConvertR: SendNumArgsReg Rd: DPFPReg0. self ConvertR: ClassReg Rd: DPFPReg1. self DivRd: DPFPReg1 Rd: DPFPReg0. @@ -1895,7 +1895,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAsFloatMultiply [ | currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self ConvertR: SendNumArgsReg Rd: DPFPReg0. self ConvertR: ClassReg Rd: DPFPReg1. self MulRd: DPFPReg1 Rd: DPFPReg0. @@ -1911,7 +1911,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAsFloatSubtract [ | currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self ConvertR: SendNumArgsReg Rd: DPFPReg0. self ConvertR: ClassReg Rd: DPFPReg1. self SubRd: DPFPReg1 Rd: DPFPReg0. @@ -1985,7 +1985,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAt [ self SubCq: 24 R: SPReg. self MoveR: ReceiverResultReg R: Extra3Reg. self MoveR: Extra3Reg Mw: 0 r: SPReg. - self genLoadArgAtDepth: 3 into: Extra3Reg. + self genLoadArg: 0 spilled: 3 into: Extra3Reg. self MoveR: Extra3Reg Mw: 8 r: SPReg. self MoveMw: 0 r: SPReg R: Extra3Reg. self TstCq: 7 R: Extra3Reg. @@ -2085,13 +2085,12 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAt [ currentBlock := self Label. jump6 jmpTarget: currentBlock. s73 := 0. - self MoveCq: s73 R: SendNumArgsReg. + self MoveCq: s73 R: Extra2Reg. jump6 := self Jump: 0. currentBlock := self Label. jump9 jmpTarget: currentBlock. self CmpCq: 2 R: Extra1Reg. jump9 := self JumpAboveOrEqual: 0. - self MoveR: Extra2Reg R: SendNumArgsReg. self MoveR: Extra2Reg R: ClassReg. jump7 := self Jump: 0. currentBlock := self Label. @@ -2141,8 +2140,8 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAt [ self MoveM64: 24 r: ClassReg R: Extra0Reg. self ArithmeticShiftRightCq: 3 R: Extra0Reg. self AndCq: 16rFFFF R: Extra0Reg. - self MoveR: Extra0Reg R: SendNumArgsReg. self MoveR: Extra2Reg R: ClassReg. + self MoveR: Extra0Reg R: Extra2Reg. currentBlock := self Label. jump6 jmpTarget: currentBlock. jump7 jmpTarget: currentBlock. @@ -2156,7 +2155,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAt [ jump6 := self JumpZero: 0. currentBlock := self Label. jump7 jmpTarget: currentBlock. - self SubR: SendNumArgsReg R: ClassReg. + self SubR: Extra2Reg R: ClassReg. self CmpCq: 24 R: Extra1Reg. jump7 := self JumpAboveOrEqual: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. @@ -2166,7 +2165,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveAt [ self CmpR: ClassReg R: Extra3Reg. jump4 := self JumpAbove: 0. self MoveMw: 8 r: SPReg R: Extra3Reg. - self AddR: SendNumArgsReg R: Extra3Reg. + self AddR: Extra2Reg R: Extra3Reg. self MoveR: Extra3Reg Mw: 8 r: SPReg. self CmpCq: 5 R: Extra1Reg. jump9 := self JumpAbove: 0. @@ -2659,7 +2658,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveBitAnd [ | jump1 currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArgAtDepth: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self MoveR: SendNumArgsReg R: Extra0Reg. self AndR: ClassReg R: Extra0Reg. self TstCq: 1 R: Extra0Reg. @@ -2678,7 +2677,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveBitShift [ | jump1 jump2 currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self CmpCq: 0 R: SendNumArgsReg. jump1 := self JumpLessOrEqual: 0. self LogicalShiftLeftR: SendNumArgsReg R: ClassReg. @@ -2703,7 +2702,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveBitXor [ | currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self XorR: ClassReg R: SendNumArgsReg. self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. @@ -2962,7 +2961,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveClass [ s56 := self methodNumArgs. s56 = 1 ifTrue: [ | jump5 jump3 jump1 jump6 jump4 jump2 | - self genLoadArgAtDepth: 0 into: Extra0Reg. + self genLoadArg: 0 spilled: 0 into: Extra0Reg. self MoveR: Extra0Reg R: ClassReg. self AndCq: 7 R: ClassReg. self CmpCq: 0 R: ClassReg. @@ -3248,13 +3247,13 @@ SimpleDruidTestRTLCompiler >> gen_primitiveDivide [ | currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self DivR: SendNumArgsReg R: ClassReg - Quo: ClassReg - Rem: SendNumArgsReg. - self MoveR: ClassReg R: ReceiverResultReg. + Quo: SendNumArgsReg + Rem: ClassReg. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -3397,7 +3396,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveEqualsThanFloats [ | jumpNext currentBlock jumpTrue | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self ConvertR: SendNumArgsReg Rd: DPFPReg0. self ConvertR: ClassReg Rd: DPFPReg1. self CmpRd: DPFPReg1 Rd: DPFPReg0. @@ -3519,7 +3518,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloat64AtPut [ | currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self ConvertR: SendNumArgsReg Rd: DPFPReg0. self MoveRd: DPFPReg0 M64: 0 r: ClassReg. self genPrimReturn. @@ -3532,7 +3531,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatAdd [ | jump1 s89 jumpNext jump9 jump6 jump3 currentBlock jump8 jump5 jump2 s121 jumpTrue s118 s93 jump7 jump4 | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArgAtDepth: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self MoveR: ClassReg R: Extra0Reg. self AndCq: 7 R: Extra0Reg. self CmpCq: 0 R: Extra0Reg. @@ -3731,7 +3730,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatEqual [ | jump1 jump6 jump3 currentBlock s82 jump8 jump5 s79 jump2 jump7 jump4 | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArgAtDepth: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self MoveR: ClassReg R: Extra0Reg. self AndCq: 7 R: Extra0Reg. self CmpCq: 0 R: Extra0Reg. @@ -3849,7 +3848,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatMultiply [ | jump1 s89 jumpNext jump9 jump6 jump3 currentBlock jump8 jump5 jump2 s121 jumpTrue s118 s93 jump7 jump4 | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArgAtDepth: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self MoveR: ClassReg R: Extra0Reg. self AndCq: 7 R: Extra0Reg. self CmpCq: 0 R: Extra0Reg. @@ -4032,7 +4031,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatNotEqual [ | jump1 jump6 jump3 currentBlock s82 jump8 jump5 s79 jump2 jump7 jump4 | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArgAtDepth: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self MoveR: ClassReg R: Extra0Reg. self AndCq: 7 R: Extra0Reg. self CmpCq: 0 R: Extra0Reg. @@ -4150,7 +4149,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFloatSubtract [ | jump1 s89 jumpNext jump9 jump6 jump3 currentBlock jump8 jump5 jump2 s121 jumpTrue s118 s93 jump7 jump4 | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArgAtDepth: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self MoveR: ClassReg R: Extra0Reg. self AndCq: 7 R: Extra0Reg. self CmpCq: 0 R: Extra0Reg. @@ -4368,7 +4367,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFullClosureValue [ s22 = 1 ifTrue: [ | jump4 jump3 jump2 jump1 | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArgAtDepth: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self MoveM64: 24 r: ClassReg R: SendNumArgsReg. self ArithmeticShiftRightCq: 3 R: SendNumArgsReg. self CmpCq: 1 R: SendNumArgsReg. @@ -4401,8 +4400,8 @@ SimpleDruidTestRTLCompiler >> gen_primitiveFullClosureValue [ s43 = 2 ifTrue: [ | jump1 jump2 jump3 jump4 | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArgAtDepth: 0 into: SendNumArgsReg. - self genLoadArgAtDepth: 1 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. + self genLoadArg: 1 spilled: 0 into: SendNumArgsReg. self MoveM64: 24 r: ClassReg R: SendNumArgsReg. self ArithmeticShiftRightCq: 3 R: SendNumArgsReg. self CmpCq: 2 R: SendNumArgsReg. @@ -4439,7 +4438,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveGreaterOrEqualThanArgument [ "AutoGenerated by Druid" | jumpNext currentBlock jumpTrue | - self genLoadArg: 0 into: ClassReg. + self genLoadArg: 0 spilled: 0 into: ClassReg. self CmpCq: 0 R: ClassReg. jumpTrue := self JumpGreaterOrEqual: 0. self MoveCq: 0 R: ClassReg. @@ -4498,7 +4497,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveGreaterOrEqualsThanFloats [ | jumpNext currentBlock jumpTrue | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self ConvertR: SendNumArgsReg Rd: DPFPReg0. self ConvertR: ClassReg Rd: DPFPReg1. self CmpRd: DPFPReg1 Rd: DPFPReg0. @@ -4562,7 +4561,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveGreaterThanArgument [ "AutoGenerated by Druid" | jumpNext currentBlock jumpTrue | - self genLoadArg: 0 into: ClassReg. + self genLoadArg: 0 spilled: 0 into: ClassReg. self CmpCq: 0 R: ClassReg. jumpTrue := self JumpGreater: 0. self MoveCq: 0 R: ClassReg. @@ -4604,7 +4603,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveGreaterThanFloats [ | jumpNext currentBlock jumpTrue | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self ConvertR: SendNumArgsReg Rd: DPFPReg0. self ConvertR: ClassReg Rd: DPFPReg1. self CmpRd: DPFPReg1 Rd: DPFPReg0. @@ -4838,7 +4837,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveImmediateAsInteger [ s40 := self methodNumArgs. s40 = 1 ifTrue: [ | jump5 jump3 jump1 jump4 jump2 | - self genLoadArgAtDepth: 0 into: ClassReg. + self genLoadArg: 0 spilled: 0 into: ClassReg. self TstCq: 1 R: ClassReg. jump1 := self JumpZero: 0. self ArithmeticShiftRightCq: 3 R: ClassReg. @@ -4987,13 +4986,13 @@ SimpleDruidTestRTLCompiler >> gen_primitiveIntegerDivide [ | currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self DivR: SendNumArgsReg R: ClassReg - Quo: ClassReg - Rem: SendNumArgsReg. - self MoveR: ClassReg R: ReceiverResultReg. + Quo: SendNumArgsReg + Rem: ClassReg. + self MoveR: SendNumArgsReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -5009,9 +5008,9 @@ SimpleDruidTestRTLCompiler >> gen_primitiveIntegerDivideByConstant [ self DivR: SendNumArgsReg R: ClassReg - Quo: SendNumArgsReg - Rem: ClassReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. + Quo: ClassReg + Rem: SendNumArgsReg. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -5068,7 +5067,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveLessOrEqualThanArgument [ "AutoGenerated by Druid" | jumpNext currentBlock jumpTrue | - self genLoadArg: 0 into: ClassReg. + self genLoadArg: 0 spilled: 0 into: ClassReg. self CmpCq: 0 R: ClassReg. jumpTrue := self JumpLessOrEqual: 0. self MoveCq: 0 R: ClassReg. @@ -5127,7 +5126,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveLessOrEqualsThanFloats [ | jumpNext currentBlock jumpTrue | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self ConvertR: SendNumArgsReg Rd: DPFPReg0. self ConvertR: ClassReg Rd: DPFPReg1. self CmpRd: DPFPReg1 Rd: DPFPReg0. @@ -5191,7 +5190,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveLessThanArgument [ "AutoGenerated by Druid" | jumpNext currentBlock jumpTrue | - self genLoadArg: 0 into: ClassReg. + self genLoadArg: 0 spilled: 0 into: ClassReg. self CmpCq: 0 R: ClassReg. jumpTrue := self JumpLess: 0. self MoveCq: 0 R: ClassReg. @@ -5210,7 +5209,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveLessThanFloats [ | jumpNext currentBlock jumpTrue | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self ConvertR: SendNumArgsReg Rd: DPFPReg0. self ConvertR: ClassReg Rd: DPFPReg1. self CmpRd: DPFPReg1 Rd: DPFPReg0. @@ -5298,7 +5297,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveLogicalBitShiftRight [ | currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self LogicalShiftRightR: SendNumArgsReg R: ClassReg. self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. @@ -5364,7 +5363,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveMod [ | currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self DivR: SendNumArgsReg R: ClassReg @@ -5449,7 +5448,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveMultiplyWithOverflow [ | jump1 jump2 currentBlock s8 | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self ArithmeticShiftRightCq: 3 R: ClassReg. self SubCq: 1 R: SendNumArgsReg. self MulR: ClassReg R: SendNumArgsReg. @@ -5612,7 +5611,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveNewWithArg [ self SubCq: 32 R: SPReg. self MoveR: ReceiverResultReg R: Extra3Reg. self MoveR: Extra3Reg Mw: 0 r: SPReg. - self genLoadArgAtDepth: 4 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 4 into: SendNumArgsReg. self TstCq: 1 R: SendNumArgsReg. jump1 := self JumpZero: 0. self ArithmeticShiftRightCq: 3 R: SendNumArgsReg. @@ -5721,37 +5720,37 @@ SimpleDruidTestRTLCompiler >> gen_primitiveNewWithArg [ self DivR: Extra0Reg R: ClassReg - Quo: Extra2Reg - Rem: Extra0Reg. + Quo: Extra0Reg + Rem: ClassReg. s85 := 4. - self MoveCq: s85 R: Extra0Reg. - self SubR: SendNumArgsReg R: Extra0Reg. - self AndCq: 3 R: Extra0Reg. - self AddR: Extra0Reg R: Extra1Reg. + self MoveCq: s85 R: ClassReg. + self SubR: SendNumArgsReg R: ClassReg. + self AndCq: 3 R: ClassReg. + self AddR: ClassReg R: Extra1Reg. self MoveCq: s78 R: ClassReg. - self MoveR: Extra2Reg R: SendNumArgsReg. + self MoveR: Extra0Reg R: SendNumArgsReg. jump8 := self Jump: 0. currentBlock := self Label. jump3 jmpTarget: currentBlock. s94 := 0. self CmpCq: 16 R: Extra1Reg. jump3 := self JumpNonZero: 0. - self MoveR: SendNumArgsReg R: Extra0Reg. - self AddCq: 7 R: Extra0Reg. + self MoveR: SendNumArgsReg R: ClassReg. + self AddCq: 7 R: ClassReg. s98 := 8. - self MoveCq: s98 R: Extra2Reg. + self MoveCq: s98 R: Extra0Reg. self - DivR: Extra2Reg - R: Extra0Reg - Quo: Extra0Reg - Rem: Extra2Reg. + DivR: Extra0Reg + R: ClassReg + Quo: Extra2Reg + Rem: Extra0Reg. s101 := 8. - self MoveCq: s101 R: Extra2Reg. - self SubR: SendNumArgsReg R: Extra2Reg. - self AndCq: 7 R: Extra2Reg. - self AddR: Extra2Reg R: Extra1Reg. + self MoveCq: s101 R: Extra0Reg. + self SubR: SendNumArgsReg R: Extra0Reg. + self AndCq: 7 R: Extra0Reg. + self AddR: Extra0Reg R: Extra1Reg. self MoveCq: s94 R: ClassReg. - self MoveR: Extra0Reg R: SendNumArgsReg. + self MoveR: Extra2Reg R: SendNumArgsReg. jump12 := self Jump: 0. currentBlock := self Label. jump3 jmpTarget: currentBlock. @@ -5954,7 +5953,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveNotEqualsThanFloats [ | jumpNext currentBlock jumpTrue | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self ConvertR: SendNumArgsReg Rd: DPFPReg0. self ConvertR: ClassReg Rd: DPFPReg1. self CmpRd: DPFPReg1 Rd: DPFPReg0. @@ -6038,7 +6037,7 @@ SimpleDruidTestRTLCompiler >> gen_primitivePushFirstArgument [ "AutoGenerated by Druid" | currentBlock | - self genLoadArg: 0 into: ClassReg. + self genLoadArg: 0 spilled: 0 into: ClassReg. self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive @@ -6058,7 +6057,7 @@ SimpleDruidTestRTLCompiler >> gen_primitivePushReceiverOf1ArgSelector [ "AutoGenerated by Druid" | currentBlock | - self genLoadArg: 0 into: ClassReg. + self genLoadArg: 0 spilled: 0 into: ClassReg. self genPrimReturn. ^ CompletePrimitive ] @@ -6117,8 +6116,8 @@ SimpleDruidTestRTLCompiler >> gen_primitiveReturnOneWithArguments [ "AutoGenerated by Druid" | currentBlock | - self genLoadArg: 0 into: ClassReg. - self genLoadArg: 1 into: ClassReg. + self genLoadArg: 0 spilled: 0 into: ClassReg. + self genLoadArg: 1 spilled: 0 into: ClassReg. self MoveCq: 1 R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive @@ -6468,7 +6467,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveSubWithOverflow [ | jump1 jump2 currentBlock s7 | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self AddCq: -1 R: SendNumArgsReg. self SubR: SendNumArgsReg R: ClassReg. jump1 := self JumpNoOverflow: 0. @@ -6491,7 +6490,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveSumWithOverflow [ | jump1 jump2 currentBlock s7 | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self AddCq: -1 R: ClassReg. self AddR: SendNumArgsReg R: ClassReg. jump1 := self JumpNoOverflow: 0. @@ -6557,7 +6556,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveUint16AtPut [ | currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self MoveR: SendNumArgsReg M64: 0 r: ClassReg. self genPrimReturn. ^ CompletePrimitive @@ -6582,7 +6581,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveUint32AtPut [ | currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self MoveR: SendNumArgsReg M64: 0 r: ClassReg. self genPrimReturn. ^ CompletePrimitive @@ -6606,7 +6605,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveUint64AtPut [ | currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self MoveR: SendNumArgsReg M64: 0 r: ClassReg. self genPrimReturn. ^ CompletePrimitive @@ -6631,7 +6630,7 @@ SimpleDruidTestRTLCompiler >> gen_primitiveUint8AtPut [ | currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. self MoveR: SendNumArgsReg M64: 0 r: ClassReg. self genPrimReturn. ^ CompletePrimitive @@ -6824,8 +6823,8 @@ SimpleDruidTestRTLCompiler >> gen_primitiveWithTwoArgs [ | jump1 jump2 currentBlock | self MoveR: ReceiverResultReg R: ClassReg. - self genLoadArg: 0 into: SendNumArgsReg. - self genLoadArg: 1 into: Extra0Reg. + self genLoadArg: 0 spilled: 0 into: SendNumArgsReg. + self genLoadArg: 1 spilled: 0 into: Extra0Reg. self CmpCq: 0 R: ClassReg. jump1 := self JumpLessOrEqual: 0. jump2 := self Jump: 0. diff --git a/Druid/DRStackInstruction.class.st b/Druid/DRStackInstruction.class.st index 931032ad..6a6fc892 100644 --- a/Druid/DRStackInstruction.class.st +++ b/Druid/DRStackInstruction.class.st @@ -69,8 +69,9 @@ DRStackInstruction >> removeStackDependent: aStackDependent [ { #category : #accessing } DRStackInstruction >> replaceDependency: anOperand by: anotherOperand [ + anOperand = anotherOperand ifTrue: [ ^ self ]. + (self stackDependencies asArray includes: anOperand) ifTrue: [ - anOperand replaceBy: anotherOperand. self stackDependencies: (self stackDependencies asArray copyWithout: anOperand). self stackDependencies add: anotherOperand. ^ self ]. From 60c04082b967cf632e7f7857fc589d1d4cc7563b Mon Sep 17 00:00:00 2001 From: palumbon Date: Thu, 3 Oct 2024 18:43:06 +0200 Subject: [PATCH 17/20] Testing storeAndPopRemoteTempLongBytecode meta-compilation --- Druid-Tests/DRProductionBytecodeTest.class.st | 41 ++ Druid-Tests/DruidTestRTLCompiler.class.st | 311 +++++++++++++-- .../SimpleDruidTestRTLCompiler.class.st | 373 ++++++++++++++++++ 3 files changed, 683 insertions(+), 42 deletions(-) diff --git a/Druid-Tests/DRProductionBytecodeTest.class.st b/Druid-Tests/DRProductionBytecodeTest.class.st index 01b04aeb..a9a70fb7 100644 --- a/Druid-Tests/DRProductionBytecodeTest.class.st +++ b/Druid-Tests/DRProductionBytecodeTest.class.st @@ -3032,3 +3032,44 @@ DRProductionBytecodeTest >> testStoreAndPopReceiverVariableBytecodeRememberedRec self assert: machineSimulator receiverRegisterValue equals: object. self assert: (memory fetchPointer: 0 ofObject: object) equals: value ] + +{ #category : #tests } +DRProductionBytecodeTest >> testStoreAndPopRemoteTempLongBytecode [ + + | object vectIndex tempIndex | + cogit ceStoreCheckTrampoline: fakeTrampoline. + vectIndex := 3. + tempIndex := 1. + + cogit byte1: vectIndex. + cogit byte2: tempIndex. + + self + compileBytecode: 253 + selector: #storeAndPopRemoteTempLongBytecode + thenDo: [ :generator | + cogit methodOrBlockNumTemps: 2. + cogit methodOrBlockNumArgs: 0. + cogit ssPushRegister: ReceiverResultReg. + + "Execute the druid's compiled code" + generator value. + + "Then return without druid's compiled code" + cogit genUpArrowReturn ]. + + object := self newObjectWithSlots: vectIndex + 1. + + self + createFramefulCallFrom: callerAddress + receiver: memory trueObject + arguments: #() + temporaries: { object }. + self pushAddress: memory nilObject. + + self executePrimitiveWithReceiver: memory trueObject. "????" + + self assert: machineSimulator receiverRegisterValue equals: memory trueObject. + + self assert: (memory fetchPointer: vectIndex ofObject: object) equals: memory trueObject +] diff --git a/Druid-Tests/DruidTestRTLCompiler.class.st b/Druid-Tests/DruidTestRTLCompiler.class.st index b059fa61..a35dcb3d 100644 --- a/Druid-Tests/DruidTestRTLCompiler.class.st +++ b/Druid-Tests/DruidTestRTLCompiler.class.st @@ -9849,9 +9849,9 @@ DruidTestRTLCompiler >> gen_primitiveModByConstant [ self DivR: SendNumArgsReg R: ClassReg - Quo: ClassReg - Rem: SendNumArgsReg. - self MoveR: SendNumArgsReg R: ReceiverResultReg. + Quo: SendNumArgsReg + Rem: ClassReg. + self MoveR: ClassReg R: ReceiverResultReg. self genPrimReturn. ^ CompletePrimitive ] @@ -10140,11 +10140,10 @@ DruidTestRTLCompiler >> gen_primitiveNewWithArg [ self DivR: Extra0Reg R: ClassReg - Quo: Extra0Reg - Rem: ClassReg. + Quo: ClassReg + Rem: Extra0Reg. self AndCq: 1 R: SendNumArgsReg. self AddR: SendNumArgsReg R: Extra1Reg. - self MoveR: Extra0Reg R: ClassReg. jump10 := self Jump: 0. currentBlock := self Label. jump8 jmpTarget: currentBlock. @@ -10156,18 +10155,17 @@ DruidTestRTLCompiler >> gen_primitiveNewWithArg [ self DivR: Extra0Reg R: ClassReg - Quo: Extra0Reg - Rem: ClassReg. + Quo: ClassReg + Rem: Extra0Reg. self AndCq: 1 R: SendNumArgsReg. self AddR: SendNumArgsReg R: Extra1Reg. self MoveMw: 8 r: SPReg R: Extra3Reg. self CmpCq: 0 R: Extra3Reg. jump8 := self JumpNonZero: 0. - self MoveCq: s55 R: ClassReg. + self MoveCq: s55 R: Extra0Reg. jump11 := self Jump: 0. currentBlock := self Label. jump8 jmpTarget: currentBlock. - self MoveR: Extra0Reg R: ClassReg. currentBlock := self Label. jump10 jmpTarget: currentBlock. s73 := 0. @@ -10237,7 +10235,8 @@ DruidTestRTLCompiler >> gen_primitiveNewWithArg [ self MoveMw: 8 r: SPReg R: Extra3Reg. self CmpCq: 0 R: Extra3Reg. jump12 := self JumpNonZero: 0. - self MoveR: SendNumArgsReg R: Extra0Reg. + self MoveR: ClassReg R: Extra0Reg. + self MoveR: SendNumArgsReg R: ClassReg. currentBlock := self Label. jump11 jmpTarget: currentBlock. self MoveMw: 0 r: SPReg R: Extra3Reg. @@ -10248,9 +10247,9 @@ DruidTestRTLCompiler >> gen_primitiveNewWithArg [ jump11 := self JumpZero: 0. self CmpCq: 0 R: Extra2Reg. jump8 := self JumpBelow: 0. - self MoveR: ClassReg R: Extra3Reg. - self MoveR: Extra3Reg Mw: 16 r: SPReg. self MoveR: Extra0Reg R: Extra3Reg. + self MoveR: Extra3Reg Mw: 16 r: SPReg. + self MoveR: ClassReg R: Extra3Reg. self MoveR: Extra3Reg Mw: 24 r: SPReg. jump7 := self Jump: 0. currentBlock := self Label. @@ -10277,59 +10276,59 @@ DruidTestRTLCompiler >> gen_primitiveNewWithArg [ self CmpCq: 1 R: Extra3Reg. jump12 := self JumpAboveOrEqual: 0. s157 := 8. - self MoveCq: s157 R: ClassReg. + self MoveCq: s157 R: SendNumArgsReg. jump6 := self Jump: 0. currentBlock := self Label. jump12 jmpTarget: currentBlock. self MoveMw: 24 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg R: ClassReg. - self LogicalShiftLeftCq: 3 R: ClassReg. + self MoveR: Extra3Reg R: SendNumArgsReg. + self LogicalShiftLeftCq: 3 R: SendNumArgsReg. currentBlock := self Label. jump6 jmpTarget: currentBlock. - self AddCq: 8 R: ClassReg. - self MoveAw: objectMemory freeStartAddress R: SendNumArgsReg. - self AddR: ClassReg R: SendNumArgsReg. + self AddCq: 8 R: SendNumArgsReg. + self MoveAw: objectMemory freeStartAddress R: Extra0Reg. + self AddR: SendNumArgsReg R: Extra0Reg. s168 := objectMemory getScavengeThreshold. - self CmpCq: s168 R: SendNumArgsReg. + self CmpCq: s168 R: Extra0Reg. jump6 := self JumpBelowOrEqual: 0. - self CmpCq: s168 R: SendNumArgsReg. + self CmpCq: s168 R: Extra0Reg. jump12 := self JumpAbove: 0. currentBlock := self Label. jump6 jmpTarget: currentBlock. - self MoveAw: objectMemory freeStartAddress R: SendNumArgsReg. + self MoveAw: objectMemory freeStartAddress R: Extra0Reg. self MoveMw: 24 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg R: Extra0Reg. - self LogicalShiftLeftCq: 56 R: Extra0Reg. + self MoveR: Extra3Reg R: ClassReg. + self LogicalShiftLeftCq: 56 R: ClassReg. self LogicalShiftLeftCq: 24 R: Extra1Reg. - self AddR: Extra1Reg R: Extra0Reg. - self AddR: Extra2Reg R: Extra0Reg. - self OrCq: 0 R: Extra0Reg. - self MoveR: Extra0Reg M64: 0 r: SendNumArgsReg. - self MoveAw: objectMemory freeStartAddress R: Extra0Reg. - self AddR: ClassReg R: Extra0Reg. - self MoveR: Extra0Reg Aw: objectMemory freeStartAddress. - self MoveR: SendNumArgsReg R: Extra0Reg. - self AddCq: 8 R: Extra0Reg. + self AddR: Extra1Reg R: ClassReg. + self AddR: Extra2Reg R: ClassReg. + self OrCq: 0 R: ClassReg. + self MoveR: ClassReg M64: 0 r: Extra0Reg. + self MoveAw: objectMemory freeStartAddress R: ClassReg. + self AddR: SendNumArgsReg R: ClassReg. + self MoveR: ClassReg Aw: objectMemory freeStartAddress. + self MoveR: Extra0Reg R: ClassReg. + self AddCq: 8 R: ClassReg. self MoveMw: 24 r: SPReg R: Extra3Reg. self LogicalShiftLeftCq: 3 R: Extra3Reg. self MoveR: Extra3Reg Mw: 24 r: SPReg. - self MoveR: SendNumArgsReg R: ClassReg. + self MoveR: Extra0Reg R: SendNumArgsReg. self MoveMw: 24 r: SPReg R: Extra3Reg. - self AddR: Extra3Reg R: ClassReg. - self AddCq: 8 R: ClassReg. - self SubCq: 1 R: ClassReg. + self AddR: Extra3Reg R: SendNumArgsReg. + self AddCq: 8 R: SendNumArgsReg. + self SubCq: 1 R: SendNumArgsReg. b690 := self Label. - self CmpR: Extra0Reg R: ClassReg. + self CmpR: ClassReg R: SendNumArgsReg. jump6 := self JumpLess: 0. self MoveMw: 16 r: SPReg R: Extra3Reg. - self MoveR: Extra3Reg M64: 0 r: Extra0Reg. - self MoveR: Extra0Reg R: Extra2Reg. + self MoveR: Extra3Reg M64: 0 r: ClassReg. + self MoveR: ClassReg R: Extra2Reg. self AddCq: 8 R: Extra2Reg. - self MoveR: Extra2Reg R: Extra0Reg. + self MoveR: Extra2Reg R: ClassReg. jump5 := self Jump: b690. currentBlock := self Label. jump6 jmpTarget: currentBlock. - self MoveR: SendNumArgsReg R: ReceiverResultReg. + self MoveR: Extra0Reg R: ReceiverResultReg. self AddCq: 32 R: SPReg. self genPrimReturn. currentBlock := self Label. @@ -11990,6 +11989,234 @@ DruidTestRTLCompiler >> gen_storeAndPopReceiverVariableBytecode [ ^ 0 ] +{ #category : #generated } +DruidTestRTLCompiler >> gen_storeAndPopRemoteTempLongBytecode [ + "AutoGenerated by Druid" + + | s6 s79 jump5 s46 jump3 s38 jump8 jump1 s75 t1 s2 currentBlock s51 s49 jump6 s73 jumpNext live s5 jumpTrue s3 t2 jump2 jump7 t0 s41 | + live := 0. + t0 := self + allocateRegNotConflictingWith: live + ifNone: [ ^ self unknownBytecode ]. + live := live bitOr: (self registerMaskFor: t0). + t1 := self + allocateRegNotConflictingWith: live + ifNone: [ ^ self unknownBytecode ]. + live := live bitOr: (self registerMaskFor: t1). + t2 := self + allocateRegNotConflictingWith: live + ifNone: [ ^ self unknownBytecode ]. + live := live bitOr: (self registerMaskFor: t2). + self annotateBytecode: self Label. + s3 := byte1. + (self simStackTempAt: byte2) copyToReg: t0. + s5 := TempVectReadBarrier. + s5 ifTrue: [ + | jump1 b557 jumpNext jump6 jump3 jump8 jump5 jumpTrue jump2 jump7 jump4 | + self MoveM64: 0 r: t0 R: t1. + self AndCq: 16r3FFFF7 R: t1. + self CmpCq: 0 R: t1. + jump1 := self JumpNonZero: 0. + self MoveM64: 8 r: t0 R: t1. + b557 := self Label. + self MoveR: t1 R: t0. + self AndCq: 7 R: t0. + self CmpCq: 0 R: t0. + jump2 := self JumpNonZero: 0. + self MoveM64: 0 r: t1 R: t0. + self AndCq: 16r3FFFF7 R: t0. + self CmpCq: 0 R: t0. + jump3 := self JumpNonZero: 0. + self MoveM64: 8 r: t1 R: t0. + self MoveR: t0 R: t1. + jump4 := self Jump: b557. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + jump3 jmpTarget: currentBlock. + self MoveR: t1 R: t0. + jump3 := self Jump: 0. + currentBlock := self Label. + jump1 jmpTarget: currentBlock. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + (self ssValue: 0) copyToReg: t1. + self MoveR: t0 R: t2. + self AndCq: 7 R: t2. + self ssFlushStackExceptTop: 0. + self CmpCq: 0 R: t2. + jump3 := self JumpNonZero: 0. + s38 := objectMemory getMemoryMap getSpaceMaskToUse. + self MoveR: t0 R: t2. + self AndCq: s38 R: t2. + s41 := objectMemory getMemoryMap getOldSpaceMask. + self CmpCq: s41 R: t2. + jump1 := self JumpNonZero: 0. + self MoveR: t1 R: t2. + self AndCq: 7 R: t2. + self CmpCq: 0 R: t2. + jump2 := self JumpNonZero: 0. + s46 := objectMemory getMemoryMap getSpaceMaskToUse. + self MoveR: t1 R: t2. + self AndCq: s46 R: t2. + s49 := objectMemory getMemoryMap getNewSpaceMask. + self CmpCq: s49 R: t2. + jump5 := self JumpNonZero: 0. + s51 := objectMemory getMemoryMap getNewSpaceStart. + self MoveR: t1 R: t2. + self CmpCq: s51 R: t2. + jumpTrue := self JumpAboveOrEqual: 0. + self MoveCq: 0 R: t2. + jumpNext := self Jump: 0. + jumpTrue jmpTarget: self Label. + self MoveCq: 1 R: t2. + jumpNext jmpTarget: self Label. + self CmpCq: 1 R: t2. + jump6 := self JumpNonZero: 0. + self MoveM64: 0 r: t0 R: t2. + self LogicalShiftRightCq: 29 R: t2. + self AndCq: 1 R: t2. + self CmpCq: 0 R: t2. + jump7 := self JumpNonZero: 0. + self MoveR: t0 R: TempReg. + backEnd saveAndRestoreLinkRegAround: [ + self CallRT: ceStoreCheckTrampoline ]. + jump8 := self Jump: 0. + currentBlock := self Label. + jump5 jmpTarget: currentBlock. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + jump1 jmpTarget: currentBlock. + jump2 jmpTarget: currentBlock. + jump6 jmpTarget: currentBlock. + jump7 jmpTarget: currentBlock. + jump8 jmpTarget: currentBlock. + self MoveM64: 0 r: t0 R: t2. + self LogicalShiftRightCq: 29 R: t2. + self AndCq: 1 R: t2. + self CmpCq: 0 R: t2. + jump8 := self JumpNonZero: 0. + self TstCq: 7 R: t1. + jump7 := self JumpNonZero: 0. + self CmpCq: 16r20000000000 R: t0. + jump6 := self JumpLess: 0. + self CmpCq: 16r20000000000 R: t1. + jump2 := self JumpGreaterOrEqual: 0. + self genMoveConstant: objectMemory nilObject R: t2. + self CmpR: t2 R: t1. + jump1 := self JumpBelow: 0. + s73 := objectMemory trueObject. + self CmpCq: s73 R: t1. + jump3 := self JumpBelowOrEqual: 0. + currentBlock := self Label. + jump1 jmpTarget: currentBlock. + s75 := objectMemory getMemoryMap getNewSpaceStart. + self CmpCq: s75 R: t1. + jump1 := self JumpBelow: 0. + self MoveR: t0 R: TempReg. + backEnd saveAndRestoreLinkRegAround: [ + self CallRT: ceStoreCheckTrampoline ]. + currentBlock := self Label. + jump8 jmpTarget: currentBlock. + jump7 jmpTarget: currentBlock. + jump6 jmpTarget: currentBlock. + jump2 jmpTarget: currentBlock. + jump3 jmpTarget: currentBlock. + jump1 jmpTarget: currentBlock. + s79 := s3 << 3. + self AddCq: s79 R: t0. + self MoveR: t1 M64: 8 r: t0. + self ssPop: 1 popSpilled: true. + ^ 0 ]. + (self ssValue: 0) copyToReg: t1. + self MoveR: t0 R: t2. + self AndCq: 7 R: t2. + self ssFlushStackExceptTop: 0. + self CmpCq: 0 R: t2. + jump1 := self JumpNonZero: 0. + s38 := objectMemory getMemoryMap getSpaceMaskToUse. + self MoveR: t0 R: t2. + self AndCq: s38 R: t2. + s41 := objectMemory getMemoryMap getOldSpaceMask. + self CmpCq: s41 R: t2. + jump3 := self JumpNonZero: 0. + self MoveR: t1 R: t2. + self AndCq: 7 R: t2. + self CmpCq: 0 R: t2. + jump2 := self JumpNonZero: 0. + s46 := objectMemory getMemoryMap getSpaceMaskToUse. + self MoveR: t1 R: t2. + self AndCq: s46 R: t2. + s49 := objectMemory getMemoryMap getNewSpaceMask. + self CmpCq: s49 R: t2. + jump6 := self JumpNonZero: 0. + s51 := objectMemory getMemoryMap getNewSpaceStart. + self MoveR: t1 R: t2. + self CmpCq: s51 R: t2. + jumpTrue := self JumpAboveOrEqual: 0. + self MoveCq: 0 R: t2. + jumpNext := self Jump: 0. + jumpTrue jmpTarget: self Label. + self MoveCq: 1 R: t2. + jumpNext jmpTarget: self Label. + self CmpCq: 1 R: t2. + jump7 := self JumpNonZero: 0. + self MoveM64: 0 r: t0 R: t2. + self LogicalShiftRightCq: 29 R: t2. + self AndCq: 1 R: t2. + self CmpCq: 0 R: t2. + jump8 := self JumpNonZero: 0. + self MoveR: t0 R: TempReg. + backEnd saveAndRestoreLinkRegAround: [ + self CallRT: ceStoreCheckTrampoline ]. + jump5 := self Jump: 0. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + currentBlock := self Label. + jump1 jmpTarget: currentBlock. + jump3 jmpTarget: currentBlock. + jump2 jmpTarget: currentBlock. + jump7 jmpTarget: currentBlock. + jump8 jmpTarget: currentBlock. + jump5 jmpTarget: currentBlock. + self MoveM64: 0 r: t0 R: t2. + self LogicalShiftRightCq: 29 R: t2. + self AndCq: 1 R: t2. + self CmpCq: 0 R: t2. + jump5 := self JumpNonZero: 0. + self TstCq: 7 R: t1. + jump8 := self JumpNonZero: 0. + self CmpCq: 16r20000000000 R: t0. + jump7 := self JumpLess: 0. + self CmpCq: 16r20000000000 R: t1. + jump2 := self JumpGreaterOrEqual: 0. + self genMoveConstant: objectMemory nilObject R: t2. + self CmpR: t2 R: t1. + jump3 := self JumpBelow: 0. + s73 := objectMemory trueObject. + self CmpCq: s73 R: t1. + jump1 := self JumpBelowOrEqual: 0. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + s75 := objectMemory getMemoryMap getNewSpaceStart. + self CmpCq: s75 R: t1. + jump3 := self JumpBelow: 0. + self MoveR: t0 R: TempReg. + backEnd saveAndRestoreLinkRegAround: [ + self CallRT: ceStoreCheckTrampoline ]. + currentBlock := self Label. + jump5 jmpTarget: currentBlock. + jump8 jmpTarget: currentBlock. + jump7 jmpTarget: currentBlock. + jump2 jmpTarget: currentBlock. + jump1 jmpTarget: currentBlock. + jump3 jmpTarget: currentBlock. + s79 := s3 << 3. + self AddCq: s79 R: t0. + self MoveR: t1 M64: 8 r: t0. + self ssPop: 1 popSpilled: true. + ^ 0 +] + { #category : #query } DruidTestRTLCompiler >> hasAnnotatedAbstractInstructions: annotation [ diff --git a/Druid-Tests/SimpleDruidTestRTLCompiler.class.st b/Druid-Tests/SimpleDruidTestRTLCompiler.class.st index 4b11d308..faecbf6c 100644 --- a/Druid-Tests/SimpleDruidTestRTLCompiler.class.st +++ b/Druid-Tests/SimpleDruidTestRTLCompiler.class.st @@ -7367,6 +7367,379 @@ SimpleDruidTestRTLCompiler >> gen_storeAndPopReceiverVariableBytecode [ ^ 0 ] +{ #category : #generated } +SimpleDruidTestRTLCompiler >> gen_storeAndPopRemoteTempLongBytecode [ + "AutoGenerated by Druid" + + | s6 t5 jump5 jump3 t3 s44 s14 s62 s2 t1 currentBlock jump8 jump1 s67 s60 jumpNext jump6 s163 s47 s146 t4 s5 jumpTrue s3 t2 jump2 jump7 t0 s57 | + self SubCq: 8 R: SPReg. + t0 := ClassReg. + t1 := SendNumArgsReg. + t2 := Extra3Reg. + t3 := Extra1Reg. + t4 := Extra2Reg. + t5 := Extra0Reg. + self annotateBytecode: self Label. + s3 := byte1. + self + MoveMw: (self frameOffsetOfTemporary: byte2) + r: FPReg + R: ClassReg. + s5 := TempVectReadBarrier. + s5 ifTrue: [ + | jump1 b557 jumpNext jump6 jump3 jump8 jump5 jumpTrue jump2 jump7 jump4 | + self MoveM64: 0 r: t0 R: t1. + self AndCq: 16r3FFFF7 R: t1. + self CmpCq: 0 R: t1. + jump1 := self JumpNonZero: 0. + self MoveM64: 8 r: t0 R: t1. + b557 := self Label. + s14 := s3. + self MoveR: t1 R: t0. + self AndCq: 7 R: t0. + self CmpCq: 0 R: t0. + jump2 := self JumpNonZero: 0. + self MoveM64: 0 r: t1 R: t0. + self AndCq: 16r3FFFF7 R: t0. + self CmpCq: 0 R: t0. + jump3 := self JumpNonZero: 0. + self MoveM64: 8 r: t1 R: t0. + self MoveR: t0 R: t1. + jump4 := self Jump: b557. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + jump3 jmpTarget: currentBlock. + self MoveR: t1 R: t0. + self MoveCq: s14 R: t1. + jump3 := self Jump: 0. + currentBlock := self Label. + jump1 jmpTarget: currentBlock. + self MoveCq: s3 R: t1. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + self MoveMw: 8 r: SPReg R: t2. + self MoveR: t2 Mw: 0 r: SPReg. + self MoveR: t0 R: t3. + self AndCq: 7 R: t3. + self CmpCq: 0 R: t3. + jump3 := self JumpNonZero: 0. + s44 := objectMemory getMemoryMap getSpaceMaskToUse. + self MoveR: t0 R: t3. + self AndCq: s44 R: t3. + s47 := objectMemory getMemoryMap getOldSpaceMask. + self CmpCq: s47 R: t3. + jumpTrue := self JumpZero: 0. + self MoveCq: 0 R: t3. + jumpNext := self Jump: 0. + jumpTrue jmpTarget: self Label. + self MoveCq: 1 R: t3. + jumpNext jmpTarget: self Label. + self CmpCq: 1 R: t3. + jump1 := self JumpNonZero: 0. + self MoveR: t1 R: t3. + self MoveMw: 0 r: SPReg R: t2. + self MoveR: t2 R: t1. + self MoveR: t1 R: t4. + self AndCq: 7 R: t4. + self CmpCq: 0 R: t4. + jump2 := self JumpNonZero: 0. + s57 := objectMemory getMemoryMap getSpaceMaskToUse. + self MoveR: t1 R: t4. + self AndCq: s57 R: t4. + s60 := objectMemory getMemoryMap getNewSpaceMask. + self CmpCq: s60 R: t4. + jump5 := self JumpNonZero: 0. + s62 := objectMemory getMemoryMap getNewSpaceStart. + self MoveR: t1 R: t4. + self CmpCq: s62 R: t4. + jumpTrue := self JumpAboveOrEqual: 0. + self MoveCq: 0 R: t4. + jumpNext := self Jump: 0. + jumpTrue jmpTarget: self Label. + self MoveCq: 1 R: t4. + jumpNext jmpTarget: self Label. + jump6 := self Jump: 0. + currentBlock := self Label. + jump5 jmpTarget: currentBlock. + s67 := 0. + self MoveCq: s67 R: t4. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + self CmpCq: 1 R: t4. + jump6 := self JumpNonZero: 0. + self MoveR: t1 R: t4. + self MoveM64: 0 r: t0 R: t1. + self LogicalShiftRightCq: 29 R: t1. + self AndCq: 1 R: t1. + self CmpCq: 0 R: t1. + jump5 := self JumpNonZero: 0. + self MoveR: t0 R: TempReg. + backEnd saveAndRestoreLinkRegAround: [ + self CallRT: ceStoreCheckTrampoline ]. + currentBlock := self Label. + jump5 jmpTarget: currentBlock. + self MoveR: t3 R: t1. + jump5 := self Jump: 0. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + self MoveR: t3 R: t4. + self MoveR: t1 R: t3. + jump6 := self Jump: 0. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: t3 R: t4. + self MoveR: t1 R: t3. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + self MoveR: t4 R: t1. + self MoveR: t3 R: t4. + currentBlock := self Label. + jump5 jmpTarget: currentBlock. + self MoveR: t4 R: t3. + jump5 := self Jump: 0. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + jump1 jmpTarget: currentBlock. + self MoveMw: 0 r: SPReg R: t2. + self MoveR: t2 R: t3. + currentBlock := self Label. + jump5 jmpTarget: currentBlock. + self MoveM64: 0 r: t0 R: t4. + self LogicalShiftRightCq: 29 R: t4. + self AndCq: 1 R: t4. + self CmpCq: 0 R: t4. + jump5 := self JumpZero: 0. + self MoveR: t3 R: t4. + jump1 := self Jump: 0. + currentBlock := self Label. + jump5 jmpTarget: currentBlock. + self TstCq: 7 R: t3. + jump5 := self JumpZero: 0. + self MoveR: t3 R: t4. + jump3 := self Jump: 0. + currentBlock := self Label. + jump5 jmpTarget: currentBlock. + self CmpCq: 16r20000000000 R: t0. + jump5 := self JumpLess: 0. + self CmpCq: 16r20000000000 R: t3. + jump6 := self JumpBelow: 0. + self MoveR: t3 R: t4. + jump2 := self Jump: 0. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + self genMoveConstant: objectMemory nilObject R: t4. + self CmpR: t4 R: t3. + jump6 := self JumpBelow: 0. + s146 := objectMemory trueObject. + self MoveR: t3 R: t4. + self CmpCq: s146 R: t4. + jumpTrue := self JumpBelowOrEqual: 0. + self MoveCq: 0 R: t4. + jumpNext := self Jump: 0. + jumpTrue jmpTarget: self Label. + self MoveCq: 1 R: t4. + jumpNext jmpTarget: self Label. + self CmpCq: 1 R: t4. + jump7 := self JumpNonZero: 0. + self MoveR: t3 R: t4. + jump8 := self Jump: 0. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + jump7 jmpTarget: currentBlock. + self MoveR: t0 R: t4. + self MoveR: t3 R: t5. + s163 := objectMemory getMemoryMap getNewSpaceStart. + self CmpCq: s163 R: t5. + jump7 := self JumpBelow: 0. + self MoveR: t4 R: TempReg. + backEnd saveAndRestoreLinkRegAround: [ + self CallRT: ceStoreCheckTrampoline ]. + self MoveR: t3 R: t4. + jump6 := self Jump: 0. + currentBlock := self Label. + jump7 jmpTarget: currentBlock. + self MoveR: t3 R: t4. + jump7 := self Jump: 0. + currentBlock := self Label. + jump5 jmpTarget: currentBlock. + self MoveR: t3 R: t4. + currentBlock := self Label. + jump1 jmpTarget: currentBlock. + jump3 jmpTarget: currentBlock. + jump2 jmpTarget: currentBlock. + jump8 jmpTarget: currentBlock. + jump6 jmpTarget: currentBlock. + jump7 jmpTarget: currentBlock. + self LogicalShiftLeftCq: 3 R: t1. + self AddR: t1 R: t0. + self MoveR: t4 M64: 8 r: t0. + self MoveMw: 0 r: SPReg R: t2. + self PopN: 1. + self AddCq: 8 R: SPReg. + ^ 0 ]. + self MoveCq: s3 R: t1. + self MoveMw: 8 r: SPReg R: t2. + self MoveR: t2 Mw: 0 r: SPReg. + self MoveR: t0 R: t3. + self AndCq: 7 R: t3. + self CmpCq: 0 R: t3. + jump7 := self JumpNonZero: 0. + s44 := objectMemory getMemoryMap getSpaceMaskToUse. + self MoveR: t0 R: t3. + self AndCq: s44 R: t3. + s47 := objectMemory getMemoryMap getOldSpaceMask. + self CmpCq: s47 R: t3. + jumpTrue := self JumpZero: 0. + self MoveCq: 0 R: t3. + jumpNext := self Jump: 0. + jumpTrue jmpTarget: self Label. + self MoveCq: 1 R: t3. + jumpNext jmpTarget: self Label. + self CmpCq: 1 R: t3. + jump6 := self JumpNonZero: 0. + self MoveR: t1 R: t3. + self MoveMw: 0 r: SPReg R: t2. + self MoveR: t2 R: t1. + self MoveR: t1 R: t4. + self AndCq: 7 R: t4. + self CmpCq: 0 R: t4. + jump8 := self JumpNonZero: 0. + s57 := objectMemory getMemoryMap getSpaceMaskToUse. + self MoveR: t1 R: t4. + self AndCq: s57 R: t4. + s60 := objectMemory getMemoryMap getNewSpaceMask. + self CmpCq: s60 R: t4. + jump2 := self JumpNonZero: 0. + s62 := objectMemory getMemoryMap getNewSpaceStart. + self MoveR: t1 R: t4. + self CmpCq: s62 R: t4. + jumpTrue := self JumpAboveOrEqual: 0. + self MoveCq: 0 R: t4. + jumpNext := self Jump: 0. + jumpTrue jmpTarget: self Label. + self MoveCq: 1 R: t4. + jumpNext jmpTarget: self Label. + jump3 := self Jump: 0. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + s67 := 0. + self MoveCq: s67 R: t4. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + self CmpCq: 1 R: t4. + jump3 := self JumpNonZero: 0. + self MoveR: t1 R: t4. + self MoveM64: 0 r: t0 R: t1. + self LogicalShiftRightCq: 29 R: t1. + self AndCq: 1 R: t1. + self CmpCq: 0 R: t1. + jump2 := self JumpNonZero: 0. + self MoveR: t0 R: TempReg. + backEnd saveAndRestoreLinkRegAround: [ + self CallRT: ceStoreCheckTrampoline ]. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: t3 R: t1. + jump2 := self Jump: 0. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + self MoveR: t3 R: t4. + self MoveR: t1 R: t3. + jump3 := self Jump: 0. + currentBlock := self Label. + jump8 jmpTarget: currentBlock. + self MoveR: t3 R: t4. + self MoveR: t1 R: t3. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + self MoveR: t4 R: t1. + self MoveR: t3 R: t4. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: t4 R: t3. + jump2 := self Jump: 0. + currentBlock := self Label. + jump7 jmpTarget: currentBlock. + jump6 jmpTarget: currentBlock. + self MoveMw: 0 r: SPReg R: t2. + self MoveR: t2 R: t3. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveM64: 0 r: t0 R: t4. + self LogicalShiftRightCq: 29 R: t4. + self AndCq: 1 R: t4. + self CmpCq: 0 R: t4. + jump2 := self JumpZero: 0. + self MoveR: t3 R: t4. + jump6 := self Jump: 0. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self TstCq: 7 R: t3. + jump2 := self JumpZero: 0. + self MoveR: t3 R: t4. + jump7 := self Jump: 0. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self CmpCq: 16r20000000000 R: t0. + jump2 := self JumpLess: 0. + self CmpCq: 16r20000000000 R: t3. + jump3 := self JumpBelow: 0. + self MoveR: t3 R: t4. + jump8 := self Jump: 0. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + self genMoveConstant: objectMemory nilObject R: t4. + self CmpR: t4 R: t3. + jump3 := self JumpBelow: 0. + s146 := objectMemory trueObject. + self MoveR: t3 R: t4. + self CmpCq: s146 R: t4. + jumpTrue := self JumpBelowOrEqual: 0. + self MoveCq: 0 R: t4. + jumpNext := self Jump: 0. + jumpTrue jmpTarget: self Label. + self MoveCq: 1 R: t4. + jumpNext jmpTarget: self Label. + self CmpCq: 1 R: t4. + jump1 := self JumpNonZero: 0. + self MoveR: t3 R: t4. + jump5 := self Jump: 0. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. + jump1 jmpTarget: currentBlock. + self MoveR: t0 R: t4. + self MoveR: t3 R: t5. + s163 := objectMemory getMemoryMap getNewSpaceStart. + self CmpCq: s163 R: t5. + jump1 := self JumpBelow: 0. + self MoveR: t4 R: TempReg. + backEnd saveAndRestoreLinkRegAround: [ + self CallRT: ceStoreCheckTrampoline ]. + self MoveR: t3 R: t4. + jump3 := self Jump: 0. + currentBlock := self Label. + jump1 jmpTarget: currentBlock. + self MoveR: t3 R: t4. + jump1 := self Jump: 0. + currentBlock := self Label. + jump2 jmpTarget: currentBlock. + self MoveR: t3 R: t4. + currentBlock := self Label. + jump6 jmpTarget: currentBlock. + jump7 jmpTarget: currentBlock. + jump8 jmpTarget: currentBlock. + jump5 jmpTarget: currentBlock. + jump3 jmpTarget: currentBlock. + jump1 jmpTarget: currentBlock. + self LogicalShiftLeftCq: 3 R: t1. + self AddR: t1 R: t0. + self MoveR: t4 M64: 8 r: t0. + self MoveMw: 0 r: SPReg R: t2. + self PopN: 1. + self AddCq: 8 R: SPReg. + ^ 0 +] + { #category : #query } SimpleDruidTestRTLCompiler >> hasAnnotatedAbstractInstructions: annotation [ From eaf1e44572bc1fe5835b5ee08f27f67908b03241 Mon Sep 17 00:00:00 2001 From: palumbon Date: Thu, 3 Oct 2024 18:44:36 +0200 Subject: [PATCH 18/20] Ups, missing extension --- Druid-Tests/SimpleStackBasedCogit.extension.st | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 Druid-Tests/SimpleStackBasedCogit.extension.st diff --git a/Druid-Tests/SimpleStackBasedCogit.extension.st b/Druid-Tests/SimpleStackBasedCogit.extension.st new file mode 100644 index 00000000..d5d626fb --- /dev/null +++ b/Druid-Tests/SimpleStackBasedCogit.extension.st @@ -0,0 +1,7 @@ +Extension { #name : #SimpleStackBasedCogit } + +{ #category : #'*Druid-Tests' } +SimpleStackBasedCogit >> byte2: anInteger [ + + byte2 := anInteger +] From f8573f018f36271eed3bdf238b55c8baa64ab8c2 Mon Sep 17 00:00:00 2001 From: palumbon Date: Thu, 14 Nov 2024 15:05:15 +0100 Subject: [PATCH 19/20] Hi SimpleDruidStaticTypePredictionJIT --- Druid-Tests/DruidTestRTLCompiler.class.st | 35 +++++++++++++++++++++-- Druid/DRInterpreterToCompiler.class.st | 10 +++++++ 2 files changed, 43 insertions(+), 2 deletions(-) diff --git a/Druid-Tests/DruidTestRTLCompiler.class.st b/Druid-Tests/DruidTestRTLCompiler.class.st index a35dcb3d..8e3a558a 100644 --- a/Druid-Tests/DruidTestRTLCompiler.class.st +++ b/Druid-Tests/DruidTestRTLCompiler.class.st @@ -901,16 +901,47 @@ DruidTestRTLCompiler >> gen_bytecodePopOnTwoBranches [ DruidTestRTLCompiler >> gen_bytecodePrimAdd [ "AutoGenerated by Druid" - | live currentBlock | + | t0 jump3 jump1 t1 currentBlock jump2 live t2 | live := 0. + t0 := self + allocateRegNotConflictingWith: live + ifNone: [ ^ self unknownBytecode ]. + live := live bitOr: (self registerMaskFor: t0). + t1 := self + allocateRegNotConflictingWith: live + ifNone: [ ^ self unknownBytecode ]. + live := live bitOr: (self registerMaskFor: t1). + t2 := self + allocateRegNotConflictingWith: live + ifNone: [ ^ self unknownBytecode ]. + live := live bitOr: (self registerMaskFor: t2). + (self ssValue: 1) copyToReg: t0. + (self ssValue: 0) copyToReg: t1. + self MoveR: t0 R: t2. + self AndR: t1 R: t2. self ssFlushStackExceptTop: 2. + self TstCq: 1 R: t2. + jump1 := self JumpZero: 0. + self AddCq: -1 R: t0. + self AddR: t1 R: t0. + jump2 := self JumpOverflow: 0. + self ssUnspillStackSlotAt: 0. + self ssUnspillStackSlotAt: 1. + self MoveR: t0 R: t2. + jump3 := self Jump: 0. + currentBlock := self Label. + jump1 jmpTarget: currentBlock. + jump2 jmpTarget: currentBlock. self marshallSendArgumentsNoPush: 1. self genMarshalledSendNoPush: -1 numArgs: 1 sendTable: ordinarySendTrampolines. + self MoveR: ReceiverResultReg R: t2. + currentBlock := self Label. + jump3 jmpTarget: currentBlock. self ssPop: 2 popSpilled: false. - self ssPushRegister: ReceiverResultReg. + self ssPushRegister: t2. ^ 0 ] diff --git a/Druid/DRInterpreterToCompiler.class.st b/Druid/DRInterpreterToCompiler.class.st index 7658ffd2..4bfd9f00 100644 --- a/Druid/DRInterpreterToCompiler.class.st +++ b/Druid/DRInterpreterToCompiler.class.st @@ -201,6 +201,16 @@ DRInterpreterToCompiler class >> generateSimpleDruidJITModel [ superclass: SimpleStackBasedCogit ] +{ #category : #'instance creation' } +DRInterpreterToCompiler class >> generateSimpleDruidStaticTypePredictionJITModel [ + +