OpenFPGA_Pong_Quartus.ipynb

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  "nbformat_minor": 0,
  "metadata": {
    "colab": {
      "provenance": [],
      "authorship_tag": "ABX9TyPalF9STcyKhpvCvHVyYG+t",
      "include_colab_link": true
    },
    "kernelspec": {
      "name": "python3",
      "display_name": "Python 3"
    },
    "language_info": {
      "name": "python"
    }
  },
  "cells": [
    {
      "cell_type": "markdown",
      "metadata": {
        "id": "view-in-github",
        "colab_type": "text"
      },
      "source": [
        "<a href=\"https://colab.research.google.com/github/AEW2015/fpga-colab/blob/main/OpenFPGA_Pong_Quartus.ipynb\" target=\"_parent\"><img src=\"https://colab.research.google.com/assets/colab-badge.svg\" alt=\"Open In Colab\"/></a>"
      ]
    },
    {
      "cell_type": "markdown",
      "source": [
        "# OpenFPGA Pong Quartus Build"
      ],
      "metadata": {
        "id": "eE5qeoJkeDl8"
      }
    },
    {
      "cell_type": "markdown",
      "source": [
        "Download Quartus Lite 22.1"
      ],
      "metadata": {
        "id": "UTH_3Q9CeK_S"
      }
    },
    {
      "cell_type": "code",
      "execution_count": 1,
      "metadata": {
        "colab": {
          "base_uri": "https://localhost:8080/"
        },
        "id": "BXQJITSiY7u4",
        "outputId": "0556f93f-d583-4327-93cd-5fe56f0633f7"
      },
      "outputs": [
        {
          "output_type": "stream",
          "name": "stdout",
          "text": [
            "--2023-01-10 03:43:11--  https://downloads.intel.com/akdlm/software/acdsinst/22.1std/915/ib_tar/Quartus-lite-22.1std.0.915-linux.tar\n",
            "Resolving downloads.intel.com (downloads.intel.com)... 23.220.150.28, 2600:141b:e800:1489::b, 2600:141b:e800:148f::b\n",
            "Connecting to downloads.intel.com (downloads.intel.com)|23.220.150.28|:443... connected.\n",
            "HTTP request sent, awaiting response... 200 OK\n",
            "Length: 7016724480 (6.5G) [application/x-tar]\n",
            "Saving to: ‘Quartus-lite-22.1std.0.915-linux.tar’\n",
            "\n",
            "Quartus-lite-22.1st 100%[===================>]   6.53G  91.2MB/s    in 52s     \n",
            "\n",
            "2023-01-10 03:44:03 (130 MB/s) - ‘Quartus-lite-22.1std.0.915-linux.tar’ saved [7016724480/7016724480]\n",
            "\n"
          ]
        }
      ],
      "source": [
        "! wget https://downloads.intel.com/akdlm/software/acdsinst/22.1std/915/ib_tar/Quartus-lite-22.1std.0.915-linux.tar"
      ]
    },
    {
      "cell_type": "code",
      "source": [
        "! mkdir quartus_install"
      ],
      "metadata": {
        "id": "_3XkFHdiZGHp"
      },
      "execution_count": 2,
      "outputs": []
    },
    {
      "cell_type": "code",
      "source": [
        "! tar xf /content/Quartus-lite-22.1std.0.915-linux.tar -C /content/quartus_install"
      ],
      "metadata": {
        "id": "Hmmp01AbZINc"
      },
      "execution_count": 3,
      "outputs": []
    },
    {
      "cell_type": "code",
      "source": [
        "%cd /content/quartus_install/"
      ],
      "metadata": {
        "colab": {
          "base_uri": "https://localhost:8080/"
        },
        "id": "AvwZIfB-ZJhZ",
        "outputId": "4178b129-d5f7-4b05-bff8-4cda2c675754"
      },
      "execution_count": 4,
      "outputs": [
        {
          "output_type": "stream",
          "name": "stdout",
          "text": [
            "/content/quartus_install\n"
          ]
        }
      ]
    },
    {
      "cell_type": "markdown",
      "source": [
        "Auto script to install Quartus with Cyclone V.  By running this, you agree to their License Agreement!"
      ],
      "metadata": {
        "id": "SufWYKj7djRV"
      }
    },
    {
      "cell_type": "code",
      "source": [
        "! printf \"\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\n\\ny\\n\\ny\\nn\\ny\\nn\\nn\\nn\\ny\\nn\\nn\\ny\\nn\\ny\\nn\\nn\\nn\\n\" | ./setup.sh"
      ],
      "metadata": {
        "colab": {
          "base_uri": "https://localhost:8080/"
        },
        "id": "0ItXeGE7ZLMB",
        "outputId": "88534082-1e80-416e-c446-bd1fc9972a1b"
      },
      "execution_count": 5,
      "outputs": [
        {
          "output_type": "stream",
          "name": "stdout",
          "text": [
            "Warning: This installer detects you either don't have a display set up or don't \r\n",
            "have the necessary GUI libraries installed, this installation will run in \r\n",
            "console mode.\r\n",
            "Press [Enter] to continue:----------------------------------------------------------------------------\r\n",
            "Welcome to the Quartus Prime Lite Edition (Free) 22.1std.0.915 Setup Wizard.\r\n",
            "\r\n",
            "The Quartus Prime software requires that your system have sufficient physical \r\n",
            "RAM to compile designs targeting specific devices. You can check the \"Memory \r\n",
            "Recommendations\" section in the \"Quartus Prime Software and Device Support \r\n",
            "Release Notes\" (https://www.intel.com/content/www/us/en/programmable/ \r\n",
            "documentation/lit-rn.html) for detailed memory requirements for a particular \r\n",
            "device.\r\n",
            "\r\n",
            "For more information about Intel FPGA software, go to \r\n",
            "https://www.intel.com/content/www/us/en/products/ programmable.html.\r\n",
            "\r\n",
            "\r\n",
            "----------------------------------------------------------------------------\r\n",
            "License Agreement\r\n",
            "\r\n",
            "You can view the full license agreement at the link below or use --install_lic \r\n",
            "option from command-line to get the license agreement files before the \r\n",
            "installation. You must accept the terms of the agreement before continuing with \r\n",
            "the installation.\r\n",
            "\r\n",
            "http://fpgasoftware.intel.com/eula/\r\n",
            "\r\n",
            "----------------------------------------------------------------------------\r\n",
            "\r\n",
            "\r\n",
            "Press [Enter] to continue:QUARTUS PRIME AND INTEL FPGA IP LICENSE AGREEMENT, VERSION 22.1std\r\n",
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            "1.6. \"Derivative Works\" means a derivative work, as defined in 17\r\n",
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            "which the License Key management software will be installed.\r\n",
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            "1.8. \"Devices\" means Intel FPGA's or Intel complex programmable logic\r\n",
            "devices.\r\n",
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            "1.9. \"Documentation\" means Intel-provided technical data (including,\r\n",
            "but not limited to manuals, release notes, advisories, etc.) which:\r\n",
            "(i) provides operating instructions for using or (ii) explains the\r\n",
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            "1.11. \"Feedback\" means materials, information, comments, suggestions,\r\n",
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            "use of the Licensed Software\r\n",
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            "1.12. \"Fixed with Companion License\" means a license to install: (i)\r\n",
            "the Licensed Software on a fixed standalone computer for use by a\r\n",
            "single User, and (ii) the Licensed Software on up to two companion\r\n",
            "fixed standalone computers. Under this license, only one Seat may be\r\n",
            "Used by a single User at any given time.\r\n",
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            "1.13. \"Floating Node Seat\" is a license that allows the Licensed\r\n",
            "Software to be: (i) installed on and accessed from any number of\r\n",
            "computers on a network environment; (ii) Used by the permitted number\r\n",
            "of Concurrent Users that is equal to the number of Seats licensed as\r\n",
            "determined by the License Key.\r\n",
            "\r\n",
            "1.14. \"FPGA\" means a field programmable gate array.\r\n",
            "\r\n",
            "1.15. \"Infringement Claim\" has the meaning ascribed to it in Section\r\n",
            "7.1.\r\n",
            "Press [Enter] to continue:\r\n",
            "1.16. \"Intel FPGA IP\" means one or more design files, including\r\n",
            "encrypted netlists, RTL, test vectors, simulation models (such as\r\n",
            "VHDL, Verilog HDL, Quartus simulation, Matlab, Simulink, Verisity,\r\n",
            "Specman, Synopsys, and Vera) and other models, each of which may be\r\n",
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            "the design of a specific function into a Device, in the form delivered\r\n",
            "to You by Intel, including any subsequent upgrades or updates\r\n",
            "delivered to You by Intel.\r\n",
            "\r\n",
            "1.17. \"Intel FPGA IP Permitted Derivative Work\" means a Derivative\r\n",
            "Work created by You of any Intel FPGA IP which has been provided to\r\n",
            "You in unencrypted source code format, and is permitted by Section 2.\r\n",
            "\r\n",
            "1.18. \"Intellectual Property Rights\" means all (i) patents, patent\r\n",
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            "\r\n",
            "1.21. \"License Key\" means a FlexNet license key, license file, license\r\n",
            "manager, dongle or other key, code or information provided by Intel\r\n",
            "that: (i) enables a User to download, install, operate and/or regulate\r\n",
            "User access to the Licensed Software; (ii) indicates the expiration\r\n",
            "date for the license period for the Licensed Software; and (iii) lists\r\n",
            "the number of Concurrent Users authorized to Use the Licensed\r\n",
            "Software.\r\n",
            "\r\n",
            "Press [Enter] to continue:1.22. \"Licensed Product\" means any Device (i) which You or an\r\n",
            "Authorized Contractor have designed pursuant to the license grants to\r\n",
            "Quartus Prime in Section 2, and/or (ii) in which You or an Authorized\r\n",
            "Contractor have implemented or programmed Intel FPGA IP pursuant to\r\n",
            "the license grants to Intel FPGA IP in Section 2.\r\n",
            "\r\n",
            "1.23. \"Licensed Software\" means the version(s) of (i) Quartus Prime\r\n",
            "and/or (ii) Intel FPGA IP(s) enabled for You via the License Key.\r\n",
            "Licensed Software does not include Unlicensed Software or Third Party\r\n",
            "Materials.\r\n",
            "\r\n",
            "1.24. \"NDA\" has the meaning ascribed to it in Section 5.\r\n",
            "\r\n",
            "1.25. \"Open Source Software\" means any software that requires as a\r\n",
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            "or distributed with such software: (a) be disclosed or distributed in\r\n",
            "source code form; (b) be licensed for the purpose of making Derivative\r\n",
            "Works; and (c) be redistributable at no charge. Open Source Software\r\n",
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            "Netscape Public License; (v) the Sun Community Source License (SCSL);\r\n",
            "(vi) the Sun Industry Source License (SISL); and (vii) the Common\r\n",
            "Public License (CPL). The Open Source Software components associated\r\n",
            "with the Licensed Software and their corresponding license terms may\r\n",
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            "that is provided with the Licensed Software.\r\n",
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            "1.26. \"Quartus Prime\" means the Quartus Software Suite(R), in the form\r\n",
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            "Fixed with Companion License, which is enabled via a License Key.\r\n",
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            "capabilities and functions of such items, and any full or partial\r\n",
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            "Press [Enter] to continue:\r\n",
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            "similar group or entity that creates technology specifications to be\r\n",
            "used by others.  Examples of Standards include GSM, LTE, 5G, Wi-Fi,\r\n",
            "CDMA, MPEG, and HTML.  Examples of groups that create Standards\r\n",
            "include IEEE, ITU, 3GPP, and ETSI.\r\n",
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            "1.30. \"Support\" means any support or maintenance services provided to\r\n",
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            "1.31. \"Third Party License\" means a separate license file, header, or\r\n",
            "release note that contain additional terms, conditions or restrictions\r\n",
            "imposed by Third Party Licensors.\r\n",
            "\r\n",
            "1.32. \"Third Party Licensors\" means any third party that licenses or\r\n",
            "provides Third Party Materials to Intel.\r\n",
            "\r\n",
            "1.33. \"Third Party Materials\" means materials or components included\r\n",
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            "Press [Enter] to continue:to, software, code portions or files, which are owned by Third Party\r\n",
            "Licensors, and are provided subject to Third Party Licenses.\r\n",
            "\r\n",
            "1.34. \"Unlicensed Software\" means any Intel computer programs or code\r\n",
            "in any format for which You do not hold an active License Key issued\r\n",
            "by Intel, including but not limited to any non-subscribed or disabled\r\n",
            "features accompanying the Licensed Software.\r\n",
            "\r\n",
            "1.35. \"Use\" means downloading, installing and/or copying all or any\r\n",
            "portion of the Licensed Software into the Designated Equipment for\r\n",
            "processing the instructions contained in the Licensed Software, and/or\r\n",
            "loading data into or displaying, viewing or extracting output results\r\n",
            "from, or otherwise operating, any portion of the Licensed Software.\r\n",
            "\r\n",
            "1.36. \"User\" means each individual identified by You as a person\r\n",
            "authorized to Use the Licensed Software on behalf of and for Your\r\n",
            "benefit, including Your employees and Your Authorized Contractors.\r\n",
            "\r\n",
            "2. Licenses and Restrictions.\r\n",
            "\r\n",
            "2.1. Your License.  Conditioned on Your compliance with the terms and\r\n",
            "conditions of this Agreement, including payment of any applicable\r\n",
            "License Fee, Intel grants to You a limited, nonexclusive,\r\n",
            "Press [Enter] to continue:nontransferable, worldwide, fully paid-up license during the term of\r\n",
            "this Agreement under Intel's copyrights:\r\n",
            "\r\n",
            "(i) in Quartus Prime,\r\n",
            "\r\n",
            "a. to Use Quartus Prime to create, simulate, verify, place and route,\r\n",
            "and program designs on Devices, and\r\n",
            "\r\n",
            "b. to manufacture or have manufactured, market, offer for sale, sell,\r\n",
            "or otherwise distribute or have distributed Licensed Products within\r\n",
            "Your products; and\r\n",
            "\r\n",
            "(ii) in Intel FPGA IP,\r\n",
            "\r\n",
            "a. to Use the Intel FPGA IP to design with, parameterize, compile,\r\n",
            "place and route, and generate programming files and netlists, solely\r\n",
            "for implementation in Devices,\r\n",
            "\r\n",
            "b. to modify and create Derivative Works of any Intel FPGA IP which is\r\n",
            "provided to You in unencrypted source code format in order to create\r\n",
            "Intel FPGA IP Permitted Derivative Works,\r\n",
            "\r\n",
            "c. to program and incorporate the Intel FPGA IP in Devices,\r\n",
            "Press [Enter] to continue:\r\n",
            "d. to manufacture or have manufactured, market, offer for sale, sell,\r\n",
            "or otherwise distribute or have distributed Licensed Products within\r\n",
            "Your products, and,\r\n",
            "\r\n",
            "e. subject to Intel's prior written approval, and upon the negotiation\r\n",
            "of a mutually acceptable agreement and Your payment to Intel of\r\n",
            "additional license fees and/or royalties, to incorporate Intel FPGA IP\r\n",
            "within an approved ASIC for a specific project.\r\n",
            "\r\n",
            "2.2. Use Restrictions. Except as expressly permitted under this\r\n",
            "Agreement, the following restrictions apply to Your use of the\r\n",
            "Licensed Software:\r\n",
            "\r\n",
            "2.2.1. Your Use of the Licensed Software is restricted to any use,\r\n",
            "license or other restrictions agreed to at the time of Your order of\r\n",
            "the License Software (for example but not limited to, quantity,\r\n",
            "duration, number of instantiations and customers).\r\n",
            "2.2.2. You may only use the Licensed Software in accordance with the\r\n",
            "Documentation, including all restrictions on use which may be placed\r\n",
            "in the release notes, advisories, and manuals.\r\n",
            "2.2.3. You may not use, copy, modify, distribute, or otherwise\r\n",
            "transfer the Licensed Software or any portions thereof, or permit any\r\n",
            "Press [Enter] to continue:remote access thereof by any person or entity.\r\n",
            "2.2.4. You may not modify or synthesize any simulation model output\r\n",
            "generated from or resulting from the Licensed Software.\r\n",
            "2.2.5. You may not sublicense or transfer the Licensed Software or any\r\n",
            "rights granted to You under this Agreement.\r\n",
            "2.2.6. No right is granted under this Agreement to Use the Licensed\r\n",
            "Software (including any machine-executable, binary resulting from Use\r\n",
            "of the Licensed Software) to design, develop, incorporate in, or\r\n",
            "program any devices other than Devices.\r\n",
            "2.2.7. You may not decompile, disassemble, reverse engineer, or\r\n",
            "otherwise attempt to access the source code of the Licensed Software\r\n",
            "or reduce it to a human readable form except as otherwise permitted by\r\n",
            "applicable law.\r\n",
            "2.2.8. You may not publish or disclose the results of any benchmarking\r\n",
            "or testing of the Licensed Software or use such results for Your own\r\n",
            "software development activities, without the prior written permission\r\n",
            "of Intel.\r\n",
            "2.2.9. If You have obtained the Licensed Software through the Intel\r\n",
            "FPGA University Program, then You are only permitted to Use the\r\n",
            "Licensed Software for educational and academic purposes and cannot Use\r\n",
            "the Licensed Software for any commercial purposes.\r\n",
            "2.2.10. If You are using Intel FPGA IP pursuant to the Intel FPGA\r\n",
            "Evaluation Mode, Your license is more limited than the license granted\r\n",
            "Press [Enter] to continue:by Intel in Section 2 of this Agreement.   In the Intel FPGA\r\n",
            "Evaluation Mode You may only (i) evaluate the logic designs of Devices\r\n",
            "by performing the following functions:  design entry, timing, place\r\n",
            "and route, compilation and verification of logic designs for Devices;\r\n",
            "and (ii) evaluate the hardware in Devices by programming the Intel\r\n",
            "FPGA IP into such Devices, but only for so long as the Devices are\r\n",
            "continuously connected via a programming cable to a host development\r\n",
            "computer that is running the Intel development tool programmer\r\n",
            "software.    In the Intel FPGA Evaluation Mode, (i) the Intel FPGA IP\r\n",
            "will operate for a predetermined amount of time, after which the Intel\r\n",
            "FPGA IP will be automatically disabled and will be inoperable, and\r\n",
            "(ii) certain features and functions of the Intel FPGA IP may be\r\n",
            "disabled by Intel.  In no event will Intel be held liable for any\r\n",
            "damages or losses to You or any third party resulting from the\r\n",
            "automatic disabling of any Intel FPGA IP during Use in the Intel FPGA\r\n",
            "Evaluation Mode.\r\n",
            "\r\n",
            "2.3. Delivery and License Key. The Licensed Software will be delivered\r\n",
            "electronically and will be deemed accepted upon delivery. In\r\n",
            "accordance with its distribution method, Intel may include with the\r\n",
            "Licensed Software additional Unlicensed Software to which the License\r\n",
            "Key will not permit access. Inclusion of such Unlicensed Software in\r\n",
            "no way implies a license from Intel to access or Use such Unlicensed\r\n",
            "Press [Enter] to continue:Software, and You agree not to access or Use such Unlicensed Software.\r\n",
            "\r\n",
            "2.4. Designated Equipment. In order to generate License Keys, You must\r\n",
            "provide Intel with the Designated Equipment's host identification\r\n",
            "number, which Intel will include in the applicable License Key. You\r\n",
            "may change the Designated Equipment as permitted by the customer self-\r\n",
            "service license center, with further changes permitted only upon\r\n",
            "consent of Intel. Whenever You receive a new License Key in order to\r\n",
            "effect a transfer to new Designated Equipment, You will immediately\r\n",
            "cease to Use the Licensed Software under the previously issued License\r\n",
            "Key. You acknowledge and agree that You will not operate more than the\r\n",
            "number of Seats of the Licensed Software associated with Your License\r\n",
            "Key.\r\n",
            "\r\n",
            "2.5. Floating Node Seat. If You have purchased a Floating Node Seat,\r\n",
            "You may also copy the Licensed Software onto another computer (or\r\n",
            "access it through networked workstations) for Use by another User;\r\n",
            "provided however, that all Users agree to accept the terms and\r\n",
            "conditions of this Agreement in writing prior to Using the Licensed\r\n",
            "Software.\r\n",
            "\r\n",
            "2.6. Authorized Contractors. You may permit Authorized Contractors to\r\n",
            "perform services on Your behalf solely under the licenses granted to\r\n",
            "Press [Enter] to continue:You in Section 2. You agree that all access to or Use of the Licensed\r\n",
            "Software by an Authorized Contractor is subject to the following: (i)\r\n",
            "such access and/or Use will be for Your sole benefit; (ii) a breach of\r\n",
            "this Agreement or the terms of any other Intel agreement by the\r\n",
            "Authorized Contractor will be deemed to be a breach of such\r\n",
            "agreement(s) by You, and You will be liable for any such breaches by\r\n",
            "the Authorized Contractor and will indemnify Intel for any damages\r\n",
            "suffered by Intel as a result of such breaches; and (iii) You will\r\n",
            "ensure that in no event will any such Authorized Contractor be a\r\n",
            "competitor of Intel for Devices.\r\n",
            "\r\n",
            "2.7. Third Party Materials.\r\n",
            "\r\n",
            "2.7.1. Third Party Materials may be provided in the download for use\r\n",
            "with the Licensed Software.  The Third Party Materials are licensed to\r\n",
            "You pursuant to the terms of the applicable Third Party License.  The\r\n",
            "Third Party Materials and Third Party Licenses are identified either\r\n",
            "in the documentation accompanying the Licensed Software, hyperlinks\r\n",
            "included with this Agreement or Readme files included with the\r\n",
            "Licensed Software.  You agree to carefully review and fully comply\r\n",
            "with the terms of such Third Party Licenses.\r\n",
            "\r\n",
            "2.7.2. Third Party Materials Disclaimer. NOTWITHSTANDING ANYTHING TO\r\n",
            "Press [Enter] to continue:THE CONTRARY IN THE AGREEMENT, AS BETWEEN YOU AND INTEL, AND TO THE\r\n",
            "MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, ALL THIRD PARTY LICENSES\r\n",
            "WILL BE SUBJECT TO SECTION 6.2 (DISCLAIMER OF WARRANTIES); SECTION 10\r\n",
            "(LIMITATION OF LIABILITY); AND SECTION 11 (CHOICE OF LAW/VENUE). INTEL\r\n",
            "OFFERS NO WARRANTIES (WHETHER EXPRESS OR IMPLIED); INDEMNIFICATION;\r\n",
            "AND/OR SUPPORT OF ANY KIND WITH RESPECT TO THIRD PARTY MATERIALS,\r\n",
            "EXCEPT THAT INTEL WILL PASS THROUGH TO YOU, IF AND TO THE EXTENT\r\n",
            "AVAILABLE, ANY WARRANTIES EXPRESSLY PROVIDED TO INTEL BY THIRD PARTY\r\n",
            "LICENSORS RELATING TO SUCH THIRD PARTY MATERIALS.\r\n",
            "\r\n",
            "2.8. Open Source Statement. The Licensed Software may include Open\r\n",
            "Source Software licensed pursuant to an Open Source Software license\r\n",
            "agreement(s) identified in in the applicable source code file(s) or\r\n",
            "file header(s) provided with or otherwise associated with the Licensed\r\n",
            "Software. Neither You, nor any OEM, ODM, customer, or distributor may\r\n",
            "subject any proprietary portion of the Licensed Software to any Open\r\n",
            "Source Software license obligations including, without limitation,\r\n",
            "combining or distributing the Licensed Software with Open Source\r\n",
            "Software in a manner that subjects Intel, the Licensed Software or any\r\n",
            "portion thereof to any Open Source Software license obligation.\r\n",
            "Nothing in this Agreement limits any rights under, or grants rights\r\n",
            "that supersede, the terms of any applicable Open Source Software\r\n",
            "license.\r\n",
            "Press [Enter] to continue:\r\n",
            "2.9. Intellectual Property Rights Notices. Any copies of the Licensed\r\n",
            "Software made by or for You must include all Intellectual Property\r\n",
            "Rights notices. You will not, and will cause Your Authorized\r\n",
            "Contractors and Your customers and/or end users not to, remove any\r\n",
            "Intel Intellectual Property Rights notices or other proprietary\r\n",
            "markings from the Licensed Software. Any copy of the Licensed Software\r\n",
            "or portions thereof, including but not limited to any modified\r\n",
            "versions, Derivative Works, any portion merged into a design, and/or\r\n",
            "any design or product that incorporates all or any portion of the\r\n",
            "Licensed Software, will continue to be subject to the terms and\r\n",
            "conditions of this Agreement.\r\n",
            "\r\n",
            "2.10. Feedback. This Agreement does not obligate You to provide Intel\r\n",
            "with Feedback. To the extent You provide Intel with Feedback in a\r\n",
            "tangible form, You grant to Intel and its affiliates a non-exclusive,\r\n",
            "perpetual, sublicenseable, irrevocable, worldwide, royalty-free, fully\r\n",
            "paid-up and transferable license, to and under all of Your\r\n",
            "intellectual property rights, whether perfected or not, to publicly\r\n",
            "perform, publicly display, reproduce, use, make, have made, sell,\r\n",
            "offer for sale, sublicense, distribute, import, create Derivative\r\n",
            "Works of and otherwise exploit any comments, suggestions,\r\n",
            "descriptions, ideas or other feedback regarding the Licensed Software\r\n",
            "Press [Enter] to continue:provided by You or on Your behalf.\r\n",
            "\r\n",
            "2.11. No Other Licenses or Intellectual Property Rights. Except as\r\n",
            "provided in this Agreement, neither party grants to the other party,\r\n",
            "either directly or indirectly, by implication, or by way of estoppel,\r\n",
            "any license or any other rights under such party's Intellectual\r\n",
            "Property Rights. Other than the rights expressly granted to You under\r\n",
            "the Agreement, Intel expressly reserves all other rights in and to the\r\n",
            "Licensed Software, Documentation, and Intellectual Property Rights\r\n",
            "associated with any of the foregoing. You acknowledge and agree that\r\n",
            "this Agreement does not grant You any right to practice, or any other\r\n",
            "rights with respect to, any patent of Intel or its licensors.\r\n",
            "\r\n",
            "3. Ownership and Future Development.\r\n",
            "\r\n",
            "3.1. Ownership of Licensed Software. All right, title and interest in\r\n",
            "and to the Licensed Software and associated Documentation are and will\r\n",
            "remain the exclusive property of Intel and its licensors or suppliers,\r\n",
            "including but not limited to enhancements, corrections, improvements,\r\n",
            "modified versions, or Derivative Works of all the foregoing, in whole\r\n",
            "or in part, whether developed or co-developed by Intel, or developed\r\n",
            "or co-developed by You pursuant to this Agreement. Notwithstanding\r\n",
            "anything to the contrary above in this Section, You will own all\r\n",
            "Press [Enter] to continue:right, title and interest in any Intel FPGA IP Permitted Derivative\r\n",
            "Works created by You under this Agreement, and You may use and\r\n",
            "distribute any Intel FPGA IP Permitted Derivative Works, but agree to\r\n",
            "solely use and distribute Intel FPGA IP Permitted Derivative Works\r\n",
            "only for use in Devices.  You grant to Intel and its affiliates a non-\r\n",
            "exclusive, perpetual, sublicenseable, irrevocable, worldwide, royalty-\r\n",
            "free, fully paid-up and transferable license, to and under all of Your\r\n",
            "Intellectual Property Rights, whether perfected or not, to publicly\r\n",
            "perform, publicly display, reproduce, use, make, have made, sell,\r\n",
            "offer for sale, sublicense, distribute, import, create Derivative\r\n",
            "Works of and otherwise exploit any of Your Intel FPGA IP Permitted\r\n",
            "Derivative Works.\r\n",
            "\r\n",
            "3.2. You recognize and acknowledge that Intel is or may be\r\n",
            "independently developing for commercial use products that may be\r\n",
            "complementary to or competitive with Your products and may in the\r\n",
            "future independently develop products that may compete with Your\r\n",
            "products. Nothing in this Agreement will limit Intel's independent\r\n",
            "development and marketing or distribution of any products or systems,\r\n",
            "provided such independent development is accomplished without use of\r\n",
            "Your confidential information. The existence of this Agreement will\r\n",
            "not prevent Intel from undertaking discussions with third parties,\r\n",
            "including Your competitors.\r\n",
            "Press [Enter] to continue:\r\n",
            "4. Fees and Taxes\r\n",
            "\r\n",
            "4.1. License Fee. You will pay Intel (or an Authorized Distributor)\r\n",
            "the License Fees in the amounts and at the times set forth in the\r\n",
            "applicable quote or invoice.  Your obligation to remit License Fees in\r\n",
            "accordance with the applicable quote or invoice is absolute,\r\n",
            "unconditional, noncancellable and nonrefundable, and will not be\r\n",
            "subject to any abatement, set-off, claim, counterclaim, adjustment,\r\n",
            "reduction, or defense for any reason including, but not limited to,\r\n",
            "any claim that Intel failed to perform under this Agreement or\r\n",
            "termination of this Agreement. Past due amounts will bear interest at\r\n",
            "the rate of the lesser of 1-1/2% per month on the unpaid balance, or\r\n",
            "the maximum rate allowable by law.  In addition to all other sums\r\n",
            "payable under this Agreement, You will pay all out-of-pocket expenses\r\n",
            "that Intel or an Authorized Distributor incurs, including fees and\r\n",
            "disbursements of counsel, in connection with collection and other\r\n",
            "enforcement proceedings resulting from or in connection with those\r\n",
            "proceedings.\r\n",
            "\r\n",
            "4.2. Taxes.  All payments will be made free and clear without\r\n",
            "deduction for any present and future taxes imposed by any taxing\r\n",
            "authority.  If You are prohibited by law from making such payments\r\n",
            "Press [Enter] to continue:unless You deduct or withhold taxes from the payments and remit the\r\n",
            "taxes to the local taxing jurisdiction, then You must withhold and\r\n",
            "remit those taxes and pay to Intel the remaining net amount after the\r\n",
            "taxes have been withheld.  You will promptly furnish Intel with a copy\r\n",
            "of an official tax receipt or other appropriate evidence of any taxes\r\n",
            "imposed on payments made under this Agreement, including taxes on any\r\n",
            "additional amounts paid.  In cases other than taxes referred to above\r\n",
            "including, but not limited to, sales and use taxes, stamp taxes, value\r\n",
            "added taxes, property taxes and other taxes or duties imposed by any\r\n",
            "taxing authority on or with respect to this Agreement, You will bear\r\n",
            "the costs of those taxes or duties. If those taxes or duties are\r\n",
            "legally imposed initially on Intel or Intel is later assessed by any\r\n",
            "taxing authority, then You will promptly reimburse Intel for those\r\n",
            "taxes or duties plus any interest and penalties that Intel suffers.\r\n",
            "\r\n",
            "5. Confidentiality and Publicity.\r\n",
            "\r\n",
            "5.1. With respect to Confidential Information, You agree to: maintain\r\n",
            "the confidentiality of the Confidential Information with at least the\r\n",
            "same degree of care that You use to protect Your own confidential and\r\n",
            "proprietary information, but no less than a reasonable degree of care\r\n",
            "under the circumstances; not to use or disclose Confidential\r\n",
            "Information for any purpose except to the extent necessary and for the\r\n",
            "Press [Enter] to continue:purpose of exercising Your rights under this Agreement (the \"Intended\r\n",
            "Purpose\"); to restrict the disclosure and possession of Confidential\r\n",
            "Information solely to those Users, employees and Authorized\r\n",
            "Contractors with a need to know/need to access for the Intended\r\n",
            "Purpose, who agree to be bound by written confidentiality agreements\r\n",
            "no less strict than those contained in this Agreement; and be liable\r\n",
            "to Intel for any breaches of the confidentiality obligations by Your\r\n",
            "Users, employees, and Authorized Contractors. You will not be liable\r\n",
            "for the disclosure of any Confidential Information that is: generally\r\n",
            "made available publicly or to third parties by the disclosing party\r\n",
            "without restriction on disclosure; received without any obligation of\r\n",
            "confidentiality from a third party who rightfully had possession of\r\n",
            "the information; rightfully known to You without any limitation on\r\n",
            "disclosure, before Your receipt from the disclosing party; the same as\r\n",
            "information that is independently developed by employees, contingent\r\n",
            "workers, or professional advisers of Yours; or required to be\r\n",
            "disclosed under applicable laws, regulations, or court, judicial, or\r\n",
            "government agency orders. The receiving party must give the disclosing\r\n",
            "party reasonable notice before this disclosure, and seek a protective\r\n",
            "order, confidential treatment, or other remedy, if available, to limit\r\n",
            "the scope of the required disclosure. Information exchanged between\r\n",
            "Intel and You may additionally be subject to the terms and conditions\r\n",
            "of the Corporate Non-Disclosure Agreement(s) or Intel Pre-Release Loan\r\n",
            "Press [Enter] to continue:Agreement(s) (referred to herein collectively or individually as\r\n",
            "\"NDA\") entered into by and in force between Intel and You.  In the\r\n",
            "event of a conflict between this Agreement and the NDA, the NDA will\r\n",
            "control.  You agree that Intel may disclose Your identity by name,\r\n",
            "address and other contact information, and identify the Licensed\r\n",
            "Software licensed to You, to the extent required by Intel's agreements\r\n",
            "with its licensors and Authorized Distributors.\r\n",
            "\r\n",
            "5.2. You agree not to use Intel's name, trademarks or logos in any\r\n",
            "publications, advertisements, or other announcements without Intel's\r\n",
            "prior written consent.\r\n",
            "\r\n",
            "6. Warranty Information\r\n",
            "\r\n",
            "6.1. Limited Warranty.  If the Licensed Software has been delivered on\r\n",
            "physical media, Intel warrants for 90 days after delivery that the\r\n",
            "media on which the Licensed Software is furnished is free of\r\n",
            "manufacturing defects and shipping damage provided the media has been\r\n",
            "properly installed. Intel does not warrant that the Licensed Software\r\n",
            "will meet Your requirements or that the use will be uninterrupted or\r\n",
            "error-free.  Your sole remedy and Intel's entire liability for breach\r\n",
            "of the warranty in this Section, is that You may return the defective\r\n",
            "media to Intel for replacement or alternate delivery, at Intel's\r\n",
            "Press [Enter] to continue:option and expense.  This warranty is void if the media defect has\r\n",
            "resulted from accident, abuse, mishandling, misuse, misinstallation,\r\n",
            "neglect or misapplication.\r\n",
            "\r\n",
            "6.2. Disclaimer of Warranties. Except as provided above, Intel makes\r\n",
            "no warranties to You with respect to the Licensed Software, Third\r\n",
            "Party Materials, Open Source Software or any Support, service, advice,\r\n",
            "or assistance furnished under this Agreement, and no warranties of any\r\n",
            "kind, whether written, oral, implied or statutory, including\r\n",
            "warranties of merchantability or fitness for a particular purpose,\r\n",
            "non-infringement or arising from course of dealing or usage in trade\r\n",
            "will apply.\r\n",
            "\r\n",
            "6.3. Encryption Technology.  The Licensed Software may include\r\n",
            "Encryption Technology. The Encryption Technology is based on both\r\n",
            "recognized industry encryption technology standards and proprietary\r\n",
            "Intel technology. The Encryption Technology is provided solely for\r\n",
            "Your convenience in using the Licensed Software under this Agreement.\r\n",
            "You recognize and agree that no encryption software is error-free,\r\n",
            "foolproof or completely secure (including the Encryption Technology)\r\n",
            "and as such You agree that the Encryption Technology is provided \"as\r\n",
            "is\" with no warranties of any kind, whether written, oral, implied or\r\n",
            "statutory, including warranties of merchantability, fitness for a\r\n",
            "Press [Enter] to continue:particular purpose, non-infringement or arising from course of dealing\r\n",
            "or usage in trade.  You agree that Your use of the Encryption\r\n",
            "Technology is at Your own risk and that Intel will not be liable for\r\n",
            "any claims related to Your use of the Encryption Technology.\r\n",
            "\r\n",
            "6.4. Third Party Actions; Security Threats.  Intel makes no warranty\r\n",
            "with respect to any malfunctions or other errors in its hardware\r\n",
            "products or software products caused by virus, infection, worm or\r\n",
            "similar malicious code not developed or introduced by Intel.  Intel\r\n",
            "makes no warranty that any hardware products or software products will\r\n",
            "protect against all possible security threats, including intentional\r\n",
            "misconduct by third parties.  Intel is not liable for any downtime or\r\n",
            "service interruption, for any lost or stolen data or systems, or for\r\n",
            "any other damages arising out of or relating to any such actions or\r\n",
            "intrusions.\r\n",
            "\r\n",
            "7. Indemnification.\r\n",
            "\r\n",
            "7.1. Intel will defend, at its own expense, any legal action brought\r\n",
            "against You to the extent that it is based on any claim or allegation\r\n",
            "that the Licensed Software, in the form delivered to You, directly\r\n",
            "infringes a U.S. patent or copyright or constitutes a misappropriation\r\n",
            "of trade secrets of any third party (\"Infringement Claim\").\r\n",
            "Press [Enter] to continue:\r\n",
            "7.2. Intel will pay any costs and damages finally awarded against You\r\n",
            "in any Infringement Claim that are attributable to the Infringement\r\n",
            "Claim or that You incur through settlement of the Infringement Claim,\r\n",
            "but will not be responsible for any compromise that You made or\r\n",
            "expense that You incurred without Intel's written consent.\r\n",
            "\r\n",
            "7.3. Notwithstanding anything else in the Agreement, Intel will not\r\n",
            "indemnify or defend You for claims asserted, in whole or part,\r\n",
            "against: (i) technology or designs that You gave to Intel; (ii)\r\n",
            "failure to use compatible devices (including Intel Devices) as set\r\n",
            "forth in the Specifications;  (iii) modifications or programming to\r\n",
            "the Licensed Software that were made by anyone other than Intel; or,\r\n",
            "(iv) the Licensed Software's alleged implementation of some or all of\r\n",
            "a Standard.\r\n",
            "\r\n",
            "7.4. The defense and payment obligations of Intel in this Section 7\r\n",
            "are subject to the condition that You: (i) give Intel prompt written\r\n",
            "notice of the Infringement Claim; (ii) allow Intel to direct the\r\n",
            "defense and settlement of the Infringement Claim; and (iii) cooperate\r\n",
            "with Intel in the defense and settlement of the Infringement Claim.\r\n",
            "\r\n",
            "7.5. This indemnity is personal to You and will under no circumstances\r\n",
            "Press [Enter] to continue:be assignable, transferable or subject to pass-through to Your\r\n",
            "customers or indirect customers.  You will notify customers that they\r\n",
            "must look solely to You in connection with any Infringement Claim.\r\n",
            "\r\n",
            "7.6. If any Licensed Software, or the operation of the Licensed\r\n",
            "Software, becomes or, in Intel's opinion is likely to become, the\r\n",
            "subject of an Infringement Claim, Intel may, at Intel's option and\r\n",
            "expense, procure for You the right to continue using the Licensed\r\n",
            "Software, replace or modify the Licensed Software so that it becomes\r\n",
            "non-infringing, or terminate the license granted under this Agreement\r\n",
            "for that Licensed Software and refund to You the License Fees You paid\r\n",
            "to Intel (less a reasonable charge for the period during which You has\r\n",
            "had availability of that Licensed Software for use, and of Support).\r\n",
            "This Section 7 will survive for three (3) years after expiration or\r\n",
            "termination of this Agreement.\r\n",
            "\r\n",
            "8. Term and Termination.\r\n",
            "\r\n",
            "8.1. Term. This Agreement is effective until terminated by either\r\n",
            "party, or terminated in accordance with its terms, whichever occurs\r\n",
            "first.\r\n",
            "\r\n",
            "8.2. Termination. Intel may terminate this Agreement in accordance\r\n",
            "Press [Enter] to continue:with its terms. You may terminate this Agreement at any time by\r\n",
            "uninstalling and permanently ceasing Use of the Licensed Software.\r\n",
            "Intel may terminate the license immediately if You or an Authorized\r\n",
            "Contractor fail to comply with any material term or condition of this\r\n",
            "Agreement, including but not limited to Your or an Authorized\r\n",
            "Contractor's breach of the license rights granted in this Agreement,\r\n",
            "breach of Your or an Authorized Contractor's obligation of\r\n",
            "confidentiality, or if You: (i) cease to do business or terminate Your\r\n",
            "business operations; or (ii) become insolvent or seek protection under\r\n",
            "any bankruptcy or liquidation or similar proceedings, or make an\r\n",
            "assignment of all or a majority of Your assets for the benefit of\r\n",
            "creditors.\r\n",
            "\r\n",
            "8.3. Effect of Termination. Upon termination of this Agreement for any\r\n",
            "reason, the licenses and any rights granted under this Agreement will\r\n",
            "terminate, and You agree to irrevocably destroy, and will cause any of\r\n",
            "Your employees and Authorized Contractors to irrevocably destroy, the\r\n",
            "Licensed Software, Third Party Software and Unlicensed Software, and\r\n",
            "all portions of the foregoing, in Your possession or under Your\r\n",
            "control (including any portions merged into a design or Licensed\r\n",
            "Product not already distributed). Upon request, You agree to certify\r\n",
            "such destruction in writing to Intel. You may keep a single copy of\r\n",
            "the Licensed Software solely for archival purposes, but You will not\r\n",
            "Press [Enter] to continue:continue to Use the Licensed Software or any portion thereof in\r\n",
            "development after termination of the Agreement. No refund for the\r\n",
            "Licensed Software will be provided to You upon termination of this\r\n",
            "Agreement.\r\n",
            "\r\n",
            "9. Support and Maintenance Services.\r\n",
            "\r\n",
            "9.1. Upon payment of the applicable Support fee, Intel or its\r\n",
            "Authorized Distributor, will for the Support period communicated to\r\n",
            "You at the time of Your license purchase or renewal, (i) provide\r\n",
            "Support and maintenance for the Licensed Software (including bug\r\n",
            "fixes, error corrections and any other updates) made generally\r\n",
            "available by Intel to licensees that purchase support and maintenance;\r\n",
            "(ii) use commercially reasonable efforts to provide fixes to defects\r\n",
            "in the Licensed Software that cause the Licensed Software not to\r\n",
            "conform in material respects with the specifications that are\r\n",
            "diagnosed as non-conformances, and are capable of replication by\r\n",
            "Intel; and (iii) use commercially reasonable efforts to respond by\r\n",
            "telephone or email to Your inquiries for Support for the Licensed\r\n",
            "Software. You agree that any information collected by Intel or the\r\n",
            "Authorized Distributor arising from or relating to Your requests for\r\n",
            "Support, including but not limited to design files compiled using the\r\n",
            "Licensed Software provided by You for purposes of design assistance,\r\n",
            "Press [Enter] to continue:enhancement, and troubleshooting, may be used internally by Intel for\r\n",
            "the purpose of improving future versions of the Licensed Software and\r\n",
            "developing future products.\r\n",
            "\r\n",
            "9.2. Exclusions. Except as otherwise described in Section 9.1, Intel\r\n",
            "will not have any obligation to provide any maintenance, support, or\r\n",
            "training, or to provide any error corrections, updates, upgrades, new\r\n",
            "versions, other modifications, or enhancements to the Licensed\r\n",
            "Software, Devices, or any Licensed Products. You will be responsible,\r\n",
            "at Your own expense, for providing technical support and training to\r\n",
            "Your customers and any other end users of the Licensed Software or\r\n",
            "Licensed Products, and Intel will have no obligation to support any of\r\n",
            "the foregoing. You will be solely responsible for, and Intel will have\r\n",
            "no obligation to honor, any warranties that You may provide to Your\r\n",
            "customers or to any other end users of the Licensed Products.\r\n",
            "\r\n",
            "10. Limitation of Liability.\r\n",
            "\r\n",
            "10.1. Intel's cumulative liability to You for all claims of any kind\r\n",
            "resulting from Intel's performance or breach of this Agreement or the\r\n",
            "Licensed Software or Support furnished under this Agreement, including\r\n",
            "any indemnity by Intel under this Agreement, will not exceed (i) the\r\n",
            "License Fees actually received by Intel from You under this Agreement\r\n",
            "Press [Enter] to continue:for the Licensed Software and Support that is the subject of the\r\n",
            "claim, or (ii) $1,000, if the Licensed Software was provided at no\r\n",
            "charge to You, regardless of whether Intel has been advised of the\r\n",
            "possibility of those damages or whether any remedy set forth in this\r\n",
            "Agreement fails of its essential purpose or otherwise.  This\r\n",
            "limitation of liability is cumulative and not per incident; the\r\n",
            "existence of more than one claim will not increase the limit.\r\n",
            "\r\n",
            "10.2. Intel will not be liable for costs of procurement of\r\n",
            "substitutes, loss of profits, loss of use, interruption of business,\r\n",
            "or for any other special, consequential, punitive or incidental\r\n",
            "damages, however caused, whether for breach of warranty, contract,\r\n",
            "tort, negligence, strict liability or otherwise, irrespective of\r\n",
            "whether Intel has advance notice of the possibility of such damages.\r\n",
            "The limitation of liability set forth in Section 10 is a fundamental\r\n",
            "basis of this Agreement; and You understand and agree that Intel would\r\n",
            "not have entered into this Agreement without the limitation of\r\n",
            "liability.\r\n",
            "\r\n",
            "10.3. THE LICENSED SOFTWARE MAY BE USED TO CREATE END PRODUCTS USED IN\r\n",
            "SAFETY-CRITICAL APPLICATIONS DESIGNED TO COMPLY WITH FUNCTIONAL SAFETY\r\n",
            "STANDARDS OR REQUIREMENTS (\"SAFETY-CRITICAL APPLICATIONS\").  IT IS\r\n",
            "YOUR RESPONSIBILITY TO DESIGN, MANAGE AND ASSURE SYSTEM-LEVEL\r\n",
            "Press [Enter] to continue:SAFEGUARDS TO ANTICIPATE, MONITOR AND CONTROL SYSTEM FAILURES, AND YOU\r\n",
            "AGREE THAT YOU ARE SOLELY RESPONSIBLE FOR ALL APPLICABLE REGULATORY\r\n",
            "STANDARDS AND SAFETY-RELATED REQUIREMENTS CONCERNING YOUR USE OF THE\r\n",
            "LICENSED SOFTWARE IN SAFETY CRITICAL APPLICATIONS.  YOU AGREE TO\r\n",
            "INDEMNIFY AND HOLD INTEL AND ITS REPRESENTATIVES HARMLESS AGAINST ANY\r\n",
            "DAMAGES, COSTS, AND EXPENSES ARISING IN ANY WAY OUT OF YOUR USE OF THE\r\n",
            "LICENSED SOFTWARE IN SAFETY-CRITICAL APPLICATIONS.\r\n",
            "\r\n",
            "11. Choice of Law/Venue. This Agreement will in all respects be\r\n",
            "governed by, and construed and interpreted under, the laws of the\r\n",
            "United States of America and the State of Delaware, without reference\r\n",
            "to conflict of laws principles.   The parties agree that the United\r\n",
            "Nations Convention on Contracts for the International Sale of Goods\r\n",
            "(1980) is specifically excluded from and will not apply to this\r\n",
            "Agreement. All disputes arising out of or related to this Agreement\r\n",
            "will be subject to the exclusive jurisdiction of the courts of the\r\n",
            "State of Delaware or of the Federal courts sitting in that State. Each\r\n",
            "party submits to the personal jurisdiction of those courts and waives\r\n",
            "all objections to that jurisdiction and venue for those disputes.\r\n",
            "\r\n",
            "12. Export Control. You will not export, directly or indirectly, any\r\n",
            "Confidential Information, the Licensed Software, the Documentation or\r\n",
            "any product, service or technical data or system incorporating the\r\n",
            "Press [Enter] to continue:Licensed Software without first obtaining any required license or\r\n",
            "other approval from the U.S. Department of Commerce or any other\r\n",
            "agency or department of the U.S. government. In the event of export\r\n",
            "from the United States or re-export from a foreign destination, You\r\n",
            "will ensure that the distribution and export or import of the product\r\n",
            "is in compliance with all laws, regulations, orders, or other\r\n",
            "restrictions of the U.S. Export Administration Regulations and the\r\n",
            "appropriate foreign government.\r\n",
            "\r\n",
            "13. U.S. Government Restricted Rights. You acknowledge and agree that\r\n",
            "all software and software-related items licensed to You by Intel\r\n",
            "pursuant to this Agreement are \"Commercial Computer Software\" or\r\n",
            "\"Commercial Computer Software Documentation\" as defined in FAR 12.212\r\n",
            "for civilian agencies and DFARS 227-7202 for military agencies (as\r\n",
            "amended) and in the event You are permitted under this Agreement to\r\n",
            "provide such items to the U.S. government, such items will be provided\r\n",
            "under terms that are at least as restrictive as the provisions of this\r\n",
            "Agreement. The contractor/manufacturer is Intel Corporation, 2200\r\n",
            "Mission College Blvd., Santa Clara, CA 95054 and its licensors.\r\n",
            "\r\n",
            "14. No Assignment. You may not delegate, assign or transfer this\r\n",
            "Agreement, the license(s) granted or any of Your rights or duties\r\n",
            "hereunder, expressly, by implication, by operation of law, or\r\n",
            "Press [Enter] to continue:otherwise and any attempt to do so, without Intel's express prior\r\n",
            "written consent, will be null and void. Intel may assign, delegate and\r\n",
            "transfer this Agreement, and its rights and obligations hereunder, in\r\n",
            "its sole discretion.\r\n",
            "\r\n",
            "15. Problem Reporter Notice, Consent and Opt-Out. The Problem Reporter\r\n",
            "feature of the Licensed Software will collect and provide certain\r\n",
            "information to Intel concerning Your use of the Licensed Software, in\r\n",
            "the event of a software crash. No logic designs or machine-executable\r\n",
            "binary form of cores used to program a Device that are processed with\r\n",
            "the Licensed Software will be collected or transmitted with the\r\n",
            "Problem Reporter. The types of data Problem Reporter transmits to\r\n",
            "Intel include: (i) Licensed Software tools (tools used, and version\r\n",
            "and build of the Licensed Software); (ii) platform data (operating\r\n",
            "system); and (iii) Licensed Software errors log data (previous exit\r\n",
            "status). You agree that You have been fully informed about the\r\n",
            "purposes for which Your information will be used, and You give Your\r\n",
            "consent for Intel to use this information both within and outside of\r\n",
            "the European Union for the purposes described in this Problem Reporter\r\n",
            "disclosure notice. You may disable or enable Problem Reporter at any\r\n",
            "time by making the appropriate setting in the Licensed Software.\r\n",
            "\r\n",
            "16. Audit Rights. You agree to keep complete and accurate books and\r\n",
            "Press [Enter] to continue:records which confirm Your compliance with the terms and conditions of\r\n",
            "this Agreement. Intel will have a right to audit Your facilities and\r\n",
            "records, provided that such audit: (i) will be conducted at reasonable\r\n",
            "times, upon reasonable prior written notice; and (ii) will not\r\n",
            "unreasonably interfere with Your normal business operations. This\r\n",
            "Section will survive for three (3) years after expiration or\r\n",
            "termination of this Agreement.\r\n",
            "\r\n",
            "17. General Terms. This Agreement is entered into for the benefit of\r\n",
            "Intel, its licensors and Authorized Distributors, and all rights\r\n",
            "granted to You and all obligations owed to Intel, its licensors and\r\n",
            "the Authorized Distributors will be enforceable by Intel, its\r\n",
            "licensors and the Authorized Distributors. No modification of this\r\n",
            "Agreement will be binding unless in writing and signed by authorized\r\n",
            "representatives of each party. If any of the provisions of this\r\n",
            "Agreement are found to be in violation of applicable law, void, or\r\n",
            "unenforceable, then such provisions will be deemed to be deleted from\r\n",
            "the Agreement, but the remaining provisions of the Agreement will\r\n",
            "remain in full force and effect. You agree that the Agreement is the\r\n",
            "complete and entire agreement between You and Intel with respect to\r\n",
            "the subject matter hereof. No statements, promises or representations\r\n",
            "have been made by one party to the other, or are relied upon by either\r\n",
            "party when entering into this Agreement. All prior and contemporaneous\r\n",
            "Press [Enter] to continue:discussions and negotiations, whether verbal or written, are merged\r\n",
            "into and superseded by the Agreement. Except as stated herein, no\r\n",
            "entity or person not a party hereto will have any interest under this\r\n",
            "Agreement, or be deemed to be a third party beneficiary of the\r\n",
            "Agreement. If the Agreement expires or terminates for any reason, all\r\n",
            "definitions in this Agreement and the rights, obligations, and\r\n",
            "restrictions under Sections 1 (Definitions); 2.2 (Use Restrictions);\r\n",
            "2.6 (Authorized Contractors); 2.7.2 (Third Party Materials\r\n",
            "Disclaimer); 2.8 (Open Source Statement); 2.9 (Intellectual Property\r\n",
            "Rights Notices); 2.10 (Feedback); 2.11 (No Other Licenses or\r\n",
            "Intellectual Property Rights); 3 (Ownership and Future Development); 5\r\n",
            "(Confidentiality and Publicity); 6 (Warranty Information); 7\r\n",
            "(Indemnification); 8.3 (Effect of Termination); 10 (Limitation of\r\n",
            "Liability); 11 (Choice of Law/Venue); 12 (Export Control); 13 (U.S.\r\n",
            "Government Restricted Rights); 14 (No Assignment); 15 (Problem\r\n",
            "Reporter Notice, Consent and Opt-Out); 16 (Audit Rights); and 17\r\n",
            "(General Terms) will survive expiration or termination of this\r\n",
            "Agreement.\r\n",
            "\r\n",
            "END OF QUARTUS PRIME AND INTEL FPGA IP LICENSE AGREEMENT, VERSION 22.1std\r\n",
            "\r\n",
            "\r\n",
            "===================================================================\r\n",
            "Press [Enter] to continue:\r\n",
            "THIRD-PARTY LICENSES\r\n",
            "\r\n",
            "NOTE: The following third-party licenses and notices represent each\r\n",
            "third-party contributor's use requirements for Your usage of any third-\r\n",
            "party software incorporated into or provided in conjunction with the\r\n",
            "Intel FPGA product(s) licensed under the Intel FPGA Software License Agreement\r\n",
            "(\"Agreement\").  The provisions contained in each such license apply\r\n",
            "only to the respective Third-Party Components (as such term is defined\r\n",
            "in the Agreement) and not to any Intel FPGA products licensed to You.\r\n",
            "\r\n",
            "Quartus Prime THIRD-PARTY LICENSES\r\n",
            "------------------------------------------------------------------\r\n",
            "1. 7-zip 18.05 (LGPL v. 2.1, BSD 3-clause, unRAR License)\r\n",
            "2. Alphanum 1.0 (libpng/zlib License)\r\n",
            "3. Apache Xerces C++ 3.2.2 (Apache v. 2.0 license)\r\n",
            "4. backports.functools_lru_cache 1.5 (MIT)\r\n",
            "5. Base64 decoder 1.0 (Zlib License)\r\n",
            "6. boost 1.53.0 (MIT-style License)\r\n",
            "7. Bottle 0.12.21 (MIT License)\r\n",
            "8. buddy 2.2 (BSD-style License)\r\n",
            "9. bwidget 1.4.1 (BSD-style License)\r\n",
            "10. Cajun 2.0.1 (3 Clause BSD License)\r\n",
            "Press [Enter] to continue:11. certifi 2021.10.8 (Mozilla Public License 2.0 (MPL 2.0))\r\n",
            "12. chardet 3.0.4 (GNU Lesser General Public License v2.1)\r\n",
            "13. cheroot 6.5.4 (BSD 3 Clause License)\r\n",
            "14. CherryPy 18.1.0 (3 Clause BSD License)\r\n",
            "15. defusedxml 0.6.0 (Python Software Foundation License Version 2)\r\n",
            "16. Editline Library (libedit) 0:42:0 (NetBSD License)\r\n",
            "17. GD 2.0.34 (BSD-style License)\r\n",
            "18. IBM.ICU 4.4.2 (IBM ICU License and additional Third Party terms)\r\n",
            "19. ICU 69.1 (IBM License and additional third party terms)\r\n",
            "20. idna 2.8 (BSD)\r\n",
            "21. INCR TCL 4.0 (BSD-Style License)\r\n",
            "22. jaraco.functools 2.0 (MIT)\r\n",
            "23. jdbc sqlite 20120209 (Apache v. 2.0 license)\r\n",
            "24. jpeg 6b (Indedendent JPEG Group License)\r\n",
            "25. jQuery 1.11.3 (MIT License)\r\n",
            "26. jQuery UI 1.10.2 (MIT License)\r\n",
            "27. jQuery UI Layout Plug-in 1.3.0.rc30.79 (MIT License, GPL v.3 License)\r\n",
            "28. jre 8 (GPL v.2.0 License)\r\n",
            "29. libaji_client 22.2 (MIT)\r\n",
            "30. LIBCURL 7.84.0 (MIT/X Derivative License)\r\n",
            "31. Libelf 0.8.10 (LGPL v. 2.1 License)\r\n",
            "32. Liberty Parser 2.6 (SYNOPSYS Open Source License Version 1.0)\r\n",
            "33. libffi 3.3 (Free Software)\r\n",
            "Press [Enter] to continue:34. libunwind 1.4.0 (MIT)\r\n",
            "35. Mac4Lin 1.0 (LGPL v. 2.1 License)\r\n",
            "36. make 3.81 (GPL v. 2.0 License)\r\n",
            "37. metis 4.0.1 (GPL v. 2.0 License)\r\n",
            "38. more-itertools 5.0.0 (MIT License)\r\n",
            "39. more-itertools 6.0.0 (MIT License)\r\n",
            "40. MSDN Sample Code  (Microsoft Developer Agreement)\r\n",
            "41. Normalize.css 2.1.3 (MIT License)\r\n",
            "42. OpenOCD 0.11.0 (General Public License Version 2.0 or later)\r\n",
            "43. OpenSSL 1.1.1n (OpenSSL License and the original SSLeay (The OpenSSL License \r\n",
            "is Apache License 1.0 and SSLeay License bears some similarity to a 4-clause BSD \r\n",
            "License))\r\n",
            "44. Peewee 3.14.0 (MIT License)\r\n",
            "45. Peewee 3.8.2 (MIT License)\r\n",
            "46. Perl 5.30.3 (GPL v. 1.0 or the Artistic License)\r\n",
            "47. PicNet Table Filter  (MIT License)\r\n",
            "48. Protobuf 3.4.0 (BSD 3 Clause License)\r\n",
            "49. psutil 5.6.7 (BSD 3-Clause License)\r\n",
            "50. Python 3.7.13 (PSF License for Python 3.7.13)\r\n",
            "51. [foss] pytz (2018.9)\r\n",
            "52. Requests 2.25.1 (Apache v. 2.0 license)\r\n",
            "53. safestringlib 20170614 (MIT License)\r\n",
            "54. six 1.15.0 (MIT)\r\n",
            "Press [Enter] to continue:55. sqlite 3.39.2 (Public Domain)\r\n",
            "56. superlu 2.2.0 (BSD 3 Clause License)\r\n",
            "57. Tablelist 5.5 (MIT style license)\r\n",
            "58. TableSorter 2.7.3 (MIT License, GPL v. 3.0 Licenses)\r\n",
            "59. tbb 4.2.2 (GPL v.2.0 License)\r\n",
            "60. TCL-TK 8.6 (BSD-style License)\r\n",
            "61. tcldom 3.0 (BSD Style License)\r\n",
            "62. tcllib 1.11 (BSD 4 Clause License)\r\n",
            "63. tclsoap 1.6.7 (MIT License)\r\n",
            "64. tclxml 3.2 (BSD style License)\r\n",
            "65. tempora 1.14 (MIT)\r\n",
            "66. TinyXML2 7.0.1 (zlib)\r\n",
            "67. tktable 2.10 (Tcl/Tk license)\r\n",
            "68. Twitter Bootstrap 3.0.3 (Apache v. 2.0 License)\r\n",
            "69. Twitter Bootstrap 3.3.6 (MIT License)\r\n",
            "70. Underscore.js 1.4.4 (MIT License)\r\n",
            "71. unzip 6.10c23 (Info-ZIP license)\r\n",
            "72. urllib3 1.26.6 (MIT)\r\n",
            "73. xcb-util-image 0.4.0 (MIT)\r\n",
            "74. xcb-util-keysyms 0.4.0 (MIT)\r\n",
            "75. xcb-util-renderutil 0.3.9 (MIT)\r\n",
            "76. xcb-util-wm 0.4.1 (MIT)\r\n",
            "77. xcb-util 0.4.0 (MIT)\r\n",
            "Press [Enter] to continue:78. xmlgen 1.4 (Apache v. 2.0 license)\r\n",
            "79. zc.lockfile 1.4 (Zope Public License (ZPL 2.1))\r\n",
            "80. ZLIB 1.2.12 (Zlib License)\r\n",
            "\r\n",
            "Intel FPGA IP THIRD-PARTY LICENSES\r\n",
            "------------------------------------------------------------------\r\n",
            "1. Micrium uC/OS II 2.93.0 (Apache 2.0)\r\n",
            "2. antlr 2.7.2 (BSD 4 Clause License)\r\n",
            "3. antlr 4.5.1 (BSD 3 Clause License)\r\n",
            "4. appframework 1.03 (LGPL v. 2.1 License)\r\n",
            "5. asm 3.1 (BSD 3 Clause License)\r\n",
            "6. beansbinding 1.2.1 (LGPL v. 2.1 License)\r\n",
            "7. JGoodies Binding 2.0.6 (BSD 3 Clause License)\r\n",
            "8. binutils 2.37.50 (GNU General Public License v3.0 or later)\r\n",
            "9. boost 1.38.0 (MIT-style License)\r\n",
            "10. boost 1.65.0 (MIT-style License)\r\n",
            "11. castor 1.0.3 (Apache v. 2.0 and Intalio BSD-style Licenses)\r\n",
            "12. castor 1.2 (Apache v. 2.0 and Intalio BSD-style Licenses)\r\n",
            "13. checker-framework 2.3.0 (GPL v. 2 License)\r\n",
            "14. checkstyle 4.2 (LGPL v. 2.1 License)\r\n",
            "15. cli 1.1 (Apache v. 2.0 License)\r\n",
            "16. cloog 0.18.1 (LGPL v2 License)\r\n",
            "17. cobertura 1.8 (GPL v. 2 License)\r\n",
            "Press [Enter] to continue:18. codesourcery 2019.05-04 (CodeSourcery Inc License)\r\n",
            "19. Apache Common Collections 4.1 (Apache License 2.0)\r\n",
            "20. Apache Common Collections 4.3 (Apache License 2.0)\r\n",
            "21. Apache Common Lang 3.7 (Apache License 2.0)\r\n",
            "22. commons-beanutils 1.6 (Apache v. 1.1 License)\r\n",
            "23. commons-digester 1.5 (Apache v. 1.1 License)\r\n",
            "24. commons-logging 1.1 (Apache v. 2.0 License)\r\n",
            "25. commons-logging 1.2 (Apache v. 2.0 License)\r\n",
            "26. commons-math 3.5 (Apache v. 2.0 License)\r\n",
            "27. commons-pool 1.2 (Apache v. 2.0 License)\r\n",
            "28. cpputest 3.8 (BSD 3-clause \"New\" or \"Revised\" License)\r\n",
            "29. DockingFrames 1.1.2_20b (LGPL v. 2.1 License)\r\n",
            "30. DockingFrames 1.1.2p12c (LGPL v. 2.1 License)\r\n",
            "31. eclipse-cpp-mars-2 4.5.0 (Eclipse Public License v 1.0)\r\n",
            "32. expat 2.4.8 (MIT License)\r\n",
            "33. explicitlayout 3.0 (LGPL v. 2.1 License)\r\n",
            "34. fmt 4.0.0 (BSD 2-clause \"Simplified\" License)\r\n",
            "35. forms_rt 6.0 (Apache v. 2.0 License)\r\n",
            "36. gcc 12.1.1 (GPL v. 3 License)\r\n",
            "37. gdb 11.2.90 (GPL v. 3 License)\r\n",
            "38. gmp 6.2.1 (LGPL v. 3 License)\r\n",
            "39. gnu 1.2.5 (GPL v. 2 License)\r\n",
            "40. guava-libraries 27.1 (Apache v. 2.0 License)\r\n",
            "Press [Enter] to continue:41. hamcrest 1.3 (BSD 3 Clause License)\r\n",
            "42. isl 0.25 (MIT License)\r\n",
            "43. jacl 1.3.2a (Jacl Software License)\r\n",
            "44. javasysmon 0.3.5 (BSD 2 Clause License)\r\n",
            "45. jaxb-ri 2.3.0 (GPL v. 2.0, and CDDL v. 1.1 Licenses plus Classpath \r\n",
            "Exception)\r\n",
            "46. jaxb-ri 2.2.7 (CDDL v. 1.1; GPL v. 2 Classpath Exception)\r\n",
            "47. jaxb-xew-plugin 1.4 (LGPL v. 3 License)\r\n",
            "48. jaxb2-basics-annotate 1.0.1 (BSD 2 Clause License)\r\n",
            "49. jaxb2-basics-tools 0.9.0 (BSD 3 Clause License)\r\n",
            "50. jaxen 1.1.1 (BSD 3 Clause License)\r\n",
            "51. jaxen 1.3 (BSD 4 Clause License)\r\n",
            "52. jcommon 1.0.16 (LGPL v. 3 License)\r\n",
            "53. JDOM 1.0 (BSD-style License)\r\n",
            "54. JFreeChart 1.0.13 (LGPL v. 3 License)\r\n",
            "55. JGraphX 2.2.0.2 (BSD 3 Clause License)\r\n",
            "56. jline 2.12 (BSD 3 Clause License)\r\n",
            "57. Jline3 3.7.0 (BSD 3-clause \"New\" or \"Revised\" License)\r\n",
            "58. jsap 2.0a (LGPL v. 2.1 License)\r\n",
            "59. jsr173 1.0 (Apache v. 2.0 License)\r\n",
            "60. junit 3.8.1 (Common Public License v. 1.0)\r\n",
            "61. junit 4.0 (Common Public License v. 1.0)\r\n",
            "62. junit 4.1 (Common Public License v. 1.0)\r\n",
            "Press [Enter] to continue:63. l2fprod 7.3 (Apache v. 2.0 License)\r\n",
            "64. libstdc v3 (GPL v. 3 License)\r\n",
            "65. looks 2.0.1 (BSD 2 Clause License)\r\n",
            "66. make 3.81 (GPL v. 2 License)\r\n",
            "67. miglayout15 3.0.3 (BSD 2 Clause License)\r\n",
            "68. miglayout 4.0 (BSD)\r\n",
            "69. mpc 1.2.1 (LGPL v. 3 License)\r\n",
            "70. mpfr 4.0.2 (LGPL v. 3 License)\r\n",
            "71. mpir 2.2.1 (LGPL v. 3 License)\r\n",
            "72. mpir 3.0.0 (LGPL v. 3 License)\r\n",
            "73. mydoggy 1.4.2 (LGPL v. 3 License)\r\n",
            "74. ncurses 6.3\r\n",
            "75. netbeans-swing-outline 6.9 (LGPL v. 2.1, GPL v. 2.0, and CDDL v. 1 Licenses \r\n",
            "plus Classpath Exception)\r\n",
            "76. newlib 4.2.0 (Red Hat and BSD 3 Clause Licenses)\r\n",
            "77. quickserver 1.4.7 (LGPL v.2.1 License)\r\n",
            "78. swingworker 3 (MPL v. 1.1 and LGPL v. 2.1 Licenses)\r\n",
            "79. symphony 5.4.5 (Eclipse Public License v. 1.0)\r\n",
            "80. systemc 2.2.0 (SystemC Open Source License v. 3.3)\r\n",
            "81. velocity 1.4 (Apache v. 2.0 License)\r\n",
            "82. wraplf 0.2 (Apache v. 2.0 License)\r\n",
            "83. xalan 1.2.2 (Apache v. 2.0 License)\r\n",
            "84. xerces-c 3.2.2 (Apache v. 2.0 License)\r\n",
            "Press [Enter] to continue:85. xerces 2.12.0 (Apache v. 1.1 License)\r\n",
            "86. xmlbeans 2.2.0 (Apache v. 2.0 License)\r\n",
            "\r\n",
            "Press [Enter] to continue:\r\n",
            "Do you accept this license? [y/n]: \r\n",
            "Do you accept this license? [y/n]: \n",
            "----------------------------------------------------------------------------\n",
            "Specify the directory where Quartus Prime Lite Edition (Free) 22.1std.0.915 will \n",
            "be installed\n",
            "\n",
            "Installation directory [/root/intelFPGA_lite/22.1std]: \n",
            "----------------------------------------------------------------------------\n",
            "Select the components you want to install\n",
            "\n",
            "Quartus Prime Lite Edition (Free)  [Y/n] :\n",
            "Quartus Prime Lite Edition (Free)  - Quartus Prime (includes Nios II EDS) (8475MB) : Y (Cannot be edited)\n",
            "\n",
            "Quartus Prime Lite Edition (Free)  - Quartus Prime Help (499.1MB) [Y/n] :\n",
            "Quartus Prime Lite Edition (Free)  - Devices [Y/n] :\n",
            "Quartus Prime Lite Edition (Free)  - Devices - Arria II (536.5MB) [Y/n] :\n",
            "Quartus Prime Lite Edition (Free)  - Devices - Cyclone IV (516.1MB) [Y/n] :\n",
            "Quartus Prime Lite Edition (Free)  - Devices - Cyclone 10 LP (293.3MB) [Y/n] :\n",
            "Quartus Prime Lite Edition (Free)  - Devices - Cyclone V (1432.3MB) [Y/n] :\n",
            "Quartus Prime Lite Edition (Free)  - Devices - MAX II/V (13.1MB) [Y/n] :\n",
            "Quartus Prime Lite Edition (Free)  - Devices - MAX 10 FPGA (356.9MB) [Y/n] :\n",
            "Questa - Intel FPGA Starter Edition (A zero cost license required) (4180.8MB) [Y/n] :\n",
            "Questa - Intel FPGA Edition (4180.8MB) [y/N] : \n",
            "Is the selection above correct? [Y/n]: \n",
            "----------------------------------------------------------------------------\n",
            "Ready to Install\n",
            "\n",
            "\n",
            "\t\t\t\t\n",
            "Summary:\n",
            "  Installation directory: /root/intelFPGA_lite/22.1std\n",
            "  Required disk space:  14090 MB\n",
            "  Available disk space: 73312 MB\n",
            "\n",
            "\n",
            "\n",
            "  \n",
            "  \n",
            "  \n",
            "\n",
            "\t\t\t  \n",
            "\t\t\t  \n",
            "\n",
            "\n",
            "\n",
            "----------------------------------------------------------------------------\n",
            "Wait while Setup installs Quartus Prime Lite Edition (Free) 22.1std.0.915\n",
            "\n",
            " Installing\n",
            " 0% ______________ 50% ______________ 100%\n",
            " #########################################\n",
            "\n",
            "----------------------------------------------------------------------------\n",
            "Setup has finished installing Quartus Prime Lite Edition (Free) 22.1std.0.915.\n",
            "\n",
            "Create shortcuts on Desktop [Y/n]: \n",
            "Launch Quartus Prime Lite Edition [Y/n]: \n",
            "Provide your feedback at https://fpga-swdepot.intel.com/feedback/22.1std/installer [y/N]: \n"
          ]
        }
      ]
    },
    {
      "cell_type": "code",
      "source": [
        "! echo $PATH\n",
        "\n",
        "import os\n",
        "os.environ['PATH'] += \":/root/intelFPGA_lite/22.1std/quartus/bin\"\n",
        "\n",
        "! echo $PATH"
      ],
      "metadata": {
        "colab": {
          "base_uri": "https://localhost:8080/"
        },
        "id": "K08S4NEXe0t8",
        "outputId": "e2949f1f-9009-43d9-e2c5-c0e1c18a56b7"
      },
      "execution_count": 6,
      "outputs": [
        {
          "output_type": "stream",
          "name": "stdout",
          "text": [
            "/opt/bin:/usr/local/nvidia/bin:/usr/local/cuda/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/tools/node/bin:/tools/google-cloud-sdk/bin\n",
            "/opt/bin:/usr/local/nvidia/bin:/usr/local/cuda/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/tools/node/bin:/tools/google-cloud-sdk/bin:/root/intelFPGA_lite/22.1std/quartus/bin\n"
          ]
        }
      ]
    },
    {
      "cell_type": "code",
      "source": [
        "%cd /content/"
      ],
      "metadata": {
        "colab": {
          "base_uri": "https://localhost:8080/"
        },
        "id": "oxXDt7e_ZnUo",
        "outputId": "a79ef02e-1ceb-4179-947b-addf4ed4afaa"
      },
      "execution_count": 7,
      "outputs": [
        {
          "output_type": "stream",
          "name": "stdout",
          "text": [
            "/content\n"
          ]
        }
      ]
    },
    {
      "cell_type": "code",
      "source": [
        "! git clone https://github.com/agg23/openfpga-pong.git"
      ],
      "metadata": {
        "colab": {
          "base_uri": "https://localhost:8080/"
        },
        "id": "KYN8tLNNerEw",
        "outputId": "ea03df9f-ff3c-44cf-8f0d-c628dff7fb3d"
      },
      "execution_count": 8,
      "outputs": [
        {
          "output_type": "stream",
          "name": "stdout",
          "text": [
            "Cloning into 'openfpga-pong'...\n",
            "remote: Enumerating objects: 747, done.\u001b[K\n",
            "remote: Counting objects: 100% (747/747), done.\u001b[K\n",
            "remote: Compressing objects: 100% (268/268), done.\u001b[K\n",
            "remote: Total 747 (delta 441), reused 709 (delta 411), pack-reused 0\u001b[K\n",
            "Receiving objects: 100% (747/747), 14.38 MiB | 32.65 MiB/s, done.\n",
            "Resolving deltas: 100% (441/441), done.\n"
          ]
        }
      ]
    },
    {
      "cell_type": "code",
      "source": [
        "%cd /content/openfpga-pong/src/fpga/"
      ],
      "metadata": {
        "colab": {
          "base_uri": "https://localhost:8080/"
        },
        "id": "r-QMZ3oGevRB",
        "outputId": "da6ae057-1132-489b-a6ea-53197e5833ba"
      },
      "execution_count": 9,
      "outputs": [
        {
          "output_type": "stream",
          "name": "stdout",
          "text": [
            "/content/openfpga-pong/src/fpga\n"
          ]
        }
      ]
    },
    {
      "cell_type": "code",
      "source": [
        "! quartus_map --read_settings_files=on  --write_settings_files=off ap_core -c ap_core"
      ],
      "metadata": {
        "colab": {
          "base_uri": "https://localhost:8080/"
        },
        "id": "qB_tj9KxewvC",
        "outputId": "86da3684-7ddb-41c2-8053-74de805081b6"
      },
      "execution_count": 10,
      "outputs": [
        {
          "output_type": "stream",
          "name": "stdout",
          "text": [
            "quartus_map: /root/intelFPGA_lite/22.1std/quartus/linux64/liblzma.so.5: no version information available (required by /usr/lib/x86_64-linux-gnu/libunwind.so.8)\n",
            "\u001b[0;32mInfo: *******************************************************************\n",
            "\u001b[0m\u001b[0;32mInfo: Running Quartus Prime Analysis & Synthesis\n",
            "\u001b[0m\u001b[0;32m    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition\n",
            "\u001b[0m\u001b[0;32m    Info: Copyright (C) 2022  Intel Corporation. All rights reserved.\n",
            "\u001b[0m\u001b[0;32m    Info: Your use of Intel Corporation's design tools, logic functions \n",
            "\u001b[0m\u001b[0;32m    Info: and other software and tools, and any partner logic \n",
            "\u001b[0m\u001b[0;32m    Info: functions, and any output files from any of the foregoing \n",
            "\u001b[0m\u001b[0;32m    Info: (including device programming or simulation files), and any \n",
            "\u001b[0m\u001b[0;32m    Info: associated documentation or information are expressly subject \n",
            "\u001b[0m\u001b[0;32m    Info: to the terms and conditions of the Intel Program License \n",
            "\u001b[0m\u001b[0;32m    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,\n",
            "\u001b[0m\u001b[0;32m    Info: the Intel FPGA IP License Agreement, or other applicable license\n",
            "\u001b[0m\u001b[0;32m    Info: agreement, including, without limitation, that your use is for\n",
            "\u001b[0m\u001b[0;32m    Info: the sole purpose of programming logic devices manufactured by\n",
            "\u001b[0m\u001b[0;32m    Info: Intel and sold by Intel or its authorized distributors.  Please\n",
            "\u001b[0m\u001b[0;32m    Info: refer to the applicable agreement for further details, at\n",
            "\u001b[0m\u001b[0;32m    Info: https://fpgasoftware.intel.com/eula.\n",
            "\u001b[0m\u001b[0;32m    Info: Processing started: Tue Jan 10 03:52:46 2023\n",
            "\u001b[0m\u001b[0;32mInfo: Command: quartus_map --read_settings_files=on --write_settings_files=off ap_core -c ap_core\n",
            "\u001b[0m\u001b[0;32mInfo (125069): Default assignment values were changed in the current version of the Quartus Prime software -- changes to default assignments values are contained in file /root/intelFPGA_lite/22.1std/quartus/linux64/assignment_defaults.qdf\n",
            "\u001b[0m\u001b[0;32mInfo (16303): High Performance Effort optimization mode selected -- timing performance will be prioritized at the potential cost of increased compilation time\n",
            "\u001b[0m\u001b[0;32m    Info (16304): Mode behavior is affected by advanced setting Fitter Effort (default for this mode is Standard Fit)\n",
            "\u001b[0m\u001b[0;36mWarning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.\n",
            "\u001b[0m\u001b[0;32mInfo (20029): Only one processor detected - disabling parallel compilation\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ic/sr_nor.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: sr_nor_sync-rtl File: /content/openfpga-pong/src/fpga/core/pong/ic/sr_nor.vhd Line: 15\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: sr_nor_sync File: /content/openfpga-pong/src/fpga/core/pong/ic/sr_nor.vhd Line: 4\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ic/sr_nand.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: sr_nand_sync-rtl File: /content/openfpga-pong/src/fpga/core/pong/ic/sr_nand.vhd Line: 15\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: sr_nand_sync File: /content/openfpga-pong/src/fpga/core/pong/ic/sr_nand.vhd Line: 4\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ic/synchronizer.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: synchronizer-rtl File: /content/openfpga-pong/src/fpga/core/pong/ic/synchronizer.vhd Line: 31\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: synchronizer File: /content/openfpga-pong/src/fpga/core/pong/ic/synchronizer.vhd Line: 9\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ic/7474_sync.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: ic7474-rtl File: /content/openfpga-pong/src/fpga/core/pong/ic/7474_sync.vhd Line: 18\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: ic7474 File: /content/openfpga-pong/src/fpga/core/pong/ic/7474_sync.vhd Line: 4\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/game_control.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: game_control-rtl File: /content/openfpga-pong/src/fpga/core/pong/game_control.vhd Line: 25\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: game_control File: /content/openfpga-pong/src/fpga/core/pong/game_control.vhd Line: 4\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ic/555_timer.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: ic555-rtl File: /content/openfpga-pong/src/fpga/core/pong/ic/555_timer.vhd Line: 16\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: ic555 File: /content/openfpga-pong/src/fpga/core/pong/ic/555_timer.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/sound.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: sound-rtl File: /content/openfpga-pong/src/fpga/core/pong/sound.vhd Line: 31\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: sound File: /content/openfpga-pong/src/fpga/core/pong/sound.vhd Line: 5\n",
            "\u001b[0m\u001b[0;36mWarning (12019): Can't analyze file -- file core/pong/ic/jk_clr_flip_flop.vhd is missing\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ic/74153_mux.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: ic74153-rtl File: /content/openfpga-pong/src/fpga/core/pong/ic/74153_mux.vhd Line: 21\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: ic74153 File: /content/openfpga-pong/src/fpga/core/pong/ic/74153_mux.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ic/74153_double_mux.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: ic74153_double-rtl File: /content/openfpga-pong/src/fpga/core/pong/ic/74153_double_mux.vhd Line: 28\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: ic74153_double File: /content/openfpga-pong/src/fpga/core/pong/ic/74153_double_mux.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ic/7490_decade_counter.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: ic7490-rtl File: /content/openfpga-pong/src/fpga/core/pong/ic/7490_decade_counter.vhd Line: 21\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: ic7490 File: /content/openfpga-pong/src/fpga/core/pong/ic/7490_decade_counter.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ic/7448_bcd_7_segment.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: ic7448-rtl File: /content/openfpga-pong/src/fpga/core/pong/ic/7448_bcd_7_segment.vhd Line: 15\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: ic7448 File: /content/openfpga-pong/src/fpga/core/pong/ic/7448_bcd_7_segment.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/score/segments.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: score_segments-rtl File: /content/openfpga-pong/src/fpga/core/pong/score/segments.vhd Line: 21\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: score_segments File: /content/openfpga-pong/src/fpga/core/pong/score/segments.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/score/score.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: score-rtl File: /content/openfpga-pong/src/fpga/core/pong/score/score.vhd Line: 42\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: score File: /content/openfpga-pong/src/fpga/core/pong/score/score.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/score/counter.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: score_counter-rtl File: /content/openfpga-pong/src/fpga/core/pong/score/counter.vhd Line: 27\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: score_counter File: /content/openfpga-pong/src/fpga/core/pong/score/counter.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/score/bcd.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: score_bcd-rtl File: /content/openfpga-pong/src/fpga/core/pong/score/bcd.vhd Line: 29\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: score_bcd File: /content/openfpga-pong/src/fpga/core/pong/score/bcd.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ic/7483_full_adder_without_carry.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: ic7483_no_carry-rtl File: /content/openfpga-pong/src/fpga/core/pong/ic/7483_full_adder_without_carry.vhd Line: 14\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: ic7483_no_carry File: /content/openfpga-pong/src/fpga/core/pong/ic/7483_full_adder_without_carry.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ball/vertical.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: ball_vertical-rtl File: /content/openfpga-pong/src/fpga/core/pong/ball/vertical.vhd Line: 31\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: ball_vertical File: /content/openfpga-pong/src/fpga/core/pong/ball/vertical.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ic/9316_sync_4bit_counter.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: ic9316-rtl File: /content/openfpga-pong/src/fpga/core/pong/ic/9316_sync_4bit_counter.vhd Line: 22\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: ic9316 File: /content/openfpga-pong/src/fpga/core/pong/ic/9316_sync_4bit_counter.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ic/9316_internal.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: ic9316_flipflop-rtl File: /content/openfpga-pong/src/fpga/core/pong/ic/9316_internal.vhd Line: 27\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: ic9316_flipflop File: /content/openfpga-pong/src/fpga/core/pong/ic/9316_internal.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ball/move.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: ball_move-rtl File: /content/openfpga-pong/src/fpga/core/pong/ball/move.vhd Line: 20\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: ball_move File: /content/openfpga-pong/src/fpga/core/pong/ball/move.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ball/horizontal_position.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: ball_horizontal_position-rtl File: /content/openfpga-pong/src/fpga/core/pong/ball/horizontal_position.vhd Line: 22\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: ball_horizontal_position File: /content/openfpga-pong/src/fpga/core/pong/ball/horizontal_position.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ball/horizontal_direction.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: ball_horizontal_direction-rtl File: /content/openfpga-pong/src/fpga/core/pong/ball/horizontal_direction.vhd Line: 28\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: ball_horizontal_direction File: /content/openfpga-pong/src/fpga/core/pong/ball/horizontal_direction.vhd Line: 4\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ball/horizontal.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: ball_horizontal-rtl File: /content/openfpga-pong/src/fpga/core/pong/ball/horizontal.vhd Line: 33\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: ball_horizontal File: /content/openfpga-pong/src/fpga/core/pong/ball/horizontal.vhd Line: 4\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/paddle.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: paddle-rtl File: /content/openfpga-pong/src/fpga/core/pong/paddle.vhd Line: 31\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: paddle File: /content/openfpga-pong/src/fpga/core/pong/paddle.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ic/74107_neg_flip_flop.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: ic74107-rtl File: /content/openfpga-pong/src/fpga/core/pong/ic/74107_neg_flip_flop.vhd Line: 19\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: ic74107 File: /content/openfpga-pong/src/fpga/core/pong/ic/74107_neg_flip_flop.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/ic/7493_4bit_counter.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: ic7493-rtl File: /content/openfpga-pong/src/fpga/core/pong/ic/7493_4bit_counter.vhd Line: 19\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: ic7493 File: /content/openfpga-pong/src/fpga/core/pong/ic/7493_4bit_counter.vhd Line: 5\n",
            "\u001b[0m\u001b[0;36mWarning (12019): Can't analyze file -- file core/pong/ic/7474_flip_flop.vhd is missing\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/video/vsync.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: vsync-rtl File: /content/openfpga-pong/src/fpga/core/pong/video/vsync.vhd Line: 19\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: vsync File: /content/openfpga-pong/src/fpga/core/pong/video/vsync.vhd Line: 4\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/video/video.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: video-rtl File: /content/openfpga-pong/src/fpga/core/pong/video/video.vhd Line: 36\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: video File: /content/openfpga-pong/src/fpga/core/pong/video/video.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/video/vcounter.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: vcounter-rtl File: /content/openfpga-pong/src/fpga/core/pong/video/vcounter.vhd Line: 15\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: vcounter File: /content/openfpga-pong/src/fpga/core/pong/video/vcounter.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/video/hsync.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: hsync-rtl File: /content/openfpga-pong/src/fpga/core/pong/video/hsync.vhd Line: 19\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: hsync File: /content/openfpga-pong/src/fpga/core/pong/video/hsync.vhd Line: 4\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/video/hcounter.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: hcounter-rtl File: /content/openfpga-pong/src/fpga/core/pong/video/hcounter.vhd Line: 16\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: hcounter File: /content/openfpga-pong/src/fpga/core/pong/video/hcounter.vhd Line: 6\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/pong.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: pong-rtl File: /content/openfpga-pong/src/fpga/core/pong/pong.vhd Line: 41\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: pong File: /content/openfpga-pong/src/fpga/core/pong/pong.vhd Line: 5\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 2 design units, including 1 entities, in source file core/pong/net.vhd\n",
            "\u001b[0m\u001b[0;32m    Info (12022): Found design unit 1: net-rtl File: /content/openfpga-pong/src/fpga/core/pong/net.vhd Line: 18\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: net File: /content/openfpga-pong/src/fpga/core/pong/net.vhd Line: 4\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 1 design units, including 1 entities, in source file apf/apf_top.v\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: apf_top File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 44\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 4 design units, including 4 entities, in source file apf/common.v\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: synch_2 File: /content/openfpga-pong/src/fpga/apf/common.v Line: 35\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 2: synch_3 File: /content/openfpga-pong/src/fpga/apf/common.v Line: 58\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 3: bram_block_dp File: /content/openfpga-pong/src/fpga/apf/common.v Line: 78\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 4: bram_block_dp_nonstd File: /content/openfpga-pong/src/fpga/apf/common.v Line: 116\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 1 design units, including 1 entities, in source file apf/io_bridge_peripheral.v\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: io_bridge_peripheral File: /content/openfpga-pong/src/fpga/apf/io_bridge_peripheral.v Line: 52\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 1 design units, including 1 entities, in source file apf/io_pad_controller.v\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: io_pad_controller File: /content/openfpga-pong/src/fpga/apf/io_pad_controller.v Line: 41\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 1 design units, including 1 entities, in source file apf/mf_ddio_bidir_12.v\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: mf_ddio_bidir_12 File: /content/openfpga-pong/src/fpga/apf/mf_ddio_bidir_12.v Line: 40\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 1 design units, including 1 entities, in source file apf/mf_datatable.v\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: mf_datatable File: /content/openfpga-pong/src/fpga/apf/mf_datatable.v Line: 40\n",
            "\u001b[0m\u001b[0;36mWarning (10275): Verilog HDL Module Instantiation warning at core_top.v(403): ignored dangling comma in List of Port Connections File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 403\n",
            "\u001b[0m\u001b[0;36m\u001b[0m\u001b[0;32mInfo (12021): Found 1 design units, including 1 entities, in source file core/core_top.v\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: core_top File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 9\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 1 design units, including 1 entities, in source file core/core_bridge_cmd.v\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: core_bridge_cmd File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 18\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 1 design units, including 1 entities, in source file core/mf_pllbase.v\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: mf_pllbase File: /content/openfpga-pong/src/fpga/core/mf_pllbase.v Line: 8\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 1 design units, including 1 entities, in source file core/mf_pllbase/mf_pllbase_0002.v\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: mf_pllbase_0002 File: /content/openfpga-pong/src/fpga/core/mf_pllbase/mf_pllbase_0002.v Line: 2\n",
            "\u001b[0m\u001b[0;32mInfo (12127): Elaborating entity \"apf_top\" for the top level hierarchy\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"mf_ddio_bidir_12\" for hierarchy \"mf_ddio_bidir_12:isco\" File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 253\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"altddio_bidir\" for hierarchy \"mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component\" File: /content/openfpga-pong/src/fpga/apf/mf_ddio_bidir_12.v Line: 81\n",
            "\u001b[0m\u001b[0;32mInfo (12130): Elaborated megafunction instantiation \"mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component\" File: /content/openfpga-pong/src/fpga/apf/mf_ddio_bidir_12.v Line: 81\n",
            "\u001b[0m\u001b[0;32mInfo (12133): Instantiated megafunction \"mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component\" with the following parameter: File: /content/openfpga-pong/src/fpga/apf/mf_ddio_bidir_12.v Line: 81\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"extend_oe_disable\" = \"OFF\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"implement_input_in_lcell\" = \"OFF\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"intended_device_family\" = \"Cyclone V\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"invert_output\" = \"OFF\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"lpm_hint\" = \"UNUSED\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"lpm_type\" = \"altddio_bidir\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"oe_reg\" = \"UNREGISTERED\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"power_up_high\" = \"OFF\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"width\" = \"12\"\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 1 design units, including 1 entities, in source file db/ddio_bidir_euo.tdf\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: ddio_bidir_euo File: /content/openfpga-pong/src/fpga/db/ddio_bidir_euo.tdf Line: 33\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ddio_bidir_euo\" for hierarchy \"mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated\" File: /root/intelFPGA_lite/22.1std/quartus/libraries/megafunctions/altddio_bidir.tdf Line: 116\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"io_pad_controller\" for hierarchy \"io_pad_controller:ipm\" File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 314\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"synch_3\" for hierarchy \"io_pad_controller:ipm|synch_3:s00\" File: /content/openfpga-pong/src/fpga/apf/io_pad_controller.v Line: 65\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"io_bridge_peripheral\" for hierarchy \"io_bridge_peripheral:ibs\" File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 343\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"core_top\" for hierarchy \"core_top:ic\" File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 472\n",
            "\u001b[0m\u001b[0;36mWarning (10230): Verilog HDL assignment warning at core_top.v(538): truncated value with size 32 to match size of target (21) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 538\n",
            "\u001b[0m\u001b[0;36mWarning (10762): Verilog HDL Case Statement warning at core_top.v(267): can't check case statement for completeness because the case expression has too many possible states File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;36mWarning (10270): Verilog HDL Case Statement warning at core_top.v(267): incomplete case statement has no default case item File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;36mWarning (10240): Verilog HDL Always Construct warning at core_top.v(267): inferring latch(es) for variable \"bridge_rd_data\", which holds its previous value in one or more paths through the always construct File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;36mWarning (10762): Verilog HDL Case Statement warning at core_top.v(279): can't check case statement for completeness because the case expression has too many possible states File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 279\n",
            "\u001b[0m\u001b[0;36mWarning (10230): Verilog HDL assignment warning at core_top.v(431): truncated value with size 32 to match size of target (1) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 431\n",
            "\u001b[0m\u001b[0;36mWarning (10030): Net \"audgen_accum[1..0]\" at core_top.v(536) has no driver or initial value, using a default initial value '0' File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 536\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram0_a\" at core_top.v(77) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 77\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram1_a\" at core_top.v(90) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 90\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"dram_a\" at core_top.v(106) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 106\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"dram_ba\" at core_top.v(107) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 107\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"dram_dqm\" at core_top.v(109) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 109\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"sram_a\" at core_top.v(119) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 119\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram0_clk\" at core_top.v(80) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 80\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram0_adv_n\" at core_top.v(81) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 81\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram0_cre\" at core_top.v(82) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 82\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram0_ce0_n\" at core_top.v(83) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 83\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram0_ce1_n\" at core_top.v(84) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 84\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram0_oe_n\" at core_top.v(85) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 85\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram0_we_n\" at core_top.v(86) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 86\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram0_ub_n\" at core_top.v(87) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 87\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram0_lb_n\" at core_top.v(88) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 88\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram1_clk\" at core_top.v(93) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 93\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram1_adv_n\" at core_top.v(94) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 94\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram1_cre\" at core_top.v(95) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 95\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram1_ce0_n\" at core_top.v(96) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 96\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram1_ce1_n\" at core_top.v(97) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 97\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram1_oe_n\" at core_top.v(98) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 98\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram1_we_n\" at core_top.v(99) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 99\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram1_ub_n\" at core_top.v(100) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 100\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"cram1_lb_n\" at core_top.v(101) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 101\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"dram_clk\" at core_top.v(110) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 110\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"dram_cke\" at core_top.v(111) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 111\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"dram_ras_n\" at core_top.v(112) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 112\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"dram_cas_n\" at core_top.v(113) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 113\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"dram_we_n\" at core_top.v(114) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 114\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"sram_oe_n\" at core_top.v(121) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 121\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"sram_we_n\" at core_top.v(122) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 122\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"sram_ub_n\" at core_top.v(123) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 123\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"sram_lb_n\" at core_top.v(124) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 124\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"dbg_tx\" at core_top.v(134) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 134\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"user1\" at core_top.v(140) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 140\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"aux_scl\" at core_top.v(147) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 147\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"vpll_feed\" at core_top.v(151) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 151\n",
            "\u001b[0m\u001b[0;36mWarning (10034): Output port \"video_skip\" at core_top.v(164) has no driver File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 164\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[0]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[1]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[2]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[3]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[4]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[5]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[6]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[7]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[8]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[9]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[10]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[11]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[12]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[13]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[14]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[15]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[16]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[17]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[18]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[19]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[20]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[21]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[22]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[23]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[24]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[25]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[26]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[27]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[28]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[29]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[30]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (10041): Inferred latch for \"bridge_rd_data[31]\" at core_top.v(267) File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 267\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"core_bridge_cmd\" for hierarchy \"core_top:ic|core_bridge_cmd:icb\" File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 403\n",
            "\u001b[0m\u001b[0;36mWarning (10036): Verilog HDL or VHDL warning at core_bridge_cmd.v(107): object \"host_24\" assigned a value but never read File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 107\n",
            "\u001b[0m\u001b[0;36mWarning (10036): Verilog HDL or VHDL warning at core_bridge_cmd.v(108): object \"host_28\" assigned a value but never read File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 108\n",
            "\u001b[0m\u001b[0;36mWarning (10036): Verilog HDL or VHDL warning at core_bridge_cmd.v(109): object \"host_2C\" assigned a value but never read File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 109\n",
            "\u001b[0m\u001b[0;36mWarning (10858): Verilog HDL warning at core_bridge_cmd.v(114): object host_4C used but never assigned File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 114\n",
            "\u001b[0m\u001b[0;36mWarning (10858): Verilog HDL warning at core_bridge_cmd.v(135): object target_20 used but never assigned File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 135\n",
            "\u001b[0m\u001b[0;36mWarning (10858): Verilog HDL warning at core_bridge_cmd.v(136): object target_24 used but never assigned File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 136\n",
            "\u001b[0m\u001b[0;36mWarning (10858): Verilog HDL warning at core_bridge_cmd.v(137): object target_28 used but never assigned File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 137\n",
            "\u001b[0m\u001b[0;36mWarning (10858): Verilog HDL warning at core_bridge_cmd.v(138): object target_2C used but never assigned File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 138\n",
            "\u001b[0m\u001b[0;36mWarning (10036): Verilog HDL or VHDL warning at core_bridge_cmd.v(140): object \"target_40\" assigned a value but never read File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 140\n",
            "\u001b[0m\u001b[0;36mWarning (10036): Verilog HDL or VHDL warning at core_bridge_cmd.v(141): object \"target_44\" assigned a value but never read File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 141\n",
            "\u001b[0m\u001b[0;36mWarning (10036): Verilog HDL or VHDL warning at core_bridge_cmd.v(142): object \"target_48\" assigned a value but never read File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 142\n",
            "\u001b[0m\u001b[0;36mWarning (10036): Verilog HDL or VHDL warning at core_bridge_cmd.v(143): object \"target_4C\" assigned a value but never read File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 143\n",
            "\u001b[0m\u001b[0;36mWarning (10230): Verilog HDL assignment warning at core_bridge_cmd.v(179): truncated value with size 32 to match size of target (10) File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 179\n",
            "\u001b[0m\u001b[0;36mWarning (10762): Verilog HDL Case Statement warning at core_bridge_cmd.v(182): can't check case statement for completeness because the case expression has too many possible states File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 182\n",
            "\u001b[0m\u001b[0;36mWarning (10762): Verilog HDL Case Statement warning at core_bridge_cmd.v(217): can't check case statement for completeness because the case expression has too many possible states File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 217\n",
            "\u001b[0m\u001b[0;36mWarning (10030): Net \"host_4C\" at core_bridge_cmd.v(114) has no driver or initial value, using a default initial value '0' File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 114\n",
            "\u001b[0m\u001b[0;36mWarning (10030): Net \"target_20\" at core_bridge_cmd.v(135) has no driver or initial value, using a default initial value '0' File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 135\n",
            "\u001b[0m\u001b[0;36mWarning (10030): Net \"target_24\" at core_bridge_cmd.v(136) has no driver or initial value, using a default initial value '0' File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 136\n",
            "\u001b[0m\u001b[0;36mWarning (10030): Net \"target_28\" at core_bridge_cmd.v(137) has no driver or initial value, using a default initial value '0' File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 137\n",
            "\u001b[0m\u001b[0;36mWarning (10030): Net \"target_2C\" at core_bridge_cmd.v(138) has no driver or initial value, using a default initial value '0' File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 138\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"mf_datatable\" for hierarchy \"core_top:ic|core_bridge_cmd:icb|mf_datatable:idt\" File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 432\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"altsyncram\" for hierarchy \"core_top:ic|core_bridge_cmd:icb|mf_datatable:idt|altsyncram:altsyncram_component\" File: /content/openfpga-pong/src/fpga/apf/mf_datatable.v Line: 100\n",
            "\u001b[0m\u001b[0;32mInfo (12130): Elaborated megafunction instantiation \"core_top:ic|core_bridge_cmd:icb|mf_datatable:idt|altsyncram:altsyncram_component\" File: /content/openfpga-pong/src/fpga/apf/mf_datatable.v Line: 100\n",
            "\u001b[0m\u001b[0;32mInfo (12133): Instantiated megafunction \"core_top:ic|core_bridge_cmd:icb|mf_datatable:idt|altsyncram:altsyncram_component\" with the following parameter: File: /content/openfpga-pong/src/fpga/apf/mf_datatable.v Line: 100\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"address_reg_b\" = \"CLOCK1\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"clock_enable_input_a\" = \"BYPASS\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"clock_enable_input_b\" = \"BYPASS\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"clock_enable_output_a\" = \"BYPASS\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"clock_enable_output_b\" = \"BYPASS\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"indata_reg_b\" = \"CLOCK1\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"init_file\" = \"./apf/build_id.mif\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"intended_device_family\" = \"Cyclone V\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"lpm_type\" = \"altsyncram\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"numwords_a\" = \"256\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"numwords_b\" = \"256\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"outdata_aclr_a\" = \"NONE\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"outdata_aclr_b\" = \"NONE\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"outdata_reg_a\" = \"CLOCK0\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"outdata_reg_b\" = \"CLOCK1\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"power_up_uninitialized\" = \"FALSE\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"read_during_write_mode_port_b\" = \"NEW_DATA_NO_NBE_READ\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"widthad_a\" = \"8\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"widthad_b\" = \"8\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"width_a\" = \"32\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"width_b\" = \"32\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"width_byteena_a\" = \"1\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"width_byteena_b\" = \"1\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"wrcontrol_wraddress_reg_b\" = \"CLOCK1\"\n",
            "\u001b[0m\u001b[0;32mInfo (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ltk2.tdf\n",
            "\u001b[0m\u001b[0;32m    Info (12023): Found entity 1: altsyncram_ltk2 File: /content/openfpga-pong/src/fpga/db/altsyncram_ltk2.tdf Line: 28\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"altsyncram_ltk2\" for hierarchy \"core_top:ic|core_bridge_cmd:icb|mf_datatable:idt|altsyncram:altsyncram_component|altsyncram_ltk2:auto_generated\" File: /root/intelFPGA_lite/22.1std/quartus/libraries/megafunctions/altsyncram.tdf Line: 792\n",
            "\u001b[0m\u001b[0;36mWarning (113028): 253 out of 256 addresses are uninitialized. The Quartus Prime software will initialize them to \"0\". There are 2 warnings found, and 2 warnings are reported. File: /content/openfpga-pong/src/fpga/apf/build_id.mif Line: 1\n",
            "\u001b[0m\u001b[0;36m    Warning (113027): Addresses ranging from 0 to 223 are not initialized File: /content/openfpga-pong/src/fpga/apf/build_id.mif Line: 1\n",
            "\u001b[0m\u001b[0;36m    Warning (113027): Addresses ranging from 227 to 255 are not initialized File: /content/openfpga-pong/src/fpga/apf/build_id.mif Line: 1\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"synch_2\" for hierarchy \"core_top:ic|synch_2:cont_1_s\" File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 414\n",
            "\u001b[0m\u001b[0;36mWarning (10230): Verilog HDL assignment warning at common.v(47): truncated value with size 32 to match size of target (1) File: /content/openfpga-pong/src/fpga/apf/common.v Line: 47\n",
            "\u001b[0m\u001b[0;36mWarning (10230): Verilog HDL assignment warning at common.v(48): truncated value with size 32 to match size of target (1) File: /content/openfpga-pong/src/fpga/apf/common.v Line: 48\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"pong\" for hierarchy \"core_top:ic|pong:pong\" File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 474\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"video\" for hierarchy \"core_top:ic|pong:pong|video:VIDEO_GEN\" File: /content/openfpga-pong/src/fpga/core/pong/pong.vhd Line: 96\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"hcounter\" for hierarchy \"core_top:ic|pong:pong|video:VIDEO_GEN|hcounter:HCOUNTER\" File: /content/openfpga-pong/src/fpga/core/pong/video/video.vhd Line: 55\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ic7474\" for hierarchy \"core_top:ic|pong:pong|video:VIDEO_GEN|hcounter:HCOUNTER|ic7474:E7b\" File: /content/openfpga-pong/src/fpga/core/pong/video/hcounter.vhd Line: 27\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"synchronizer\" for hierarchy \"core_top:ic|pong:pong|video:VIDEO_GEN|hcounter:HCOUNTER|ic7474:E7b|synchronizer:sync\" File: /content/openfpga-pong/src/fpga/core/pong/ic/7474_sync.vhd Line: 24\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ic74107\" for hierarchy \"core_top:ic|pong:pong|video:VIDEO_GEN|hcounter:HCOUNTER|ic74107:F6b\" File: /content/openfpga-pong/src/fpga/core/pong/video/hcounter.vhd Line: 37\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"synchronizer\" for hierarchy \"core_top:ic|pong:pong|video:VIDEO_GEN|hcounter:HCOUNTER|ic74107:F6b|synchronizer:sync\" File: /content/openfpga-pong/src/fpga/core/pong/ic/74107_neg_flip_flop.vhd Line: 26\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ic7493\" for hierarchy \"core_top:ic|pong:pong|video:VIDEO_GEN|hcounter:HCOUNTER|ic7493:F8\" File: /content/openfpga-pong/src/fpga/core/pong/video/hcounter.vhd Line: 50\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"vcounter\" for hierarchy \"core_top:ic|pong:pong|video:VIDEO_GEN|vcounter:VCOUNTER\" File: /content/openfpga-pong/src/fpga/core/pong/video/video.vhd Line: 56\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"hsync\" for hierarchy \"core_top:ic|pong:pong|video:VIDEO_GEN|hsync:HSYNC\" File: /content/openfpga-pong/src/fpga/core/pong/video/video.vhd Line: 58\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"sr_nand_sync\" for hierarchy \"core_top:ic|pong:pong|video:VIDEO_GEN|hsync:HSYNC|sr_nand_sync:H5\" File: /content/openfpga-pong/src/fpga/core/pong/video/hsync.vhd Line: 25\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"vsync\" for hierarchy \"core_top:ic|pong:pong|video:VIDEO_GEN|vsync:VSYNC\" File: /content/openfpga-pong/src/fpga/core/pong/video/video.vhd Line: 70\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"sr_nor_sync\" for hierarchy \"core_top:ic|pong:pong|video:VIDEO_GEN|vsync:VSYNC|sr_nor_sync:F5\" File: /content/openfpga-pong/src/fpga/core/pong/video/vsync.vhd Line: 22\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"net\" for hierarchy \"core_top:ic|pong:pong|video:VIDEO_GEN|net:NET_GEN\" File: /content/openfpga-pong/src/fpga/core/pong/video/video.vhd Line: 82\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"paddle\" for hierarchy \"core_top:ic|pong:pong|paddle:PAD1\" File: /content/openfpga-pong/src/fpga/core/pong/pong.vhd Line: 123\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"score\" for hierarchy \"core_top:ic|pong:pong|score:SCORE\" File: /content/openfpga-pong/src/fpga/core/pong/pong.vhd Line: 169\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"score_counter\" for hierarchy \"core_top:ic|pong:pong|score:SCORE|score_counter:COUNTER\" File: /content/openfpga-pong/src/fpga/core/pong/score/score.vhd Line: 48\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ic7490\" for hierarchy \"core_top:ic|pong:pong|score:SCORE|score_counter:COUNTER|ic7490:C7\" File: /content/openfpga-pong/src/fpga/core/pong/score/counter.vhd Line: 44\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"score_bcd\" for hierarchy \"core_top:ic|pong:pong|score:SCORE|score_bcd:BCD\" File: /content/openfpga-pong/src/fpga/core/pong/score/score.vhd Line: 67\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ic74153_double\" for hierarchy \"core_top:ic|pong:pong|score:SCORE|score_bcd:BCD|ic74153_double:C6\" File: /content/openfpga-pong/src/fpga/core/pong/score/bcd.vhd Line: 42\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ic74153\" for hierarchy \"core_top:ic|pong:pong|score:SCORE|score_bcd:BCD|ic74153_double:C6|ic74153:A\" File: /content/openfpga-pong/src/fpga/core/pong/ic/74153_double_mux.vhd Line: 31\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ic7448\" for hierarchy \"core_top:ic|pong:pong|score:SCORE|score_bcd:BCD|ic7448:C5\" File: /content/openfpga-pong/src/fpga/core/pong/score/bcd.vhd Line: 90\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"score_segments\" for hierarchy \"core_top:ic|pong:pong|score:SCORE|score_segments:SEG\" File: /content/openfpga-pong/src/fpga/core/pong/score/score.vhd Line: 89\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ball_horizontal\" for hierarchy \"core_top:ic|pong:pong|ball_horizontal:BALL_HORIZONTAL\" File: /content/openfpga-pong/src/fpga/core/pong/pong.vhd Line: 203\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ball_move\" for hierarchy \"core_top:ic|pong:pong|ball_horizontal:BALL_HORIZONTAL|ball_move:BALL_MOVE\" File: /content/openfpga-pong/src/fpga/core/pong/ball/horizontal.vhd Line: 39\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ball_horizontal_direction\" for hierarchy \"core_top:ic|pong:pong|ball_horizontal:BALL_HORIZONTAL|ball_horizontal_direction:BALL_AB\" File: /content/openfpga-pong/src/fpga/core/pong/ball/horizontal.vhd Line: 50\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ball_horizontal_position\" for hierarchy \"core_top:ic|pong:pong|ball_horizontal:BALL_HORIZONTAL|ball_horizontal_position:BALL_POSITION\" File: /content/openfpga-pong/src/fpga/core/pong/ball/horizontal.vhd Line: 68\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ic9316\" for hierarchy \"core_top:ic|pong:pong|ball_horizontal:BALL_HORIZONTAL|ball_horizontal_position:BALL_POSITION|ic9316:G7\" File: /content/openfpga-pong/src/fpga/core/pong/ball/horizontal_position.vhd Line: 34\n",
            "\u001b[0m\u001b[0;36mWarning (10445): VHDL Subtype or Type Declaration warning at 9316_internal.vhd(15): subtype or type has null range File: /content/openfpga-pong/src/fpga/core/pong/ic/9316_internal.vhd Line: 15\n",
            "\u001b[0m\u001b[0;36mWarning (10296): VHDL warning at 9316_sync_4bit_counter.vhd(29): ignored assignment of value to null range File: /content/openfpga-pong/src/fpga/core/pong/ic/9316_sync_4bit_counter.vhd Line: 29\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ic9316_flipflop\" for hierarchy \"core_top:ic|pong:pong|ball_horizontal:BALL_HORIZONTAL|ball_horizontal_position:BALL_POSITION|ic9316:G7|ic9316_flipflop:A_FF\" File: /content/openfpga-pong/src/fpga/core/pong/ic/9316_sync_4bit_counter.vhd Line: 24\n",
            "\u001b[0m\u001b[0;36mWarning (10445): VHDL Subtype or Type Declaration warning at 9316_internal.vhd(15): subtype or type has null range File: /content/openfpga-pong/src/fpga/core/pong/ic/9316_internal.vhd Line: 15\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ic9316_flipflop\" for hierarchy \"core_top:ic|pong:pong|ball_horizontal:BALL_HORIZONTAL|ball_horizontal_position:BALL_POSITION|ic9316:G7|ic9316_flipflop:B_FF\" File: /content/openfpga-pong/src/fpga/core/pong/ic/9316_sync_4bit_counter.vhd Line: 40\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ic9316_flipflop\" for hierarchy \"core_top:ic|pong:pong|ball_horizontal:BALL_HORIZONTAL|ball_horizontal_position:BALL_POSITION|ic9316:G7|ic9316_flipflop:C_FF\" File: /content/openfpga-pong/src/fpga/core/pong/ic/9316_sync_4bit_counter.vhd Line: 56\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ic9316_flipflop\" for hierarchy \"core_top:ic|pong:pong|ball_horizontal:BALL_HORIZONTAL|ball_horizontal_position:BALL_POSITION|ic9316:G7|ic9316_flipflop:D_FF\" File: /content/openfpga-pong/src/fpga/core/pong/ic/9316_sync_4bit_counter.vhd Line: 72\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ball_vertical\" for hierarchy \"core_top:ic|pong:pong|ball_vertical:BALL_VERTICAL\" File: /content/openfpga-pong/src/fpga/core/pong/pong.vhd Line: 229\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ic7483_no_carry\" for hierarchy \"core_top:ic|pong:pong|ball_vertical:BALL_VERTICAL|ic7483_no_carry:B4\" File: /content/openfpga-pong/src/fpga/core/pong/ball/vertical.vhd Line: 90\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"sound\" for hierarchy \"core_top:ic|pong:pong|sound:SOUND_GEN\" File: /content/openfpga-pong/src/fpga/core/pong/pong.vhd Line: 253\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ic555\" for hierarchy \"core_top:ic|pong:pong|sound:SOUND_GEN|ic555:G4_TIMER\" File: /content/openfpga-pong/src/fpga/core/pong/sound.vhd Line: 67\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"game_control\" for hierarchy \"core_top:ic|pong:pong|game_control:CONTROL\" File: /content/openfpga-pong/src/fpga/core/pong/pong.vhd Line: 277\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"ic555\" for hierarchy \"core_top:ic|pong:pong|game_control:CONTROL|ic555:F4\" File: /content/openfpga-pong/src/fpga/core/pong/game_control.vhd Line: 36\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"synch_3\" for hierarchy \"core_top:ic|synch_3:s5\" File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 562\n",
            "\u001b[0m\u001b[0;36mWarning (10230): Verilog HDL assignment warning at common.v(70): truncated value with size 32 to match size of target (1) File: /content/openfpga-pong/src/fpga/apf/common.v Line: 70\n",
            "\u001b[0m\u001b[0;36mWarning (10230): Verilog HDL assignment warning at common.v(71): truncated value with size 32 to match size of target (1) File: /content/openfpga-pong/src/fpga/apf/common.v Line: 71\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"mf_pllbase\" for hierarchy \"core_top:ic|mf_pllbase:mp1\" File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 610\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"mf_pllbase_0002\" for hierarchy \"core_top:ic|mf_pllbase:mp1|mf_pllbase_0002:mf_pllbase_inst\" File: /content/openfpga-pong/src/fpga/core/mf_pllbase.v Line: 28\n",
            "\u001b[0m\u001b[0;32mInfo (12128): Elaborating entity \"altera_pll\" for hierarchy \"core_top:ic|mf_pllbase:mp1|mf_pllbase_0002:mf_pllbase_inst|altera_pll:altera_pll_i\" File: /content/openfpga-pong/src/fpga/core/mf_pllbase/mf_pllbase_0002.v Line: 97\n",
            "\u001b[0m\u001b[0;32mInfo (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"wire_to_nowhere_64\" into its bus\n",
            "\u001b[0m\u001b[0;32mInfo (12130): Elaborated megafunction instantiation \"core_top:ic|mf_pllbase:mp1|mf_pllbase_0002:mf_pllbase_inst|altera_pll:altera_pll_i\" File: /content/openfpga-pong/src/fpga/core/mf_pllbase/mf_pllbase_0002.v Line: 97\n",
            "\u001b[0m\u001b[0;32mInfo (12133): Instantiated megafunction \"core_top:ic|mf_pllbase:mp1|mf_pllbase_0002:mf_pllbase_inst|altera_pll:altera_pll_i\" with the following parameter: File: /content/openfpga-pong/src/fpga/core/mf_pllbase/mf_pllbase_0002.v Line: 97\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"fractional_vco_multiplier\" = \"true\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"reference_clock_frequency\" = \"74.25 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"operation_mode\" = \"normal\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"number_of_clocks\" = \"5\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"output_clock_frequency0\" = \"7.158999 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"phase_shift0\" = \"0 ps\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"duty_cycle0\" = \"50\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"output_clock_frequency1\" = \"7.158999 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"phase_shift1\" = \"34921 ps\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"duty_cycle1\" = \"50\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"output_clock_frequency2\" = \"28.635997 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"phase_shift2\" = \"0 ps\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"duty_cycle2\" = \"50\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"output_clock_frequency3\" = \"132.766896 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"phase_shift3\" = \"6590 ps\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"duty_cycle3\" = \"50\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"output_clock_frequency4\" = \"132.766892 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"phase_shift4\" = \"5649 ps\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"duty_cycle4\" = \"50\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"output_clock_frequency5\" = \"0 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"phase_shift5\" = \"0 ps\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"duty_cycle5\" = \"50\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"output_clock_frequency6\" = \"0 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"phase_shift6\" = \"0 ps\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"duty_cycle6\" = \"50\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"output_clock_frequency7\" = \"0 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"phase_shift7\" = \"0 ps\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"duty_cycle7\" = \"50\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"output_clock_frequency8\" = \"0 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"phase_shift8\" = \"0 ps\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"duty_cycle8\" = \"50\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"output_clock_frequency9\" = \"0 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"phase_shift9\" = \"0 ps\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"duty_cycle9\" = \"50\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"output_clock_frequency10\" = \"0 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"phase_shift10\" = \"0 ps\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"duty_cycle10\" = \"50\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"output_clock_frequency11\" = \"0 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"phase_shift11\" = \"0 ps\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"duty_cycle11\" = \"50\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"output_clock_frequency12\" = \"0 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"phase_shift12\" = \"0 ps\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"duty_cycle12\" = \"50\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"output_clock_frequency13\" = \"0 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"phase_shift13\" = \"0 ps\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"duty_cycle13\" = \"50\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"output_clock_frequency14\" = \"0 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"phase_shift14\" = \"0 ps\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"duty_cycle14\" = \"50\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"output_clock_frequency15\" = \"0 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"phase_shift15\" = \"0 ps\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"duty_cycle15\" = \"50\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"output_clock_frequency16\" = \"0 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"phase_shift16\" = \"0 ps\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"duty_cycle16\" = \"50\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"output_clock_frequency17\" = \"0 MHz\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"phase_shift17\" = \"0 ps\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"duty_cycle17\" = \"50\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"pll_type\" = \"General\"\n",
            "\u001b[0m\u001b[0;32m    Info (12134): Parameter \"pll_subtype\" = \"General\"\n",
            "\u001b[0m\u001b[0;36mWarning (14284): Synthesized away the following node(s):\n",
            "\u001b[0m\u001b[0;36m    Warning (14285): Synthesized away the following PLL node(s):\n",
            "\u001b[0m\u001b[0;36m        Warning (14320): Synthesized away node \"core_top:ic|mf_pllbase:mp1|mf_pllbase_0002:mf_pllbase_inst|altera_pll:altera_pll_i|outclk_wire[3]\" File: /root/intelFPGA_lite/22.1std/quartus/libraries/megafunctions/altera_pll.v Line: 749\n",
            "\u001b[0m\u001b[0;36m        Warning (14320): Synthesized away node \"core_top:ic|mf_pllbase:mp1|mf_pllbase_0002:mf_pllbase_inst|altera_pll:altera_pll_i|outclk_wire[4]\" File: /root/intelFPGA_lite/22.1std/quartus/libraries/megafunctions/altera_pll.v Line: 749\n",
            "\u001b[0m\u001b[0;32mInfo (284007): State machine \"|apf_top|core_top:ic|core_bridge_cmd:icb|tstate\" will be implemented as a safe state machine. File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 153\n",
            "\u001b[0m\u001b[0;32mInfo (284007): State machine \"|apf_top|core_top:ic|core_bridge_cmd:icb|hstate\" will be implemented as a safe state machine. File: /content/openfpga-pong/src/fpga/core/core_bridge_cmd.v Line: 127\n",
            "\u001b[0m\u001b[0;32mInfo (284007): State machine \"|apf_top|io_bridge_peripheral:ibs|rx_latch_idx\" will be implemented as a safe state machine. File: /content/openfpga-pong/src/fpga/apf/io_bridge_peripheral.v Line: 304\n",
            "\u001b[0m\u001b[0;32mInfo (284007): State machine \"|apf_top|io_bridge_peripheral:ibs|spis\" will be implemented as a safe state machine. File: /content/openfpga-pong/src/fpga/apf/io_bridge_peripheral.v Line: 106\n",
            "\u001b[0m\u001b[0;32mInfo (284007): State machine \"|apf_top|io_bridge_peripheral:ibs|state\" will be implemented as a safe state machine. File: /content/openfpga-pong/src/fpga/apf/io_bridge_peripheral.v Line: 86\n",
            "\u001b[0m\u001b[0;32mInfo (284007): State machine \"|apf_top|io_pad_controller:ipm|tr_state\" will be implemented as a safe state machine. File: /content/openfpga-pong/src/fpga/apf/io_pad_controller.v Line: 223\n",
            "\u001b[0m\u001b[0;32mInfo (284007): State machine \"|apf_top|io_pad_controller:ipm|state\" will be implemented as a safe state machine. File: /content/openfpga-pong/src/fpga/apf/io_pad_controller.v Line: 91\n",
            "\u001b[0m\u001b[0;36mWarning (12241): 15 hierarchies have connectivity warnings - see the Connectivity Checks report folder\n",
            "\u001b[0m\u001b[0;32mInfo (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using \"speed\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched\n",
            "\u001b[0m\u001b[0;36mWarning (13039): The following bidirectional pins have no drivers\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram0_dq[0]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram0_dq[1]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram0_dq[2]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram0_dq[3]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram0_dq[4]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram0_dq[5]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram0_dq[6]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram0_dq[7]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram0_dq[8]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram0_dq[9]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram0_dq[10]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram0_dq[11]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram0_dq[12]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram0_dq[13]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram0_dq[14]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram0_dq[15]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram1_dq[0]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram1_dq[1]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram1_dq[2]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram1_dq[3]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram1_dq[4]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram1_dq[5]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram1_dq[6]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram1_dq[7]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram1_dq[8]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram1_dq[9]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram1_dq[10]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram1_dq[11]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram1_dq[12]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram1_dq[13]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram1_dq[14]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"cram1_dq[15]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"dram_dq[0]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"dram_dq[1]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"dram_dq[2]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"dram_dq[3]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"dram_dq[4]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"dram_dq[5]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"dram_dq[6]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"dram_dq[7]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"dram_dq[8]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"dram_dq[9]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"dram_dq[10]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"dram_dq[11]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"dram_dq[12]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"dram_dq[13]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"dram_dq[14]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"dram_dq[15]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"sram_dq[0]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"sram_dq[1]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"sram_dq[2]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"sram_dq[3]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"sram_dq[4]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"sram_dq[5]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"sram_dq[6]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"sram_dq[7]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"sram_dq[8]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"sram_dq[9]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"sram_dq[10]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"sram_dq[11]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"sram_dq[12]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"sram_dq[13]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"sram_dq[14]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"sram_dq[15]\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;36m    Warning (13040): bidirectional pin \"aux_sda\" has no driver File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 208\n",
            "\u001b[0m\u001b[0;36mWarning (13032): The following tri-state nodes are fed by constants\n",
            "\u001b[0m\u001b[0;36m    Warning (13033): The pin \"cart_tran_bank0[4]\" is fed by VCC File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 73\n",
            "\u001b[0m\u001b[0;36m    Warning (13033): The pin \"cart_tran_bank0[5]\" is fed by VCC File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 73\n",
            "\u001b[0m\u001b[0;36m    Warning (13033): The pin \"cart_tran_bank0[6]\" is fed by VCC File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 73\n",
            "\u001b[0m\u001b[0;36m    Warning (13033): The pin \"cart_tran_bank0[7]\" is fed by VCC File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 73\n",
            "\u001b[0m\u001b[0;36m    Warning (13033): The pin \"cart_tran_pin30\" is fed by GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 77\n",
            "\u001b[0m\u001b[0;36mWarning (13009): TRI or OPNDRN buffers permanently enabled\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"cart_tran_bank0[4]~synth\" File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 73\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"cart_tran_bank0[5]~synth\" File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 73\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"cart_tran_bank0[6]~synth\" File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 73\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"cart_tran_bank0[7]~synth\" File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 73\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|tri_buf1a[0]\" File: /content/openfpga-pong/src/fpga/db/ddio_bidir_euo.tdf Line: 59\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|tri_buf1a[1]\" File: /content/openfpga-pong/src/fpga/db/ddio_bidir_euo.tdf Line: 59\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|tri_buf1a[2]\" File: /content/openfpga-pong/src/fpga/db/ddio_bidir_euo.tdf Line: 59\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|tri_buf1a[3]\" File: /content/openfpga-pong/src/fpga/db/ddio_bidir_euo.tdf Line: 59\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|tri_buf1a[4]\" File: /content/openfpga-pong/src/fpga/db/ddio_bidir_euo.tdf Line: 59\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|tri_buf1a[5]\" File: /content/openfpga-pong/src/fpga/db/ddio_bidir_euo.tdf Line: 59\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|tri_buf1a[6]\" File: /content/openfpga-pong/src/fpga/db/ddio_bidir_euo.tdf Line: 59\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|tri_buf1a[7]\" File: /content/openfpga-pong/src/fpga/db/ddio_bidir_euo.tdf Line: 59\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|tri_buf1a[8]\" File: /content/openfpga-pong/src/fpga/db/ddio_bidir_euo.tdf Line: 59\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|tri_buf1a[9]\" File: /content/openfpga-pong/src/fpga/db/ddio_bidir_euo.tdf Line: 59\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|tri_buf1a[10]\" File: /content/openfpga-pong/src/fpga/db/ddio_bidir_euo.tdf Line: 59\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"mf_ddio_bidir_12:isco|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|tri_buf1a[11]\" File: /content/openfpga-pong/src/fpga/db/ddio_bidir_euo.tdf Line: 59\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"mf_ddio_bidir_12:isclk|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|tri_buf1a[0]\" File: /content/openfpga-pong/src/fpga/db/ddio_bidir_euo.tdf Line: 59\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"mf_ddio_bidir_12:iscc|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|tri_buf1a[1]\" File: /content/openfpga-pong/src/fpga/db/ddio_bidir_euo.tdf Line: 59\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"mf_ddio_bidir_12:iscc|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|tri_buf1a[0]\" File: /content/openfpga-pong/src/fpga/db/ddio_bidir_euo.tdf Line: 59\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"mf_ddio_bidir_12:iscc|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|tri_buf1a[3]\" File: /content/openfpga-pong/src/fpga/db/ddio_bidir_euo.tdf Line: 59\n",
            "\u001b[0m\u001b[0;36m    Warning (13010): Node \"mf_ddio_bidir_12:iscc|altddio_bidir:ALTDDIO_BIDIR_component|ddio_bidir_euo:auto_generated|tri_buf1a[2]\" File: /content/openfpga-pong/src/fpga/db/ddio_bidir_euo.tdf Line: 59\n",
            "\u001b[0m\u001b[0;36mWarning (13024): Output pins are stuck at VCC or GND\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cart_tran_bank2_dir\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 58\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cart_tran_bank3_dir\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 62\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cart_tran_bank1_dir\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 66\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cart_tran_bank0_dir\" is stuck at VCC File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 74\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cart_pin30_pwroff_reset\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 83\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cart_tran_pin31_dir\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 87\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"port_ir_tx\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 92\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"port_ir_rx_disable\" is stuck at VCC File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 93\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"port_tran_si_dir\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 97\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"port_tran_so_dir\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 99\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"port_tran_sck_dir\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 101\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"port_tran_sd_dir\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 103\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram0_a[16]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 133\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram0_a[17]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 133\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram0_a[18]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 133\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram0_a[19]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 133\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram0_a[20]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 133\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram0_a[21]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 133\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram0_clk\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 136\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram0_adv_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 137\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram0_cre\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 138\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram0_ce0_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 139\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram0_ce1_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 140\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram0_oe_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 141\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram0_we_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 142\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram0_ub_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 143\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram0_lb_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 144\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram1_a[16]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 146\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram1_a[17]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 146\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram1_a[18]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 146\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram1_a[19]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 146\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram1_a[20]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 146\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram1_a[21]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 146\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram1_clk\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 149\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram1_adv_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 150\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram1_cre\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 151\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram1_ce0_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 152\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram1_ce1_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 153\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram1_oe_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 154\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram1_we_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 155\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram1_ub_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 156\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"cram1_lb_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 157\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_a[0]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 162\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_a[1]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 162\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_a[2]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 162\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_a[3]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 162\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_a[4]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 162\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_a[5]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 162\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_a[6]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 162\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_a[7]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 162\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_a[8]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 162\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_a[9]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 162\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_a[10]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 162\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_a[11]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 162\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_a[12]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 162\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_ba[0]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 163\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_ba[1]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 163\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_dqm[0]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 165\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_dqm[1]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 165\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_clk\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 166\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_cke\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 167\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_ras_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 168\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_cas_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 169\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dram_we_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 170\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_a[0]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 175\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_a[1]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 175\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_a[2]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 175\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_a[3]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 175\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_a[4]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 175\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_a[5]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 175\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_a[6]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 175\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_a[7]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 175\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_a[8]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 175\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_a[9]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 175\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_a[10]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 175\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_a[11]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 175\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_a[12]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 175\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_a[13]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 175\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_a[14]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 175\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_a[15]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 175\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_a[16]\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 175\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_oe_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 177\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_we_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 178\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_ub_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 179\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"sram_lb_n\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 180\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"dbg_tx\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 190\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"user1\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 196\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"vpll_feed\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 203\n",
            "\u001b[0m\u001b[0;36m    Warning (13410): Pin \"aux_scl\" is stuck at GND File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 211\n",
            "\u001b[0m\u001b[0;32mInfo (286030): Timing-Driven Synthesis is running\n",
            "\u001b[0m\u001b[0;32mInfo (17049): 35 registers lost all their fanouts during netlist optimizations.\n",
            "\u001b[0m\u001b[0;32mInfo (17016): Found the following redundant logic cells in design\n",
            "\u001b[0m\u001b[0;32m    Info (17048): Logic cell \"core_top:ic|audgen_sclk\" File: /content/openfpga-pong/src/fpga/core/core_top.v Line: 551\n",
            "\u001b[0m\u001b[0;32mInfo (144001): Generated suppressed messages file /content/openfpga-pong/src/fpga/output_files/ap_core.map.smsg\n",
            "\u001b[0m\u001b[0;32mInfo (16010): Generating hard_block partition \"hard_block:auto_generated_inst\"\n",
            "\u001b[0m\u001b[0;32m    Info (16011): Adding 73 node(s), including 17 DDIO, 3 PLL, 0 transceiver and 0 LCELL\n",
            "\u001b[0m\u001b[0;36mWarning: RST port on the PLL is not properly connected on instance core_top:ic|mf_pllbase:mp1|mf_pllbase_0002:mf_pllbase_inst|altera_pll:altera_pll_i|general[0].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock. File: /root/intelFPGA_lite/22.1std/quartus/libraries/megafunctions/altera_pll.v Line: 749\n",
            "\u001b[0m\u001b[0;32m    Info: Must be connected\n",
            "\u001b[0m\u001b[0;36mWarning: RST port on the PLL is not properly connected on instance core_top:ic|mf_pllbase:mp1|mf_pllbase_0002:mf_pllbase_inst|altera_pll:altera_pll_i|general[1].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock. File: /root/intelFPGA_lite/22.1std/quartus/libraries/megafunctions/altera_pll.v Line: 749\n",
            "\u001b[0m\u001b[0;32m    Info: Must be connected\n",
            "\u001b[0m\u001b[0;36mWarning: RST port on the PLL is not properly connected on instance core_top:ic|mf_pllbase:mp1|mf_pllbase_0002:mf_pllbase_inst|altera_pll:altera_pll_i|general[2].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock. File: /root/intelFPGA_lite/22.1std/quartus/libraries/megafunctions/altera_pll.v Line: 749\n",
            "\u001b[0m\u001b[0;32m    Info: Must be connected\n",
            "\u001b[0m\u001b[0;36mWarning (21074): Design contains 8 input pin(s) that do not drive logic\n",
            "\u001b[0m\u001b[0;36m    Warning (15610): No output dependent on input pin \"clk_74b\" File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 49\n",
            "\u001b[0m\u001b[0;36m    Warning (15610): No output dependent on input pin \"port_ir_rx\" File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 91\n",
            "\u001b[0m\u001b[0;36m    Warning (15610): No output dependent on input pin \"scal_audadc\" File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 116\n",
            "\u001b[0m\u001b[0;36m    Warning (15610): No output dependent on input pin \"cram0_wait\" File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 135\n",
            "\u001b[0m\u001b[0;36m    Warning (15610): No output dependent on input pin \"cram1_wait\" File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 148\n",
            "\u001b[0m\u001b[0;36m    Warning (15610): No output dependent on input pin \"vblank\" File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 185\n",
            "\u001b[0m\u001b[0;36m    Warning (15610): No output dependent on input pin \"dbg_rx\" File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 191\n",
            "\u001b[0m\u001b[0;36m    Warning (15610): No output dependent on input pin \"user2\" File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 197\n",
            "\u001b[0m\u001b[0;32mInfo (21057): Implemented 2035 device resources after synthesis - the final resource count might be different\n",
            "\u001b[0m\u001b[0;32m    Info (21058): Implemented 10 input pins\n",
            "\u001b[0m\u001b[0;32m    Info (21059): Implemented 93 output pins\n",
            "\u001b[0m\u001b[0;32m    Info (21060): Implemented 121 bidirectional pins\n",
            "\u001b[0m\u001b[0;32m    Info (21061): Implemented 1759 logic cells\n",
            "\u001b[0m\u001b[0;32m    Info (21064): Implemented 32 RAM segments\n",
            "\u001b[0m\u001b[0;32m    Info (21065): Implemented 3 PLLs\n",
            "\u001b[0m\u001b[0;32mInfo: Quartus Prime Analysis & Synthesis was successful. 0 errors, 280 warnings\n",
            "\u001b[0m\u001b[0;32m    Info: Peak virtual memory: 611 megabytes\n",
            "\u001b[0m\u001b[0;32m    Info: Processing ended: Tue Jan 10 03:53:10 2023\n",
            "\u001b[0m\u001b[0;32m    Info: Elapsed time: 00:00:24\n",
            "\u001b[0m\u001b[0;32m    Info: Total CPU time (on all processors): 00:00:30\n",
            "\u001b[0m"
          ]
        }
      ]
    },
    {
      "cell_type": "code",
      "source": [
        "! quartus_fit --read_settings_files=off --write_settings_files=off ap_core -c ap_core"
      ],
      "metadata": {
        "colab": {
          "base_uri": "https://localhost:8080/"
        },
        "id": "goR-iU4nex1H",
        "outputId": "929e0191-0c58-43fc-8b8f-32e343b28bc6"
      },
      "execution_count": 11,
      "outputs": [
        {
          "output_type": "stream",
          "name": "stdout",
          "text": [
            "quartus_fit: /root/intelFPGA_lite/22.1std/quartus/linux64/liblzma.so.5: no version information available (required by /usr/lib/x86_64-linux-gnu/libunwind.so.8)\n",
            "\u001b[0;32mInfo (125069): Default assignment values were changed in the current version of the Quartus Prime software -- changes to default assignments values are contained in file /root/intelFPGA_lite/22.1std/quartus/linux64/assignment_defaults.qdf\n",
            "\u001b[0m\u001b[0;32mInfo: *******************************************************************\n",
            "\u001b[0m\u001b[0;32mInfo: Running Quartus Prime Fitter\n",
            "\u001b[0m\u001b[0;32m    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition\n",
            "\u001b[0m\u001b[0;32m    Info: Copyright (C) 2022  Intel Corporation. All rights reserved.\n",
            "\u001b[0m\u001b[0;32m    Info: Your use of Intel Corporation's design tools, logic functions \n",
            "\u001b[0m\u001b[0;32m    Info: and other software and tools, and any partner logic \n",
            "\u001b[0m\u001b[0;32m    Info: functions, and any output files from any of the foregoing \n",
            "\u001b[0m\u001b[0;32m    Info: (including device programming or simulation files), and any \n",
            "\u001b[0m\u001b[0;32m    Info: associated documentation or information are expressly subject \n",
            "\u001b[0m\u001b[0;32m    Info: to the terms and conditions of the Intel Program License \n",
            "\u001b[0m\u001b[0;32m    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,\n",
            "\u001b[0m\u001b[0;32m    Info: the Intel FPGA IP License Agreement, or other applicable license\n",
            "\u001b[0m\u001b[0;32m    Info: agreement, including, without limitation, that your use is for\n",
            "\u001b[0m\u001b[0;32m    Info: the sole purpose of programming logic devices manufactured by\n",
            "\u001b[0m\u001b[0;32m    Info: Intel and sold by Intel or its authorized distributors.  Please\n",
            "\u001b[0m\u001b[0;32m    Info: refer to the applicable agreement for further details, at\n",
            "\u001b[0m\u001b[0;32m    Info: https://fpgasoftware.intel.com/eula.\n",
            "\u001b[0m\u001b[0;32m    Info: Processing started: Tue Jan 10 03:53:11 2023\n",
            "\u001b[0m\u001b[0;32mInfo: Command: quartus_fit --read_settings_files=off --write_settings_files=off ap_core -c ap_core\n",
            "\u001b[0m\u001b[0;32mInfo: qfit2_default_script.tcl version: #1\n",
            "\u001b[0m\u001b[0;32mInfo: Project  = ap_core\n",
            "\u001b[0m\u001b[0;32mInfo: Revision = ap_core\n",
            "\u001b[0m\u001b[0;32mInfo (16303): High Performance Effort optimization mode selected -- timing performance will be prioritized at the potential cost of increased compilation time\n",
            "\u001b[0m\u001b[0;32m    Info (16304): Mode behavior is affected by advanced setting Fitter Effort (default for this mode is Standard Fit)\n",
            "\u001b[0m\u001b[0;36mWarning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.\n",
            "\u001b[0m\u001b[0;32mInfo (20029): Only one processor detected - disabling parallel compilation\n",
            "\u001b[0m\u001b[0;32mInfo (119006): Selected device 5CEBA4F23C8 for design \"ap_core\"\n",
            "\u001b[0m\u001b[0;32mInfo (21077): Low junction temperature is 0 degrees C\n",
            "\u001b[0m\u001b[0;32mInfo (21077): High junction temperature is 85 degrees C\n",
            "\u001b[0m\u001b[0;36mWarning: RST port on the PLL is not properly connected on instance core_top:ic|mf_pllbase:mp1|mf_pllbase_0002:mf_pllbase_inst|altera_pll:altera_pll_i|general[0].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock. File: /root/intelFPGA_lite/22.1std/quartus/libraries/megafunctions/altera_pll.v Line: 749\n",
            "\u001b[0m\u001b[0;32m    Info: Must be connected\n",
            "\u001b[0m\u001b[0;32mInfo (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time\n",
            "\u001b[0m\u001b[0;36mWarning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.\n",
            "\u001b[0m\u001b[0;36mWarning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details\n",
            "\u001b[0m\u001b[0;32mInfo (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.\n",
            "\u001b[0m\u001b[0;32mInfo (184020): Starting Fitter periphery placement operations\n",
            "\u001b[0m\u001b[0;36mWarning (177007): PLL(s) placed in location FRACTIONALPLL_X54_Y1_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks\n",
            "\u001b[0m\u001b[0;32m    Info (177008): PLL core_top:ic|mf_pllbase:mp1|mf_pllbase_0002:mf_pllbase_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL\n",
            "\u001b[0m\u001b[0;32mInfo (11178): Promoted 3 clocks (3 global)\n",
            "\u001b[0m\u001b[0;32m    Info (11162): core_top:ic|mf_pllbase:mp1|mf_pllbase_0002:mf_pllbase_inst|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0 with 220 fanout uses global clock CLKCTRL_G5\n",
            "\u001b[0m\u001b[0;32m    Info (11162): core_top:ic|mf_pllbase:mp1|mf_pllbase_0002:mf_pllbase_inst|altera_pll:altera_pll_i|outclk_wire[1]~CLKENA0 with 3 fanout uses global clock CLKCTRL_G8\n",
            "\u001b[0m\u001b[0;32m    Info (11162): core_top:ic|mf_pllbase:mp1|mf_pllbase_0002:mf_pllbase_inst|altera_pll:altera_pll_i|outclk_wire[2]~CLKENA0 with 224 fanout uses global clock CLKCTRL_G10\n",
            "\u001b[0m\u001b[0;32mInfo (11191): Automatically promoted 2 clocks (2 global)\n",
            "\u001b[0m\u001b[0;32m    Info (11162): clk_74a~inputCLKENA0 with 670 fanout uses global clock CLKCTRL_G6\n",
            "\u001b[0m\u001b[0;32m    Info (11162): bridge_spiclk~inputCLKENA0 with 19 fanout uses global clock CLKCTRL_G11\n",
            "\u001b[0m\u001b[0;32m        Info (12525): This signal is driven by core routing -- it may be moved during placement to reduce routing delays\n",
            "\u001b[0m\u001b[0;36mWarning (16406): 1 global input pin(s) will use non-dedicated clock routing\n",
            "\u001b[0m\u001b[0;36m    Warning (16407): Source REFCLK I/O is not placed onto a dedicated REFCLK input pin for global clock driver bridge_spiclk~inputCLKENA0, placed at CLKCTRL_G11\n",
            "\u001b[0m\u001b[0;32m        Info (179012): Refclk input I/O pad bridge_spiclk is placed onto PIN_T17\n",
            "\u001b[0m\u001b[0;32mInfo (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00\n",
            "\u001b[0m\u001b[0;36mWarning (335093): The Timing Analyzer is analyzing 32 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report.\n",
            "\u001b[0m\u001b[0;32mInfo (332104): Reading SDC File: 'apf/apf_constraints.sdc'\n",
            "\u001b[0m\u001b[0;32mInfo (332110): Deriving PLL clocks\n",
            "\u001b[0m\u001b[0;32m    Info (332110): create_generated_clock -source {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin} -divide_by 128 -multiply_by 1037 -duty_cycle 50.00 -name {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}\n",
            "\u001b[0m\u001b[0;32m    Info (332110): create_generated_clock -source {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 84 -duty_cycle 50.00 -name {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}\n",
            "\u001b[0m\u001b[0;32m    Info (332110): create_generated_clock -source {ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 84 -phase 90.00 -duty_cycle 50.00 -name {ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} {ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}\n",
            "\u001b[0m\u001b[0;32m    Info (332110): create_generated_clock -source {ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 21 -duty_cycle 50.00 -name {ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk} {ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}\n",
            "\u001b[0m\u001b[0;32mInfo (332104): Reading SDC File: 'core/core_constraints.sdc'\n",
            "\u001b[0m\u001b[0;36mWarning (332174): Ignored filter at core_constraints.sdc(7): ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk could not be matched with a clock File: /content/openfpga-pong/src/fpga/core/core_constraints.sdc Line: 7\n",
            "\u001b[0m\u001b[0;36mWarning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value  ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk  could not match any element of the following types: ( clk ) File: /content/openfpga-pong/src/fpga/core/core_constraints.sdc Line: 7\n",
            "\u001b[0m\u001b[0;32m    Info (332050): set_clock_groups -asynchronous \\\n",
            " -group { bridge_spiclk } \\\n",
            " -group { clk_74a } \\\n",
            " -group { clk_74b } \\\n",
            " -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } \\\n",
            " -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \\\n",
            " -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk } \\\n",
            " -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk }  File: /content/openfpga-pong/src/fpga/core/core_constraints.sdc Line: 7\n",
            "\u001b[0m\u001b[0;32mInfo (332104): Reading SDC File: 'core/core_constraints.sdc'\n",
            "\u001b[0m\u001b[0;36mWarning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value  ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk  could not match any element of the following types: ( clk ) File: /content/openfpga-pong/src/fpga/core/core_constraints.sdc Line: 7\n",
            "\u001b[0m\u001b[0;32m    Info (332050): set_clock_groups -asynchronous \\\n",
            " -group { bridge_spiclk } \\\n",
            " -group { clk_74a } \\\n",
            " -group { clk_74b } \\\n",
            " -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } \\\n",
            " -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \\\n",
            " -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk } \\\n",
            " -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk }  File: /content/openfpga-pong/src/fpga/core/core_constraints.sdc Line: 7\n",
            "\u001b[0m\u001b[0;36mWarning (332060): Node: io_bridge_peripheral:ibs|pmp_addr[24] was determined to be a clock but was found without an associated clock assignment.\n",
            "\u001b[0m\u001b[0;32m    Info (13166): Latch core_top:ic|bridge_rd_data[30] is being clocked by io_bridge_peripheral:ibs|pmp_addr[24]\n",
            "\u001b[0m\u001b[0;36mWarning (332060): Node: core_top:ic|aud_mclk_divider[1] was determined to be a clock but was found without an associated clock assignment.\n",
            "\u001b[0m\u001b[0;32m    Info (13166): Register core_top:ic|audgen_dac is being clocked by core_top:ic|aud_mclk_divider[1]\n",
            "\u001b[0m\u001b[0;36mWarning (332060): Node: core_top:ic|audgen_mclk was determined to be a clock but was found without an associated clock assignment.\n",
            "\u001b[0m\u001b[0;32m    Info (13166): Register core_top:ic|aud_mclk_divider[1] is being clocked by core_top:ic|audgen_mclk\n",
            "\u001b[0m\u001b[0;32mInfo (332097): The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network.\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT  from: clkin[0]  to: clkout\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk\n",
            "\u001b[0m\u001b[0;32mInfo (332143): No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"\n",
            "\u001b[0m\u001b[0;32mInfo (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.\n",
            "\u001b[0m\u001b[0;32mInfo (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements\n",
            "\u001b[0m\u001b[0;32mInfo (332111): Found 7 clocks\n",
            "\u001b[0m\u001b[0;32m    Info (332111):   Period   Clock Name\n",
            "\u001b[0m\u001b[0;32m    Info (332111): ======== ============\n",
            "\u001b[0m\u001b[0;32m    Info (332111):   13.468 bridge_spiclk\n",
            "\u001b[0m\u001b[0;32m    Info (332111):   13.468      clk_74a\n",
            "\u001b[0m\u001b[0;32m    Info (332111):   13.468      clk_74b\n",
            "\u001b[0m\u001b[0;32m    Info (332111):    1.662 ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]\n",
            "\u001b[0m\u001b[0;32m    Info (332111):  139.641 ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk\n",
            "\u001b[0m\u001b[0;32m    Info (332111):  139.641 ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk\n",
            "\u001b[0m\u001b[0;32m    Info (332111):   34.910 ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk\n",
            "\u001b[0m\u001b[0;32mInfo (176233): Starting register packing\n",
            "\u001b[0m\u001b[0;32m\u001b[0m\u001b[0;32m\u001b[0m\u001b[0;32m\u001b[0m\u001b[0;32m\u001b[0m\u001b[0;32m\u001b[0m\u001b[0;32m\u001b[0m\u001b[0;32mInfo (176235): Finished register packing\n",
            "\u001b[0m\u001b[0;32m    Extra Info (176219): No registers were packed into other blocks\n",
            "\u001b[0m\u001b[0;32mInfo (128000): Starting physical synthesis optimizations for speed\n",
            "\u001b[0m\u001b[0;32mInfo (128002): Starting physical synthesis algorithm register retiming\n",
            "\u001b[0m\u001b[0;32mInfo (128003): Physical synthesis algorithm register retiming complete: estimated slack improvement of 1656 ps\n",
            "\u001b[0m\u001b[0;32mInfo (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division\n",
            "\u001b[0m\u001b[0;32mInfo (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps\n",
            "\u001b[0m\u001b[0;32mInfo (128002): Starting physical synthesis algorithm register retiming\n",
            "\u001b[0m\u001b[0;32mInfo (128003): Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps\n",
            "\u001b[0m\u001b[0;32mInfo (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division\n",
            "\u001b[0m\u001b[0;32mInfo (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps\n",
            "\u001b[0m\u001b[0;32mInfo (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:03\n",
            "\u001b[0m\u001b[0;32mInfo (176233): Starting register packing\n",
            "\u001b[0m\u001b[0;32m\u001b[0m\u001b[0;32m\u001b[0m\u001b[0;32m\u001b[0m\u001b[0;32m\u001b[0m\u001b[0;32mInfo (176235): Finished register packing\n",
            "\u001b[0m\u001b[0;32m    Extra Info (176219): No registers were packed into other blocks\n",
            "\u001b[0m\u001b[0;32mInfo (11798): Fitter preparation operations ending: elapsed time is 00:00:14\n",
            "\u001b[0m\u001b[0;32mInfo (170189): Fitter placement preparation operations beginning\n",
            "\u001b[0m\u001b[0;32mInfo (14951): The Fitter is using Advanced Physical Optimization.\n",
            "\u001b[0m\u001b[0;32mInfo (170190): Fitter placement preparation operations ending: elapsed time is 00:00:29\n",
            "\u001b[0m\u001b[0;32mInfo (170191): Fitter placement operations beginning\n",
            "\u001b[0m\u001b[0;32mInfo (170137): Fitter placement was successful\n",
            "\u001b[0m\u001b[0;32mInfo (170192): Fitter placement operations ending: elapsed time is 00:00:01\n",
            "\u001b[0m\u001b[0;32mInfo (170193): Fitter routing operations beginning\n",
            "\u001b[0m\u001b[0;32mInfo (170195): Router estimated average interconnect usage is 0% of the available device resources\n",
            "\u001b[0m\u001b[0;32m    Info (170196): Router estimated peak interconnect usage is 7% of the available device resources in the region that extends from location X44_Y11 to location X54_Y22\n",
            "\u001b[0m\u001b[0;32mInfo (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.\n",
            "\u001b[0m\u001b[0;32m    Info (170201): Optimizations that may affect the design's routability were skipped\n",
            "\u001b[0m\u001b[0;32m    Info (170200): Optimizations that may affect the design's timing were skipped\n",
            "\u001b[0m\u001b[0;32mInfo (170194): Fitter routing operations ending: elapsed time is 00:00:06\n",
            "\u001b[0m\u001b[0;32mInfo (11888): Total time spent on timing analysis during the Fitter is 3.26 seconds.\n",
            "\u001b[0m\u001b[0;32mInfo (334003): Started post-fitting delay annotation\n",
            "\u001b[0m\u001b[0;32mInfo (334004): Delay annotation completed successfully\n",
            "\u001b[0m\u001b[0;32mInfo (334003): Started post-fitting delay annotation\n",
            "\u001b[0m\u001b[0;32mInfo (334004): Delay annotation completed successfully\n",
            "\u001b[0m\u001b[0;32mInfo (11801): Fitter post-fit operations ending: elapsed time is 00:00:15\n",
            "\u001b[0m\u001b[0;36mWarning (169064): Following 117 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank2[0] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 57\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank2[1] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 57\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank2[2] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 57\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank2[3] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 57\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank2[4] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 57\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank2[5] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 57\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank2[6] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 57\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank2[7] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 57\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank3[0] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 61\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank3[1] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 61\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank3[2] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 61\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank3[3] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 61\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank3[4] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 61\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank3[5] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 61\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank3[6] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 61\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank3[7] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 61\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank1[0] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 65\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank1[1] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 65\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank1[2] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 65\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank1[3] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 65\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank1[4] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 65\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank1[5] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 65\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank1[6] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 65\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank1[7] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 65\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank0[4] has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 73\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank0[5] has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 73\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank0[6] has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 73\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_bank0[7] has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 73\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_pin30 has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 77\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cart_tran_pin31 has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 86\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin port_tran_si has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 96\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin port_tran_so has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 98\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin port_tran_sck has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 100\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin port_tran_sd has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 102\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin scal_vid[0] has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 108\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin scal_vid[1] has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 108\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin scal_vid[2] has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 108\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin scal_vid[3] has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 108\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin scal_vid[4] has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 108\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin scal_vid[5] has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 108\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin scal_vid[6] has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 108\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin scal_vid[7] has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 108\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin scal_vid[8] has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 108\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin scal_vid[9] has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 108\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin scal_vid[10] has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 108\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin scal_vid[11] has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 108\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin scal_clk has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 109\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin scal_de has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 110\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin scal_skip has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 111\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin scal_vs has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 112\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin scal_hs has a permanently enabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 113\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram0_dq[0] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram0_dq[1] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram0_dq[2] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram0_dq[3] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram0_dq[4] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram0_dq[5] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram0_dq[6] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram0_dq[7] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram0_dq[8] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram0_dq[9] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram0_dq[10] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram0_dq[11] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram0_dq[12] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram0_dq[13] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram0_dq[14] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram0_dq[15] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 134\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram1_dq[0] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram1_dq[1] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram1_dq[2] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram1_dq[3] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram1_dq[4] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram1_dq[5] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram1_dq[6] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram1_dq[7] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram1_dq[8] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram1_dq[9] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram1_dq[10] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram1_dq[11] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram1_dq[12] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram1_dq[13] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram1_dq[14] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin cram1_dq[15] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 147\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin dram_dq[0] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin dram_dq[1] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin dram_dq[2] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin dram_dq[3] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin dram_dq[4] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin dram_dq[5] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin dram_dq[6] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin dram_dq[7] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin dram_dq[8] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin dram_dq[9] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin dram_dq[10] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin dram_dq[11] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin dram_dq[12] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin dram_dq[13] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin dram_dq[14] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin dram_dq[15] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 164\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin sram_dq[0] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin sram_dq[1] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin sram_dq[2] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin sram_dq[3] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin sram_dq[4] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin sram_dq[5] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin sram_dq[6] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin sram_dq[7] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin sram_dq[8] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin sram_dq[9] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin sram_dq[10] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin sram_dq[11] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin sram_dq[12] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin sram_dq[13] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin sram_dq[14] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin sram_dq[15] has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 176\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin bist has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 202\n",
            "\u001b[0m\u001b[0;32m    Info (169065): Pin aux_sda has a permanently disabled output enable File: /content/openfpga-pong/src/fpga/apf/apf_top.v Line: 208\n",
            "\u001b[0m\u001b[0;32mInfo (144001): Generated suppressed messages file /content/openfpga-pong/src/fpga/output_files/ap_core.fit.smsg\n",
            "\u001b[0m\u001b[0;32mInfo: Quartus Prime Fitter was successful. 0 errors, 15 warnings\n",
            "\u001b[0m\u001b[0;32m    Info: Peak virtual memory: 1658 megabytes\n",
            "\u001b[0m\u001b[0;32m    Info: Processing ended: Tue Jan 10 03:55:09 2023\n",
            "\u001b[0m\u001b[0;32m    Info: Elapsed time: 00:01:58\n",
            "\u001b[0m\u001b[0;32m    Info: Total CPU time (on all processors): 00:02:20\n",
            "\u001b[0m"
          ]
        }
      ]
    },
    {
      "cell_type": "code",
      "source": [
        "! quartus_asm --read_settings_files=off --write_settings_files=off ap_core -c ap_core"
      ],
      "metadata": {
        "colab": {
          "base_uri": "https://localhost:8080/"
        },
        "id": "sHrAeBtqe4sl",
        "outputId": "35a21d8d-68c9-4583-b0ad-f1d381f6646b"
      },
      "execution_count": 12,
      "outputs": [
        {
          "output_type": "stream",
          "name": "stdout",
          "text": [
            "quartus_asm: /root/intelFPGA_lite/22.1std/quartus/linux64/liblzma.so.5: no version information available (required by /usr/lib/x86_64-linux-gnu/libunwind.so.8)\n",
            "\u001b[0;32mInfo: *******************************************************************\n",
            "\u001b[0m\u001b[0;32mInfo: Running Quartus Prime Assembler\n",
            "\u001b[0m\u001b[0;32m    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition\n",
            "\u001b[0m\u001b[0;32m    Info: Copyright (C) 2022  Intel Corporation. All rights reserved.\n",
            "\u001b[0m\u001b[0;32m    Info: Your use of Intel Corporation's design tools, logic functions \n",
            "\u001b[0m\u001b[0;32m    Info: and other software and tools, and any partner logic \n",
            "\u001b[0m\u001b[0;32m    Info: functions, and any output files from any of the foregoing \n",
            "\u001b[0m\u001b[0;32m    Info: (including device programming or simulation files), and any \n",
            "\u001b[0m\u001b[0;32m    Info: associated documentation or information are expressly subject \n",
            "\u001b[0m\u001b[0;32m    Info: to the terms and conditions of the Intel Program License \n",
            "\u001b[0m\u001b[0;32m    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,\n",
            "\u001b[0m\u001b[0;32m    Info: the Intel FPGA IP License Agreement, or other applicable license\n",
            "\u001b[0m\u001b[0;32m    Info: agreement, including, without limitation, that your use is for\n",
            "\u001b[0m\u001b[0;32m    Info: the sole purpose of programming logic devices manufactured by\n",
            "\u001b[0m\u001b[0;32m    Info: Intel and sold by Intel or its authorized distributors.  Please\n",
            "\u001b[0m\u001b[0;32m    Info: refer to the applicable agreement for further details, at\n",
            "\u001b[0m\u001b[0;32m    Info: https://fpgasoftware.intel.com/eula.\n",
            "\u001b[0m\u001b[0;32m    Info: Processing started: Tue Jan 10 03:55:10 2023\n",
            "\u001b[0m\u001b[0;32mInfo: Command: quartus_asm --read_settings_files=off --write_settings_files=off ap_core -c ap_core\n",
            "\u001b[0m\u001b[0;32mInfo (125069): Default assignment values were changed in the current version of the Quartus Prime software -- changes to default assignments values are contained in file /root/intelFPGA_lite/22.1std/quartus/linux64/assignment_defaults.qdf\n",
            "\u001b[0m\u001b[0;36mWarning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.\n",
            "\u001b[0m\u001b[0;32mInfo (115030): Assembler is generating device programming files\n",
            "\u001b[0m\u001b[0;36mWarning (12914): The file, /content/openfpga-pong/src/fpga/db/stp1_auto_stripped.stp, is not embedded into sof file as expected.  Some tools, such as System Console, may not function fully.\n",
            "\u001b[0m\u001b[0;32mInfo: Quartus Prime Assembler was successful. 0 errors, 2 warnings\n",
            "\u001b[0m\u001b[0;32m    Info: Peak virtual memory: 717 megabytes\n",
            "\u001b[0m\u001b[0;32m    Info: Processing ended: Tue Jan 10 03:55:15 2023\n",
            "\u001b[0m\u001b[0;32m    Info: Elapsed time: 00:00:05\n",
            "\u001b[0m\u001b[0;32m    Info: Total CPU time (on all processors): 00:00:05\n",
            "\u001b[0m"
          ]
        }
      ]
    },
    {
      "cell_type": "code",
      "source": [
        "! quartus_sta ap_core -c ap_core"
      ],
      "metadata": {
        "colab": {
          "base_uri": "https://localhost:8080/"
        },
        "id": "mc8iCM3oe6Ui",
        "outputId": "a0ed52af-a1cc-4c32-bb98-4c3b98907207"
      },
      "execution_count": 13,
      "outputs": [
        {
          "output_type": "stream",
          "name": "stdout",
          "text": [
            "quartus_sta: /root/intelFPGA_lite/22.1std/quartus/linux64/liblzma.so.5: no version information available (required by /usr/lib/x86_64-linux-gnu/libunwind.so.8)\n",
            "\u001b[0;32mInfo (125069): Default assignment values were changed in the current version of the Quartus Prime software -- changes to default assignments values are contained in file /root/intelFPGA_lite/22.1std/quartus/linux64/assignment_defaults.qdf\n",
            "\u001b[0m\u001b[0;32mInfo: *******************************************************************\n",
            "\u001b[0m\u001b[0;32mInfo: Running Quartus Prime Timing Analyzer\n",
            "\u001b[0m\u001b[0;32m    Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition\n",
            "\u001b[0m\u001b[0;32m    Info: Copyright (C) 2022  Intel Corporation. All rights reserved.\n",
            "\u001b[0m\u001b[0;32m    Info: Your use of Intel Corporation's design tools, logic functions \n",
            "\u001b[0m\u001b[0;32m    Info: and other software and tools, and any partner logic \n",
            "\u001b[0m\u001b[0;32m    Info: functions, and any output files from any of the foregoing \n",
            "\u001b[0m\u001b[0;32m    Info: (including device programming or simulation files), and any \n",
            "\u001b[0m\u001b[0;32m    Info: associated documentation or information are expressly subject \n",
            "\u001b[0m\u001b[0;32m    Info: to the terms and conditions of the Intel Program License \n",
            "\u001b[0m\u001b[0;32m    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,\n",
            "\u001b[0m\u001b[0;32m    Info: the Intel FPGA IP License Agreement, or other applicable license\n",
            "\u001b[0m\u001b[0;32m    Info: agreement, including, without limitation, that your use is for\n",
            "\u001b[0m\u001b[0;32m    Info: the sole purpose of programming logic devices manufactured by\n",
            "\u001b[0m\u001b[0;32m    Info: Intel and sold by Intel or its authorized distributors.  Please\n",
            "\u001b[0m\u001b[0;32m    Info: refer to the applicable agreement for further details, at\n",
            "\u001b[0m\u001b[0;32m    Info: https://fpgasoftware.intel.com/eula.\n",
            "\u001b[0m\u001b[0;32m    Info: Processing started: Tue Jan 10 03:55:16 2023\n",
            "\u001b[0m\u001b[0;32mInfo: Command: quartus_sta ap_core -c ap_core\n",
            "\u001b[0m\u001b[0;32mInfo: qsta_default_script.tcl version: #1\n",
            "\u001b[0m\u001b[0;32mInfo (293031): Detected changes in Quartus Prime Settings File (.qsf).\n",
            "\u001b[0m\u001b[0;32m    Info (293028): Assignment ROUTER_TIMING_OPTIMIZATION_LEVEL changed value from MAXIMUM to NORMAL.\n",
            "\u001b[0m\u001b[0;32m    Info (293028): Assignment PLACEMENT_EFFORT_MULTIPLIER changed value from 4.0 to 1.0.\n",
            "\u001b[0m\u001b[0;36mWarning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.\n",
            "\u001b[0m\u001b[0;32mInfo (20029): Only one processor detected - disabling parallel compilation\n",
            "\u001b[0m\u001b[0;32mInfo (21077): Low junction temperature is 0 degrees C\n",
            "\u001b[0m\u001b[0;32mInfo (21077): High junction temperature is 85 degrees C\n",
            "\u001b[0m\u001b[0;36mWarning (335093): The Timing Analyzer is analyzing 32 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report.\n",
            "\u001b[0m\u001b[0;32mInfo (332104): Reading SDC File: 'apf/apf_constraints.sdc'\n",
            "\u001b[0m\u001b[0;32mInfo (332110): Deriving PLL clocks\n",
            "\u001b[0m\u001b[0;32m    Info (332110): create_generated_clock -source {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin} -divide_by 128 -multiply_by 1037 -duty_cycle 50.00 -name {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}\n",
            "\u001b[0m\u001b[0;32m    Info (332110): create_generated_clock -source {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 84 -duty_cycle 50.00 -name {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} {ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}\n",
            "\u001b[0m\u001b[0;32m    Info (332110): create_generated_clock -source {ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 84 -phase 90.00 -duty_cycle 50.00 -name {ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} {ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}\n",
            "\u001b[0m\u001b[0;32m    Info (332110): create_generated_clock -source {ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 21 -duty_cycle 50.00 -name {ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk} {ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}\n",
            "\u001b[0m\u001b[0;32mInfo (332104): Reading SDC File: 'core/core_constraints.sdc'\n",
            "\u001b[0m\u001b[0;36mWarning (332174): Ignored filter at core_constraints.sdc(7): ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk could not be matched with a clock File: /content/openfpga-pong/src/fpga/core/core_constraints.sdc Line: 7\n",
            "\u001b[0m\u001b[0;36mWarning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value  ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk  could not match any element of the following types: ( clk ) File: /content/openfpga-pong/src/fpga/core/core_constraints.sdc Line: 7\n",
            "\u001b[0m\u001b[0;32m    Info (332050): set_clock_groups -asynchronous \\\n",
            " -group { bridge_spiclk } \\\n",
            " -group { clk_74a } \\\n",
            " -group { clk_74b } \\\n",
            " -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } \\\n",
            " -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \\\n",
            " -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk } \\\n",
            " -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk }  File: /content/openfpga-pong/src/fpga/core/core_constraints.sdc Line: 7\n",
            "\u001b[0m\u001b[0;32mInfo (332104): Reading SDC File: 'core/core_constraints.sdc'\n",
            "\u001b[0m\u001b[0;36mWarning (332054): Assignment set_clock_groups is accepted but has some problems at core_constraints.sdc(7): Argument -group with value  ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk  could not match any element of the following types: ( clk ) File: /content/openfpga-pong/src/fpga/core/core_constraints.sdc Line: 7\n",
            "\u001b[0m\u001b[0;32m    Info (332050): set_clock_groups -asynchronous \\\n",
            " -group { bridge_spiclk } \\\n",
            " -group { clk_74a } \\\n",
            " -group { clk_74b } \\\n",
            " -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } \\\n",
            " -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \\\n",
            " -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk } \\\n",
            " -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk }  File: /content/openfpga-pong/src/fpga/core/core_constraints.sdc Line: 7\n",
            "\u001b[0m\u001b[0;36mWarning (332060): Node: io_bridge_peripheral:ibs|pmp_addr[24] was determined to be a clock but was found without an associated clock assignment.\n",
            "\u001b[0m\u001b[0;32m    Info (13166): Latch core_top:ic|bridge_rd_data[30] is being clocked by io_bridge_peripheral:ibs|pmp_addr[24]\n",
            "\u001b[0m\u001b[0;36mWarning (332060): Node: core_top:ic|aud_mclk_divider[1] was determined to be a clock but was found without an associated clock assignment.\n",
            "\u001b[0m\u001b[0;32m    Info (13166): Register core_top:ic|audgen_dac is being clocked by core_top:ic|aud_mclk_divider[1]\n",
            "\u001b[0m\u001b[0;36mWarning (332060): Node: core_top:ic|audgen_mclk was determined to be a clock but was found without an associated clock assignment.\n",
            "\u001b[0m\u001b[0;32m    Info (13166): Register core_top:ic|aud_mclk_divider[1] is being clocked by core_top:ic|audgen_mclk\n",
            "\u001b[0m\u001b[0;32mInfo (332097): The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network.\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT  from: clkin[0]  to: clkout\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk\n",
            "\u001b[0m\u001b[0;32mInfo (332143): No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"\n",
            "\u001b[0m\u001b[0;32mInfo (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.\n",
            "\u001b[0m\u001b[0;32mInfo: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON\n",
            "\u001b[0m\u001b[0;32mInfo: Analyzing Slow 1100mV 85C Model\n",
            "\u001b[0m\u001b[0;32mInfo (332146): Worst-case setup slack is 5.065\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     Slack       End Point TNS Clock \n",
            "\u001b[0m\u001b[0;32m    Info (332119): ========= =================== =====================\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     5.065               0.000 clk_74a \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    10.420               0.000 bridge_spiclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    10.512               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    52.240               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32mInfo (332146): Worst-case hold slack is 0.432\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     Slack       End Point TNS Clock \n",
            "\u001b[0m\u001b[0;32m    Info (332119): ========= =================== =====================\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.432               0.000 clk_74a \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.435               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.519               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.545               0.000 bridge_spiclk \n",
            "\u001b[0m\u001b[0;32mInfo (332140): No Recovery paths to report\n",
            "\u001b[0m\u001b[0;32mInfo (332140): No Removal paths to report\n",
            "\u001b[0m\u001b[0;32mInfo (332146): Worst-case minimum pulse width slack is 0.831\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     Slack       End Point TNS Clock \n",
            "\u001b[0m\u001b[0;32m    Info (332119): ========= =================== =====================\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.831               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     5.405               0.000 clk_74a \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     5.859               0.000 bridge_spiclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    16.383               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    68.723               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    68.757               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32mInfo (332114): Report Metastability: Found 24 synchronizer chains.\n",
            "\u001b[0m\u001b[0;32m    Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.\n",
            "\u001b[0m\u001b[0;32m    Info (332114): Number of Synchronizer Chains Found: 24\n",
            "\u001b[0m\u001b[0;32m    Info (332114): Shortest Synchronizer Chain: 2 Registers\n",
            "\u001b[0m\u001b[0;32m    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000\n",
            "\u001b[0m\u001b[0;32m    Info (332114): Worst Case Available Settling Time: 21.780 ns\n",
            "\u001b[0m\u001b[0;32mInfo: Analyzing Slow 1100mV 0C Model\n",
            "\u001b[0m\u001b[0;32mInfo (334003): Started post-fitting delay annotation\n",
            "\u001b[0m\u001b[0;32mInfo (334004): Delay annotation completed successfully\n",
            "\u001b[0m\u001b[0;36mWarning (332060): Node: io_bridge_peripheral:ibs|pmp_addr[24] was determined to be a clock but was found without an associated clock assignment.\n",
            "\u001b[0m\u001b[0;32m    Info (13166): Latch core_top:ic|bridge_rd_data[30] is being clocked by io_bridge_peripheral:ibs|pmp_addr[24]\n",
            "\u001b[0m\u001b[0;36mWarning (332060): Node: core_top:ic|aud_mclk_divider[1] was determined to be a clock but was found without an associated clock assignment.\n",
            "\u001b[0m\u001b[0;32m    Info (13166): Register core_top:ic|audgen_dac is being clocked by core_top:ic|aud_mclk_divider[1]\n",
            "\u001b[0m\u001b[0;36mWarning (332060): Node: core_top:ic|audgen_mclk was determined to be a clock but was found without an associated clock assignment.\n",
            "\u001b[0m\u001b[0;32m    Info (13166): Register core_top:ic|aud_mclk_divider[1] is being clocked by core_top:ic|audgen_mclk\n",
            "\u001b[0m\u001b[0;32mInfo (332097): The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network.\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT  from: clkin[0]  to: clkout\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk\n",
            "\u001b[0m\u001b[0;32mInfo (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.\n",
            "\u001b[0m\u001b[0;32mInfo (332146): Worst-case setup slack is 5.187\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     Slack       End Point TNS Clock \n",
            "\u001b[0m\u001b[0;32m    Info (332119): ========= =================== =====================\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     5.187               0.000 clk_74a \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    10.360               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    10.524               0.000 bridge_spiclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    52.087               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32mInfo (332146): Worst-case hold slack is 0.412\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     Slack       End Point TNS Clock \n",
            "\u001b[0m\u001b[0;32m    Info (332119): ========= =================== =====================\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.412               0.000 clk_74a \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.423               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.526               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.582               0.000 bridge_spiclk \n",
            "\u001b[0m\u001b[0;32mInfo (332140): No Recovery paths to report\n",
            "\u001b[0m\u001b[0;32mInfo (332140): No Removal paths to report\n",
            "\u001b[0m\u001b[0;32mInfo (332146): Worst-case minimum pulse width slack is 0.831\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     Slack       End Point TNS Clock \n",
            "\u001b[0m\u001b[0;32m    Info (332119): ========= =================== =====================\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.831               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     5.309               0.000 clk_74a \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     5.820               0.000 bridge_spiclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    16.360               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    68.685               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    68.711               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32mInfo (332114): Report Metastability: Found 24 synchronizer chains.\n",
            "\u001b[0m\u001b[0;32m    Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.\n",
            "\u001b[0m\u001b[0;32m    Info (332114): Number of Synchronizer Chains Found: 24\n",
            "\u001b[0m\u001b[0;32m    Info (332114): Shortest Synchronizer Chain: 2 Registers\n",
            "\u001b[0m\u001b[0;32m    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000\n",
            "\u001b[0m\u001b[0;32m    Info (332114): Worst Case Available Settling Time: 21.625 ns\n",
            "\u001b[0m\u001b[0;32mInfo: Analyzing Fast 1100mV 85C Model\n",
            "\u001b[0m\u001b[0;32mInfo (334003): Started post-fitting delay annotation\n",
            "\u001b[0m\u001b[0;32mInfo (334004): Delay annotation completed successfully\n",
            "\u001b[0m\u001b[0;36mWarning (332060): Node: io_bridge_peripheral:ibs|pmp_addr[24] was determined to be a clock but was found without an associated clock assignment.\n",
            "\u001b[0m\u001b[0;32m    Info (13166): Latch core_top:ic|bridge_rd_data[30] is being clocked by io_bridge_peripheral:ibs|pmp_addr[24]\n",
            "\u001b[0m\u001b[0;36mWarning (332060): Node: core_top:ic|aud_mclk_divider[1] was determined to be a clock but was found without an associated clock assignment.\n",
            "\u001b[0m\u001b[0;32m    Info (13166): Register core_top:ic|audgen_dac is being clocked by core_top:ic|aud_mclk_divider[1]\n",
            "\u001b[0m\u001b[0;36mWarning (332060): Node: core_top:ic|audgen_mclk was determined to be a clock but was found without an associated clock assignment.\n",
            "\u001b[0m\u001b[0;32m    Info (13166): Register core_top:ic|aud_mclk_divider[1] is being clocked by core_top:ic|audgen_mclk\n",
            "\u001b[0m\u001b[0;32mInfo (332097): The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network.\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT  from: clkin[0]  to: clkout\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk\n",
            "\u001b[0m\u001b[0;32mInfo (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.\n",
            "\u001b[0m\u001b[0;32mInfo (332146): Worst-case setup slack is 9.512\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     Slack       End Point TNS Clock \n",
            "\u001b[0m\u001b[0;32m    Info (332119): ========= =================== =====================\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     9.512               0.000 clk_74a \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    12.141               0.000 bridge_spiclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    14.611               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    62.131               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32mInfo (332146): Worst-case hold slack is 0.176\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     Slack       End Point TNS Clock \n",
            "\u001b[0m\u001b[0;32m    Info (332119): ========= =================== =====================\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.176               0.000 clk_74a \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.181               0.000 bridge_spiclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.181               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.183               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32mInfo (332140): No Recovery paths to report\n",
            "\u001b[0m\u001b[0;32mInfo (332140): No Removal paths to report\n",
            "\u001b[0m\u001b[0;32mInfo (332146): Worst-case minimum pulse width slack is 0.831\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     Slack       End Point TNS Clock \n",
            "\u001b[0m\u001b[0;32m    Info (332119): ========= =================== =====================\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.831               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     5.205               0.000 clk_74a \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     6.372               0.000 bridge_spiclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    16.988               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    69.318               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    69.332               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32mInfo (332114): Report Metastability: Found 24 synchronizer chains.\n",
            "\u001b[0m\u001b[0;32m    Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.\n",
            "\u001b[0m\u001b[0;32m    Info (332114): Number of Synchronizer Chains Found: 24\n",
            "\u001b[0m\u001b[0;32m    Info (332114): Shortest Synchronizer Chain: 2 Registers\n",
            "\u001b[0m\u001b[0;32m    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000\n",
            "\u001b[0m\u001b[0;32m    Info (332114): Worst Case Available Settling Time: 24.128 ns\n",
            "\u001b[0m\u001b[0;32mInfo: Analyzing Fast 1100mV 0C Model\n",
            "\u001b[0m\u001b[0;36mWarning (332060): Node: io_bridge_peripheral:ibs|pmp_addr[24] was determined to be a clock but was found without an associated clock assignment.\n",
            "\u001b[0m\u001b[0;32m    Info (13166): Latch core_top:ic|bridge_rd_data[30] is being clocked by io_bridge_peripheral:ibs|pmp_addr[24]\n",
            "\u001b[0m\u001b[0;36mWarning (332060): Node: core_top:ic|aud_mclk_divider[1] was determined to be a clock but was found without an associated clock assignment.\n",
            "\u001b[0m\u001b[0;32m    Info (13166): Register core_top:ic|audgen_dac is being clocked by core_top:ic|aud_mclk_divider[1]\n",
            "\u001b[0m\u001b[0;36mWarning (332060): Node: core_top:ic|audgen_mclk was determined to be a clock but was found without an associated clock assignment.\n",
            "\u001b[0m\u001b[0;32m    Info (13166): Register core_top:ic|aud_mclk_divider[1] is being clocked by core_top:ic|audgen_mclk\n",
            "\u001b[0m\u001b[0;32mInfo (332097): The following timing edges are non-unate.  The Timing Analyzer will assume pos-unate behavior for these edges in the clock network.\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT  from: clkin[0]  to: clkout\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk\n",
            "\u001b[0m\u001b[0;32m    Info (332098): Cell: ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk\n",
            "\u001b[0m\u001b[0;32mInfo (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.\n",
            "\u001b[0m\u001b[0;32mInfo (332146): Worst-case setup slack is 9.866\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     Slack       End Point TNS Clock \n",
            "\u001b[0m\u001b[0;32m    Info (332119): ========= =================== =====================\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     9.866               0.000 clk_74a \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    12.281               0.000 bridge_spiclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    14.807               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    62.802               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32mInfo (332146): Worst-case hold slack is 0.124\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     Slack       End Point TNS Clock \n",
            "\u001b[0m\u001b[0;32m    Info (332119): ========= =================== =====================\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.124               0.000 clk_74a \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.172               0.000 bridge_spiclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.172               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.172               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32mInfo (332140): No Recovery paths to report\n",
            "\u001b[0m\u001b[0;32mInfo (332140): No Removal paths to report\n",
            "\u001b[0m\u001b[0;32mInfo (332146): Worst-case minimum pulse width slack is 0.831\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     Slack       End Point TNS Clock \n",
            "\u001b[0m\u001b[0;32m    Info (332119): ========= =================== =====================\n",
            "\u001b[0m\u001b[0;32m    Info (332119):     0.831               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     5.158               0.000 clk_74a \n",
            "\u001b[0m\u001b[0;32m    Info (332119):     6.382               0.000 bridge_spiclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    16.995               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    69.323               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32m    Info (332119):    69.336               0.000 ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk \n",
            "\u001b[0m\u001b[0;32mInfo (332114): Report Metastability: Found 24 synchronizer chains.\n",
            "\u001b[0m\u001b[0;32m    Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.\n",
            "\u001b[0m\u001b[0;32m    Info (332114): Number of Synchronizer Chains Found: 24\n",
            "\u001b[0m\u001b[0;32m    Info (332114): Shortest Synchronizer Chain: 2 Registers\n",
            "\u001b[0m\u001b[0;32m    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000\n",
            "\u001b[0m\u001b[0;32m    Info (332114): Worst Case Available Settling Time: 24.372 ns\n",
            "\u001b[0m\u001b[0;32mInfo (332102): Design is not fully constrained for setup requirements\n",
            "\u001b[0m\u001b[0;32mInfo (332102): Design is not fully constrained for hold requirements\n",
            "\u001b[0m\u001b[0;32mInfo: Quartus Prime Timing Analyzer was successful. 0 errors, 17 warnings\n",
            "\u001b[0m\u001b[0;32m    Info: Peak virtual memory: 1163 megabytes\n",
            "\u001b[0m\u001b[0;32m    Info: Processing ended: Tue Jan 10 03:55:35 2023\n",
            "\u001b[0m\u001b[0;32m    Info: Elapsed time: 00:00:19\n",
            "\u001b[0m\u001b[0;32m    Info: Total CPU time (on all processors): 00:00:19\n",
            "\u001b[0m"
          ]
        }
      ]
    },
    {
      "cell_type": "code",
      "source": [
        "%cd /content/openfpga-pong/src/fpga/output_files/"
      ],
      "metadata": {
        "colab": {
          "base_uri": "https://localhost:8080/"
        },
        "id": "GilehGBOe72x",
        "outputId": "aa3d6d31-a888-4e29-9e8b-99d9e390757e"
      },
      "execution_count": 14,
      "outputs": [
        {
          "output_type": "stream",
          "name": "stdout",
          "text": [
            "/content/openfpga-pong/src/fpga/output_files\n"
          ]
        }
      ]
    },
    {
      "cell_type": "code",
      "source": [
        "fout = open(\"bitstream.rbf_r\", \"wb\")\n",
        "with open(\"ap_core.rbf\", 'rb') as f:\n",
        "    while 1:\n",
        "        byte_s = f.read(1)\n",
        "        if not byte_s:\n",
        "            break\n",
        "        byte = byte_s[0]\n",
        "        byte = ((byte & 1) << 7) | ((byte & 2) << 5) | ((byte & 4) << 3) | ((byte & 8) << 1) |((byte & 16) >> 1) | ((byte & 32) >> 3) | ((byte & 64) >> 5) | ((byte & 128) >> 7)\n",
        "        byte_n = byte.to_bytes(1,\"big\")\n",
        "        fout.write(byte_n)\n",
        "        fout.flush()\n",
        "fout.close()"
      ],
      "metadata": {
        "id": "gAvUxBLPe9ll"
      },
      "execution_count": 15,
      "outputs": []
    }
  ]
}