diff --git a/CorebootModulePkg/CbSupportDxe/CbSupportDxe.c b/CorebootModulePkg/CbSupportDxe/CbSupportDxe.c index 24bacf815c02..223ba503b97e 100755 --- a/CorebootModulePkg/CbSupportDxe/CbSupportDxe.c +++ b/CorebootModulePkg/CbSupportDxe/CbSupportDxe.c @@ -140,14 +140,14 @@ CbDxeEntryPoint ( // // Report MMIO/IO Resources // - Status = CbReserveResourceInGcd (TRUE, EfiGcdMemoryTypeMemoryMappedIo, 0xFEE00000, SIZE_1MB, 0, SystemTable); // LAPIC - ASSERT_EFI_ERROR (Status); + //Status = CbReserveResourceInGcd (TRUE, EfiGcdMemoryTypeMemoryMappedIo, 0xFEE00000, SIZE_1MB, 0, SystemTable); // LAPIC + //ASSERT_EFI_ERROR (Status); - Status = CbReserveResourceInGcd (TRUE, EfiGcdMemoryTypeMemoryMappedIo, 0xFEC00000, SIZE_4KB, 0, SystemTable); // IOAPIC - ASSERT_EFI_ERROR (Status); + //Status = CbReserveResourceInGcd (TRUE, EfiGcdMemoryTypeMemoryMappedIo, 0xFEC00000, SIZE_4KB, 0, SystemTable); // IOAPIC + //ASSERT_EFI_ERROR (Status); - Status = CbReserveResourceInGcd (TRUE, EfiGcdMemoryTypeMemoryMappedIo, 0xFED00000, SIZE_1KB, 0, SystemTable); // HPET - ASSERT_EFI_ERROR (Status); + //Status = CbReserveResourceInGcd (TRUE, EfiGcdMemoryTypeMemoryMappedIo, 0xFED00000, SIZE_1KB, 0, SystemTable); // HPET + //ASSERT_EFI_ERROR (Status); // // Find the system table information guid hob diff --git a/CorebootModulePkg/CbSupportPei/CbSupportPei.c b/CorebootModulePkg/CbSupportPei/CbSupportPei.c index 831de89b21d1..e7905f87c307 100755 --- a/CorebootModulePkg/CbSupportPei/CbSupportPei.c +++ b/CorebootModulePkg/CbSupportPei/CbSupportPei.c @@ -141,7 +141,7 @@ CbPeiReportRemainedFvs ( } /** - Based on memory base, size and type, build resource descripter HOB. + Based on memory base, size and type, build resource descriptor HOB. @param Base Memory base address. @param Size Memory size. @@ -381,7 +381,7 @@ CbPeiEntryPoint ( SmbiosTableSize = 0; Status = CbParseAcpiTable (&pAcpiTable, &AcpiTableSize); if (EFI_ERROR (Status)) { - // ACPI table is oblidgible + // ACPI table is obligable DEBUG ((EFI_D_ERROR, "Failed to find the required acpi table\n")); ASSERT (FALSE); } diff --git a/CorebootModulePkg/Include/Library/CbParseLib.h b/CorebootModulePkg/Include/Library/CbParseLib.h index 12dd4fa979aa..9214669a439d 100644 --- a/CorebootModulePkg/Include/Library/CbParseLib.h +++ b/CorebootModulePkg/Include/Library/CbParseLib.h @@ -25,7 +25,7 @@ typedef RETURN_STATUS \ @param Tag The tag id to be found @retval NULL The Tag is not found. - @retval Others The poiter to the record found. + @retval Others The pointer to the record found. **/ VOID * @@ -114,7 +114,7 @@ CbParseSmbiosTable ( @param pPmCtrlReg Pointer to the address of power management control register @param pPmTimerReg Pointer to the address of power management timer register @param pResetReg Pointer to the address of system reset register - @param pResetValue Pointer to the value to be writen to the system reset register + @param pResetValue Pointer to the value to be written to the system reset register @param pPmEvtReg Pointer to the address of power management event register @param pPmGpeEnReg Pointer to the address of power management GPE enable register @@ -139,7 +139,7 @@ CbParseFadtInfo ( @param pRegBase Pointer to the base address of serial port registers @param pRegAccessType Pointer to the access type of serial port registers @param pRegWidth Pointer to the register width in bytes - @param pBaudrate Pointer to the serial port baudrate + @param pBaudrate Pointer to the serial port baud rate @param pInputHertz Pointer to the input clock frequency @param pUartPciAddr Pointer to the UART PCI bus, dev and func address diff --git a/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c index ca6db2306ac4..2923e21522e5 100644 --- a/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c +++ b/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c @@ -23,12 +23,12 @@ #include // -// PCI Defintions. +// PCI Definitions. // #define PCI_BRIDGE_32_BIT_IO_SPACE 0x01 // -// 16550 UART register offsets and bitfields +// 16550 UART register offsets and bit fields // #define R_UART_RXBUF 0 #define R_UART_TXBUF 0 @@ -154,7 +154,7 @@ SerialPortLibUpdatePciRegister16 ( @param Value The value to program into the PCI Configuration Register. @param Mask Bitmask of the bits to check and update in the PCI configuration register. - @return The Secondary bus number that is actually programed into the PCI to PCI Bridge device. + @return The Secondary bus number that is actually programmed into the PCI to PCI Bridge device. **/ UINT32 @@ -451,7 +451,7 @@ SerialPortWritable ( // 0 0 No cable connected. Transmit // 0 1 No cable connected. Transmit // 1 0 Cable connected, but not clear to send. Wait - // 1 1 Cable connected, and clar to send. Transmit + // 1 1 Cable connected, and clear to send. Transmit // return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) != (B_UART_MSR_DSR)); } @@ -722,7 +722,7 @@ SerialPortRead ( /** Polls a serial device to see if there is any data waiting to be read. - Polls aserial device to see if there is any data waiting to be read. + Polls a serial device to see if there is any data waiting to be read. If there is data waiting to be read from the serial device, then TRUE is returned. If there is no data waiting to be read from the serial device, then FALSE is returned. @@ -903,7 +903,7 @@ SerialPortGetControl ( } /** - Sets the baud rate, receive FIFO depth, transmit/receice time out, parity, + Sets the baud rate, receive FIFO depth, transmit/receive time out, parity, data bits, and stop bits on a serial device. @param BaudRate The requested baud rate. A BaudRate value of 0 will use the diff --git a/CorebootModulePkg/Library/CbParseLib/CbParseLib.c b/CorebootModulePkg/Library/CbParseLib/CbParseLib.c index 0909b0f49202..38d0923422cf 100644 --- a/CorebootModulePkg/Library/CbParseLib/CbParseLib.c +++ b/CorebootModulePkg/Library/CbParseLib/CbParseLib.c @@ -30,7 +30,7 @@ @param val The pointer to packed data. - @return the UNIT64 value after convertion. + @return the UNIT64 value after conversion. **/ UINT64 @@ -90,7 +90,7 @@ CbCheckSum16 ( @param Tag The tag id to be found @retval NULL The Tag is not found. - @retval Others The poiter to the record found. + @retval Others The pointer to the record found. **/ VOID * @@ -383,7 +383,7 @@ CbParseSmbiosTable ( @param pPmCtrlReg Pointer to the address of power management control register @param pPmTimerReg Pointer to the address of power management timer register @param pResetReg Pointer to the address of system reset register - @param pResetValue Pointer to the value to be writen to the system reset register + @param pResetValue Pointer to the value to be written to the system reset register @param pPmEvtReg Pointer to the address of power management event register @param pPmGpeEnReg Pointer to the address of power management GPE enable register @@ -531,7 +531,7 @@ CbParseFadtInfo ( @param pRegBase Pointer to the base address of serial port registers @param pRegAccessType Pointer to the access type of serial port registers @param pRegWidth Pointer to the register width in bytes - @param pBaudrate Pointer to the serial port baudrate + @param pBaudrate Pointer to the serial port baud rate @param pInputHertz Pointer to the input clock frequency @param pUartPciAddr Pointer to the UART PCI bus, dev and func address diff --git a/CorebootModulePkg/SataControllerDxe/SataController.h b/CorebootModulePkg/SataControllerDxe/SataController.h index e76df748d733..1ef455561554 100644 --- a/CorebootModulePkg/SataControllerDxe/SataController.h +++ b/CorebootModulePkg/SataControllerDxe/SataController.h @@ -91,7 +91,7 @@ typedef struct _EFI_SATA_CONTROLLER_PRIVATE_DATA { UINT8 DeviceCount; // - // The highest disqulified mode for each attached device, + // The highest disqualified mode for each attached device, // From ATA/ATAPI spec, if a mode is not supported, // the modes higher than it is also not supported // diff --git a/CorebootModulePkg/SecCore/Ia32/Stack.S b/CorebootModulePkg/SecCore/Ia32/Stack.S index cd492404a0a3..6a8e0e4b1537 100644 --- a/CorebootModulePkg/SecCore/Ia32/Stack.S +++ b/CorebootModulePkg/SecCore/Ia32/Stack.S @@ -11,7 +11,7 @@ # # Abstract: # -# Switch the stack from temporary memory to permenent memory. +# Switch the stack from temporary memory to permanent memory. # #------------------------------------------------------------------------------ @@ -36,20 +36,20 @@ ASM_PFX(SecSwitchStack): # # !!CAUTION!! this function address's is pushed into stack after - # migration of whole temporary memory, so need save it to permenent + # migration of whole temporary memory, so need save it to permanent # memory at first! # movl 20(%esp), %ebx # Save the first parameter movl 24(%esp), %ecx # Save the second parameter # - # Save this function's return address into permenent memory at first. - # Then, Fixup the esp point to permenent memory + # Save this function's return address into permanent memory at first. + # Then, Fixup the esp point to permanent memory # movl %esp, %eax subl %ebx, %eax addl %ecx, %eax - movl 0(%esp), %edx # copy pushed register's value to permenent memory + movl 0(%esp), %edx # copy pushed register's value to permanent memory movl %edx, 0(%eax) movl 4(%esp), %edx movl %edx, 4(%eax) @@ -57,17 +57,17 @@ ASM_PFX(SecSwitchStack): movl %edx, 8(%eax) movl 12(%esp), %edx movl %edx, 12(%eax) - movl 16(%esp), %edx # Update this function's return address into permenent memory + movl 16(%esp), %edx # Update this function's return address into permanent memory movl %edx, 16(%eax) - movl %eax, %esp # From now, esp is pointed to permenent memory + movl %eax, %esp # From now, esp is pointed to permanent memory # - # Fixup the ebp point to permenent memory + # Fixup the ebp point to permanent memory # movl %ebp, %eax subl %ebx, %eax addl %ecx, %eax - movl %eax, %ebp # From now, ebp is pointed to permenent memory + movl %eax, %ebp # From now, ebp is pointed to permanent memory popl %edx popl %ecx diff --git a/CorebootModulePkg/SecCore/Ia32/Stack.asm b/CorebootModulePkg/SecCore/Ia32/Stack.asm index 9d1ed153e121..cdddc5433f7a 100644 --- a/CorebootModulePkg/SecCore/Ia32/Stack.asm +++ b/CorebootModulePkg/SecCore/Ia32/Stack.asm @@ -11,7 +11,7 @@ ; ; Abstract: ; -; Switch the stack from temporary memory to permenent memory. +; Switch the stack from temporary memory to permanent memory. ; ;------------------------------------------------------------------------------ @@ -38,7 +38,7 @@ SecSwitchStack PROC ; ; !!CAUTION!! this function address's is pushed into stack after - ; migration of whole temporary memory, so need save it to permenent + ; migration of whole temporary memory, so need save it to permanent ; memory at first! ; @@ -46,13 +46,13 @@ SecSwitchStack PROC mov ecx, [esp + 24] ; Save the second parameter ; - ; Save this function's return address into permenent memory at first. - ; Then, Fixup the esp point to permenent memory + ; Save this function's return address into permanent memory at first. + ; Then, Fixup the esp point to permanent memory ; mov eax, esp sub eax, ebx add eax, ecx - mov edx, dword ptr [esp] ; copy pushed register's value to permenent memory + mov edx, dword ptr [esp] ; copy pushed register's value to permanent memory mov dword ptr [eax], edx mov edx, dword ptr [esp + 4] mov dword ptr [eax + 4], edx @@ -60,17 +60,17 @@ SecSwitchStack PROC mov dword ptr [eax + 8], edx mov edx, dword ptr [esp + 12] mov dword ptr [eax + 12], edx - mov edx, dword ptr [esp + 16] ; Update this function's return address into permenent memory + mov edx, dword ptr [esp + 16] ; Update this function's return address into permanent memory mov dword ptr [eax + 16], edx - mov esp, eax ; From now, esp is pointed to permenent memory + mov esp, eax ; From now, esp is pointed to permanent memory ; - ; Fixup the ebp point to permenent memory + ; Fixup the ebp point to permanent memory ; mov eax, ebp sub eax, ebx add eax, ecx - mov ebp, eax ; From now, ebp is pointed to permenent memory + mov ebp, eax ; From now, ebp is pointed to permanent memory pop edx pop ecx diff --git a/CorebootModulePkg/SecCore/Ia32/Stack.nasm b/CorebootModulePkg/SecCore/Ia32/Stack.nasm index f3362f6045d6..c04d2e08ac70 100644 --- a/CorebootModulePkg/SecCore/Ia32/Stack.nasm +++ b/CorebootModulePkg/SecCore/Ia32/Stack.nasm @@ -64,7 +64,7 @@ ASM_PFX(SecSwitchStack): mov esp, eax ; From now, esp is pointed to permanent memory ; - ; Fixup the ebp point to permenent memory + ; Fixup the ebp point to permanent memory ; mov eax, ebp sub eax, ebx diff --git a/CorebootModulePkg/SecCore/SecMain.c b/CorebootModulePkg/SecCore/SecMain.c index 7ce0463d9880..4fa5f2176750 100644 --- a/CorebootModulePkg/SecCore/SecMain.c +++ b/CorebootModulePkg/SecCore/SecMain.c @@ -57,7 +57,7 @@ SecStartupPhase2( @param SizeOfRam Size of the temporary memory available for use. - @param TempRamBase Base address of tempory ram + @param TempRamBase Base address of temporary ram @param BootFirmwareVolume Base address of the Boot Firmware Volume. **/ VOID @@ -276,8 +276,8 @@ SecTemporaryRamSupport ( // // SecSwitchStack function must be invoked after the memory migration - // immediatly, also we need fixup the stack change caused by new call into - // permenent memory. + // immediately, also we need fixup the stack change caused by new call into + // permanent memory. // SecSwitchStack ( (UINT32) (UINTN) OldStack, diff --git a/CorebootModulePkg/SecCore/SecMain.h b/CorebootModulePkg/SecCore/SecMain.h index 7bc991ab5f24..fd20cd39b46b 100644 --- a/CorebootModulePkg/SecCore/SecMain.h +++ b/CorebootModulePkg/SecCore/SecMain.h @@ -91,7 +91,7 @@ SecTemporaryRamSupport ( the control is transferred to this function. @param SizeOfRam Size of the temporary memory available for use. - @param TempRamBase Base address of tempory ram + @param TempRamBase Base address of temporary ram @param BootFirmwareVolume Base address of the Boot Firmware Volume. **/ VOID diff --git a/CorebootPayloadPkg/Contributions.txt b/CorebootPayloadPkg/Contributions.txt new file mode 100644 index 000000000000..d034120f17da --- /dev/null +++ b/CorebootPayloadPkg/Contributions.txt @@ -0,0 +1,218 @@ + +====================== += Code Contributions = +====================== + +To make a contribution to a TianoCore project, follow these steps. +1. Create a change description in the format specified below to + use in the source control commit log. +2. Your commit message must include your "Signed-off-by" signature, + and "Contributed-under" message. +3. Your "Contributed-under" message explicitly states that the + contribution is made under the terms of the specified + contribution agreement. Your "Contributed-under" message + must include the name of contribution agreement and version. + For example: Contributed-under: TianoCore Contribution Agreement 1.0 + The "TianoCore Contribution Agreement" is included below in + this document. +4. Submit your code to the TianoCore project using the process + that the project documents on its web page. If the process is + not documented, then submit the code on development email list + for the project. +5. It is preferred that contributions are submitted using the same + copyright license as the base project. When that is not possible, + then contributions using the following licenses can be accepted: + * BSD (2-clause): http://opensource.org/licenses/BSD-2-Clause + * BSD (3-clause): http://opensource.org/licenses/BSD-3-Clause + * MIT: http://opensource.org/licenses/MIT + * Python-2.0: http://opensource.org/licenses/Python-2.0 + * Zlib: http://opensource.org/licenses/Zlib + + Contributions of code put into the public domain can also be + accepted. + + Contributions using other licenses might be accepted, but further + review will be required. + +===================================================== += Change Description / Commit Message / Patch Email = +===================================================== + +Your change description should use the standard format for a +commit message, and must include your "Signed-off-by" signature +and the "Contributed-under" message. + +== Sample Change Description / Commit Message = + +=== Start of sample patch email message === + +From: Contributor Name +Subject: [PATCH] CodeModule: Brief-single-line-summary + +Full-commit-message + +Contributed-under: TianoCore Contribution Agreement 1.0 +Signed-off-by: Contributor Name +--- + +An extra message for the patch email which will not be considered part +of the commit message can be added here. + +Patch content inline or attached + +=== End of sample patch email message === + +=== Notes for sample patch email === + +* The first line of commit message is taken from the email's subject + line following [PATCH]. The remaining portion of the commit message + is the email's content until the '---' line. +* git format-patch is one way to create this format + +=== Definitions for sample patch email === + +* "CodeModule" is a short identifier for the affected code. For + example MdePkg, or MdeModulePkg UsbBusDxe. +* "Brief-single-line-summary" is a short summary of the change. +* The entire first line should be less than ~70 characters. +* "Full-commit-message" a verbose multiple line comment describing + the change. Each line should be less than ~70 characters. +* "Contributed-under" explicitly states that the contribution is + made under the terms of the contribution agreement. This + agreement is included below in this document. +* "Signed-off-by" is the contributor's signature identifying them + by their real/legal name and their email address. + +======================================== += TianoCore Contribution Agreement 1.0 = +======================================== + +INTEL CORPORATION ("INTEL") MAKES AVAILABLE SOFTWARE, DOCUMENTATION, +INFORMATION AND/OR OTHER MATERIALS FOR USE IN THE TIANOCORE OPEN SOURCE +PROJECT (COLLECTIVELY "CONTENT"). USE OF THE CONTENT IS GOVERNED BY THE +TERMS AND CONDITIONS OF THIS AGREEMENT BETWEEN YOU AND INTEL AND/OR THE +TERMS AND CONDITIONS OF LICENSE AGREEMENTS OR NOTICES INDICATED OR +REFERENCED BELOW. BY USING THE CONTENT, YOU AGREE THAT YOUR USE OF THE +CONTENT IS GOVERNED BY THIS AGREEMENT AND/OR THE TERMS AND CONDITIONS +OF ANY APPLICABLE LICENSE AGREEMENTS OR NOTICES INDICATED OR REFERENCED +BELOW. IF YOU DO NOT AGREE TO THE TERMS AND CONDITIONS OF THIS +AGREEMENT AND THE TERMS AND CONDITIONS OF ANY APPLICABLE LICENSE +AGREEMENTS OR NOTICES INDICATED OR REFERENCED BELOW, THEN YOU MAY NOT +USE THE CONTENT. + +Unless otherwise indicated, all Content made available on the TianoCore +site is provided to you under the terms and conditions of the BSD +License ("BSD"). A copy of the BSD License is available at +http://opensource.org/licenses/bsd-license.php +or when applicable, in the associated License.txt file. + +Certain other content may be made available under other licenses as +indicated in or with such Content. (For example, in a License.txt file.) + +You accept and agree to the following terms and conditions for Your +present and future Contributions submitted to TianoCore site. Except +for the license granted to Intel hereunder, You reserve all right, +title, and interest in and to Your Contributions. + +== SECTION 1: Definitions == +* "You" or "Contributor" shall mean the copyright owner or legal + entity authorized by the copyright owner that is making a + Contribution hereunder. All other entities that control, are + controlled by, or are under common control with that entity are + considered to be a single Contributor. For the purposes of this + definition, "control" means (i) the power, direct or indirect, to + cause the direction or management of such entity, whether by + contract or otherwise, or (ii) ownership of fifty percent (50%) + or more of the outstanding shares, or (iii) beneficial ownership + of such entity. +* "Contribution" shall mean any original work of authorship, + including any modifications or additions to an existing work, + that is intentionally submitted by You to the TinaoCore site for + inclusion in, or documentation of, any of the Content. For the + purposes of this definition, "submitted" means any form of + electronic, verbal, or written communication sent to the + TianoCore site or its representatives, including but not limited + to communication on electronic mailing lists, source code + control systems, and issue tracking systems that are managed by, + or on behalf of, the TianoCore site for the purpose of + discussing and improving the Content, but excluding + communication that is conspicuously marked or otherwise + designated in writing by You as "Not a Contribution." + +== SECTION 2: License for Contributions == +* Contributor hereby agrees that redistribution and use of the + Contribution in source and binary forms, with or without + modification, are permitted provided that the following + conditions are met: +** Redistributions of source code must retain the Contributor's + copyright notice, this list of conditions and the following + disclaimer. +** Redistributions in binary form must reproduce the Contributor's + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided + with the distribution. +* Disclaimer. None of the names of Contributor, Intel, or the names + of their respective contributors may be used to endorse or + promote products derived from this software without specific + prior written permission. +* Contributor grants a license (with the right to sublicense) under + claims of Contributor's patents that Contributor can license that + are infringed by the Contribution (as delivered by Contributor) to + make, use, distribute, sell, offer for sale, and import the + Contribution and derivative works thereof solely to the minimum + extent necessary for licensee to exercise the granted copyright + license; this patent license applies solely to those portions of + the Contribution that are unmodified. No hardware per se is + licensed. +* EXCEPT AS EXPRESSLY SET FORTH IN SECTION 3 BELOW, THE + CONTRIBUTION IS PROVIDED BY THE CONTRIBUTOR "AS IS" AND ANY + EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + CONTRIBUTOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE + CONTRIBUTION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + DAMAGE. + +== SECTION 3: Representations == +* You represent that You are legally entitled to grant the above + license. If your employer(s) has rights to intellectual property + that You create that includes Your Contributions, You represent + that You have received permission to make Contributions on behalf + of that employer, that Your employer has waived such rights for + Your Contributions. +* You represent that each of Your Contributions is Your original + creation (see Section 4 for submissions on behalf of others). + You represent that Your Contribution submissions include complete + details of any third-party license or other restriction + (including, but not limited to, related patents and trademarks) + of which You are personally aware and which are associated with + any part of Your Contributions. + +== SECTION 4: Third Party Contributions == +* Should You wish to submit work that is not Your original creation, + You may submit it to TianoCore site separately from any + Contribution, identifying the complete details of its source + and of any license or other restriction (including, but not + limited to, related patents, trademarks, and license agreements) + of which You are personally aware, and conspicuously marking the + work as "Submitted on behalf of a third-party: [named here]". + +== SECTION 5: Miscellaneous == +* Applicable Laws. Any claims arising under or relating to this + Agreement shall be governed by the internal substantive laws of + the State of Delaware or federal courts located in Delaware, + without regard to principles of conflict of laws. +* Language. This Agreement is in the English language only, which + language shall be controlling in all respects, and all versions + of this Agreement in any other language shall be for accommodation + only and shall not be binding. All communications and notices made + or given pursuant to this Agreement, and all documentation and + support to be provided, unless otherwise noted, shall be in the + English language. + diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.dec b/CorebootPayloadPkg/CorebootPayloadPkg.dec index b33b79c1d6bd..24e52a17812e 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkg.dec +++ b/CorebootPayloadPkg/CorebootPayloadPkg.dec @@ -26,7 +26,7 @@ # ## Defines the token space for the Coreboot Payload Package PCDs. # - gUEfiCorebootPayloadPkgTokenSpaceGuid = {0x1d127ea, 0xf6f1, 0x4ef6, {0x94, 0x15, 0x8a, 0x0, 0x0, 0x93, 0xf8, 0x9d}} + gUefiCorebootPayloadPkgTokenSpaceGuid = {0x1d127ea, 0xf6f1, 0x4ef6, {0x94, 0x15, 0x8a, 0x0, 0x0, 0x93, 0xf8, 0x9d}} # # Gop Temp @@ -48,7 +48,15 @@ # declaration, other packages should not. # ################################################################################ -[PcdsFixedAtBuild, PcdsPatchableInModule] +[PcdsFixedAtBuild] + # + # Binary representation of the GUID that determines the terminal type. The + # size must be exactly 16 bytes. The default value corresponds to + # EFI_VT_100_GUID. + # + gUefiCorebootPayloadPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer|{0x65, 0x60, 0xA6, 0xDF, 0x19, 0xB4, 0xD3, 0x11, 0x9A, 0x2D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}|VOID*|0x00000007 + +[PcdsPatchableInModule] [PcdsDynamic, PcdsDynamicEx] diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc index 6b16af63ba89..8755ec6543f2 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc @@ -85,7 +85,7 @@ # # Shell options: [BUILD_SHELL, FULL_BIN, MIN_BIN, NONE, UEFI] # - DEFINE SHELL_TYPE = FULL_BIN + DEFINE SHELL_TYPE = BUILD_SHELL [BuildOptions] *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES diff --git a/CorebootPayloadPkg/FbGop/FbGop.c b/CorebootPayloadPkg/FbGop/FbGop.c index 37d6def7f780..e5e0865fb109 100644 --- a/CorebootPayloadPkg/FbGop/FbGop.c +++ b/CorebootPayloadPkg/FbGop/FbGop.c @@ -528,7 +528,7 @@ FbGopChildHandleInstall ( } // - // Creat child handle and device path protocol firstly + // Create child handle and device path protocol firstly // FbGopPrivate->Handle = NULL; Status = gBS->InstallMultipleProtocolInterfaces ( @@ -559,7 +559,7 @@ FbGopChildHandleInstall ( } // - // Creat child handle and install Graphics Output Protocol,EDID Discovered/Active Protocol + // Create child handle and install Graphics Output Protocol,EDID Discovered/Active Protocol // Status = gBS->InstallMultipleProtocolInterfaces ( &FbGopPrivate->Handle, @@ -688,7 +688,7 @@ FbGopChildHandleUninstall ( /** - Release resource for biso video instance. + Release resource for BIOS video instance. @param FbGopPrivate Video child device private data structure @@ -703,7 +703,7 @@ FbGopDeviceReleaseResource ( } // - // Release all the resourses occupied by the FB_VIDEO_DEV + // Release all the resources occupied by the FB_VIDEO_DEV // // @@ -1222,7 +1222,7 @@ FbGopVbeBltWorker ( } // // We need to fill the Virtual Screen buffer with the blt data. - // The virtual screen is upside down, as the first row is the bootom row of + // The virtual screen is upside down, as the first row is the bottom row of // the image. // if (BltOperation == EfiBltVideoToBltBuffer) { diff --git a/CorebootPayloadPkg/FbGop/FbGop.h b/CorebootPayloadPkg/FbGop/FbGop.h index 4445f5c73045..bd2263f0e668 100644 --- a/CorebootPayloadPkg/FbGop/FbGop.h +++ b/CorebootPayloadPkg/FbGop/FbGop.h @@ -205,7 +205,7 @@ FbGopCheckForVbe ( /** - Release resource for biso video instance. + Release resource for BIOS video instance. @param FbGopPrivate Video child device private data structure @@ -311,9 +311,9 @@ FbGopGraphicsOutputVbeBlt ( /** - Grahpics Output protocol instance to block transfer for VGA device. + Graphics Output protocol instance to block transfer for VGA device. - @param This Pointer to Grahpics Output protocol instance + @param This Pointer to Graphics Output protocol instance @param BltBuffer The data to transfer to screen @param BltOperation The operation to perform @param SourceX The X coordinate of the source for BltOperation @@ -394,7 +394,7 @@ FbGopChildHandleUninstall ( ); /** - Release resource for biso video instance. + Release resource for BIOS video instance. @param FbGopPrivate Video child device private data structure diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h index 4852ed0d8d29..c777cdbac151 100644 --- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h +++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h @@ -42,7 +42,7 @@ ScanForRootBridges ( assigned to any subordinate bus found behind any PCI bridge hanging off this root bus. - The caller is repsonsible for ensuring that + The caller is responsible for ensuring that RootBusNumber <= MaxSubBusNumber. If RootBusNumber equals MaxSubBusNumber, then the root bus has no room for subordinate buses. diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c index b0a636155713..f7e1369a0869 100644 --- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -70,7 +70,7 @@ CB_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = { assigned to any subordinate bus found behind any PCI bridge hanging off this root bus. - The caller is repsonsible for ensuring that + The caller is responsible for ensuring that RootBusNumber <= MaxSubBusNumber. If RootBusNumber equals MaxSubBusNumber, then the root bus has no room for subordinate buses. diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c index 6d94ff72c956..c1babe8dc199 100644 --- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c +++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c @@ -146,7 +146,7 @@ PcatPciRootBridgeBarExisted ( } /** - Parse PCI bar and collect the assigned PCI resouce information. + Parse PCI bar and collect the assigned PCI resource information. @param[in] Command Supported attributes. @@ -392,7 +392,7 @@ ScanForRootBridges ( // if (Pci.Bridge.SubordinateBus > SubBus) { // - // If the suborinate bus number of the PCI-PCI bridge is greater + // If the subordinate bus number of the PCI-PCI bridge is greater // than the PCI root bridge's current subordinate bus number, // then update the PCI root bridge's subordinate bus number // diff --git a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c index 7e92441da11f..cf36472243c1 100644 --- a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c +++ b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c @@ -16,6 +16,65 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #include "PlatformBootManager.h" #include "PlatformConsole.h" +#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >> 8) } + +#pragma pack (1) +typedef struct { + VENDOR_DEVICE_PATH SerialDxe; + UART_DEVICE_PATH Uart; + VENDOR_DEFINED_DEVICE_PATH TermType; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_SERIAL_CONSOLE; +#pragma pack () + +#define SERIAL_DXE_FILE_GUID { \ + 0xD3987D4B, 0x971A, 0x435F, \ + { 0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41 } \ + } + +STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = { + // + // VENDOR_DEVICE_PATH SerialDxe + // + { + { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) }, + SERIAL_DXE_FILE_GUID + }, + + // + // UART_DEVICE_PATH Uart + // + { + { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) }, + 0, // Reserved + 0, // BaudRate + 0, // DataBits + 0, // Parity + 0 // StopBits + }, + + // + // VENDOR_DEFINED_DEVICE_PATH TermType + // + { + { + MESSAGING_DEVICE_PATH, MSG_VENDOR_DP, + DP_NODE_LEN (VENDOR_DEFINED_DEVICE_PATH) + } + // + // Guid to be filled in dynamically + // + }, + + // + // EFI_DEVICE_PATH_PROTOCOL End + // + { + END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, + DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL) + } +}; + VOID InstallReadyToLock ( VOID @@ -188,6 +247,22 @@ PlatformBootManagerBeforeConsole ( EfiBootManagerGetBootManagerMenu (&BootOption); EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumber, 0, &Down, NULL); + mSerialConsole.Uart.BaudRate = PcdGet64 (PcdUartDefaultBaudRate); + mSerialConsole.Uart.DataBits = PcdGet8 (PcdUartDefaultDataBits); + mSerialConsole.Uart.Parity = PcdGet8 (PcdUartDefaultParity); + mSerialConsole.Uart.StopBits = PcdGet8 (PcdUartDefaultStopBits); + // + // Add the hardcoded serial console device path to ConIn, ConOut, ErrOut. + // + CopyGuid (&mSerialConsole.TermType.Guid, + PcdGetPtr (PcdTerminalTypeGuidBuffer)); + EfiBootManagerUpdateConsoleVariable (ConIn, + (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL); + EfiBootManagerUpdateConsoleVariable (ConOut, + (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL); + EfiBootManagerUpdateConsoleVariable (ErrOut, + (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL); + // // Install ready to lock. // This needs to be done before option rom dispatched. @@ -208,7 +283,7 @@ PlatformBootManagerBeforeConsole ( Signal console ready platform customized event; Run diagnostics like memory testing; Connect certain devices; - Dispatch aditional option roms. + Dispatch additional option roms. **/ VOID EFIAPI diff --git a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf index 9e8ae9b36a0e..0c62cbcead35 100644 --- a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf +++ b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf @@ -78,3 +78,4 @@ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits + gUefiCorebootPayloadPkgTokenSpaceGuid.PcdTerminalTypeGuidBuffer diff --git a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.c b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.c index 4786170bb4e1..d8dbd3be13a3 100644 --- a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.c +++ b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.c @@ -241,7 +241,7 @@ GetGopDevicePath ( ) == 0) { // // In current implementation, we only enable one of the child handles - // as console device, i.e. sotre one of the child handle's device + // as console device, i.e. store one of the child handle's device // path to variable "ConOut" // In future, we could select all child handles to be console device // diff --git a/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c b/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c index b1cfb8e2c09e..837532373ee1 100644 --- a/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c +++ b/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c @@ -34,7 +34,7 @@ typedef struct { /** Performs platform specific initialization required for the CPU to access the hardware associated with a SerialPortLib instance. This function does - not intiailzie the serial port hardware itself. Instead, it initializes + not initialize the serial port hardware itself. Instead, it initializes hardware devices that are required for the CPU to access the serial port hardware. This function may be called more than once. diff --git a/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c b/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c index b7d6f385fe8f..2a688f95b446 100644 --- a/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c +++ b/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c @@ -163,7 +163,7 @@ EnterS3WithImmediateWake ( } /** - This function causes a systemwide reset. The exact type of the reset is + This function causes a system wide reset. The exact type of the reset is defined by the EFI_GUID that follows the Null-terminated Unicode string passed into ResetData. If the platform does not recognize the EFI_GUID in ResetData the platform must pick a supported reset type to perform.The platform may diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c index 857918df18b0..6e9578da15f6 100644 --- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c @@ -142,10 +142,10 @@ PcRtcInit ( RtcRead (RTC_ADDRESS_REGISTER_C); // - // Clear RTC register D + // Clear RTC register D - all bits except VRT (Valid RAM and Time) // - RegisterD.Data = RTC_INIT_REGISTER_D; - RtcWrite (RTC_ADDRESS_REGISTER_D, RegisterD.Data); + RegisterD.Data = RtcRead (RTC_ADDRESS_REGISTER_D); + RtcWrite (RTC_ADDRESS_REGISTER_D, RegisterD.Data & 0x80); // // Wait for up to 0.1 seconds for the RTC to be updated diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h index ba6092de45ea..8800d2ab906d 100644 --- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h @@ -78,7 +78,7 @@ extern PC_RTC_MODULE_GLOBALS mModuleGlobal; // // Register initial values // -#define RTC_INIT_REGISTER_A 0x26 +#define RTC_INIT_REGISTER_A 0x6 #define RTC_INIT_REGISTER_B 0x02 #define RTC_INIT_REGISTER_D 0x0 diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c index a61a35e9eeb5..83dd344aa581 100644 --- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c @@ -114,7 +114,7 @@ PcRtcEfiSetWakeupTime ( /** The user Entry Point for PcRTC module. - This is the entrhy point for PcRTC module. It installs the UEFI runtime service + This is the entry point for PcRTC module. It installs the UEFI runtime service including GetTime(),SetTime(),GetWakeupTime(),and SetWakeupTime(). @param ImageHandle The firmware allocated handle for the EFI image. diff --git a/apu2-build.sh b/apu2-build.sh new file mode 100755 index 000000000000..8959e463fb79 --- /dev/null +++ b/apu2-build.sh @@ -0,0 +1,9 @@ +#!/bin/bash +# build -a IA32 -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -b DEBUG -t GCC5 +build -a IA32 -a X64 -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -b DEBUG -t GCC5 +cp Build/CorebootPayloadPkgX64/DEBUG_GCC5/FV/UEFIPAYLOAD.fd ../apu2_fw_rel/apu2/coreboot/ +cd ../apu2_fw_rel +./apu2/apu2-documentation/scripts/apu2_fw_rel.sh build-ml +read -n 1 -s -p "Press any key to continue with flashing recent build ..." +./apu2/apu2-documentation/scripts/apu2_fw_rel.sh flash-ml root@$1 +cd ../edk2